Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03, Technical Manual

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III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
B-III-4-8
EPSON
S1C33L03 FUNCTION PART
When OUTINVx = "0" (active high):
The timer outputs a low level until the counter becomes equal to the comparison data A set in the CRxA
register. When the counter is incremented to the next value from the comparison data A, the output pin goes
high and a comparison A interrupt occurs. When the counter becomes equal to the comparison data B set in
the CRxB register, the counter is reset and the output pin goes low. At the same time a comparison B
interrupt occurs.
When OUTINVx = "1" (active low):
The timer outputs a high level until the counter becomes equal to the comparison data A set in the CRxA
register. When the counter is incremented to the next value from the comparison data A, the output pin goes
low and a comparison A interrupt occurs. When the counter becomes equal to the comparison data B set in
the CRxB register, the counter is reset and the output pin goes high. At the same time a comparison B
interrupt occurs.
Setting clock output fine mode
By default (after an initial reset), the clock output signal changes at the rising edge of the input clock when
CRxA[15:0] becomes equal to TCx[15:0].
In fine mode, the output signal changes according to CRxA[0] when CRxA[15:1] becomes equal to
TCx[14:0].
When CRxA[0] is "0", the output signal changes at the rising edge of the input clock.
When CRxA[0] is "1", the output signal changes at the falling edge of the input clock a half cycle from the
default setting.
Example) CRxA = 3, CRxB = 5
Input clock
Counter value
Comparison match A signal
Comparison match B signal
TMx output (when OUTINVx = "0")
TMx output (when OUTINVx = "1")
0 1 2 3 4 5 0 1 2 3 4 5 0 1
Figure 4.4 Clock Output in Fine Mode
As shown in the figure above, in fine mode the output clock duty ratio can be adjusted in the half cycle of the
input clock. However, when the CRxA value is "0", the timer outputs a pulse with a 1-cycle width as the
input clock, the same as the default setting.
In fine mode, the maximum value of CRxB is 2
15
- 1 = 32,767 and the range of CRxA that can be set is 0 to (2
×
CRxB - 1).
The fine mode is set by the following registers:
Timer 0 fine mode selection: SELFM0 (D6) / 16-bit timer 0 control register (0x48186)
Timer 1 fine mode selection: SELFM1 (D6) / 16-bit timer 1 control register (0x4818E)
Timer 2 fine mode selection: SELFM2 (D6) / 16-bit timer 2 control register (0x48196)
Timer 3 fine mode selection: SELFM3 (D6) / 16-bit timer 3 control register (0x4819E)
Timer 4 fine mode selection: SELFM4 (D6) / 16-bit timer 4 control register (0x481A6)
Timer 5 fine mode selection: SELFM5 (D6) / 16-bit timer 5 control register (0x481AE)
When "1" is written to the SELFMx bit, fine mode is set. At initial reset, the fine mode is disabled.
Precautions
1) If a same value is set to the comparison data A and B registers, a hazard may be generated in the output
signal. Therefore, do not set the comparison registers as A = B.
There is no problem when the interrupt function only is used.
2) When using the output clock, set the comparison data registers as A
≥
0 and B
≥
1. The minimum settings
are A = 0 and B = 1. In this case, the timer output clock cycle is the input clock
×
1/2.
3) When the comparison data registers are set as A > B, no comparison A signal is generated. In this case,
the output signal is fixed at the off level.