Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual Download Page 200

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II CORE BLOCK: BCU (Bus Control Unit)

B-II-4-24

EPSON

S1C33L03 FUNCTION PART

DRAM Direct Interface

Outline of DRAM Interface

The BCU incorporates a DRAM direct interface that allows DRAM to be connected directly to areas 8 and 7 or

areas 14 and 13. This interface supports the 2CAS method, so that column addresses can be set at between 8 and 11

bits. In addition, this interface supports a fast-page or an EDO-page mode (EDO DRAM directly connectable to

areas) as well as random cycles. The refresh method (CAS-before-RAS refresh or self-refresh) and timing

conditions (e.g., number of RAS/CAS cycles and number of precharge cycles) can be programmed using a control

bit.

When selecting areas 8 and 7 or areas 14 and 13 to be used for DRAM, it depends on chip-enable settings using

CEFUNC (D9) / DRAM timing set-up register (0x48130).

CEFUNC = "00": DRAM can be connected to areas 8 and 7 (default)

#CE8 and #CE7 function as #RAS0 and #RAS1, respectively.

CEFUNC

≠

"00": DRAM can be connected to areas 14 and 13.

#CE14 and #CE13 function as #RAS2 and #RAS3, respectively.

Figure 4.27 shows a sample DRAM connection. Table 4.15 and Table 4.16 show examples of connectable DRAMs

and typical configurations.

A[9:1]

D[15:0]

#RD

#RASx(#CEx)

#HCAS

#LCAS

#WE

S1C33

A[8:0]
I/O[15:0]

#OE
#RAS
#HCAS
#LCAS
#WE

4M DRAM

(256K x 16)

∗

x: 14, 13, 8 or 7

Figure 4.27 Sample DRAM Connection

Table 4.15 Connectable DRAM Example

DRAM

Number of

devices

Number of

Row bits

Number of

Column bits

Memory size

1M (64K x 16)

128K bytes

4M (256K x 16)

512K bytes

16M (1M x 16)

2M bytes

Table 4.16 DRAM Configuration Example (areas 7 and 8 only)

Area 7

Area 8

Total memory size

1 I/O

DRAM (1M)

1M bits

(128K bytes)

2 I/O

DRAM (4M)

4M bits

(512K bytes)

3 I/O

DRAM (16M)

16M bits

(2M bytes)

4 DRAM (1M)

DRAM (1M)

2M bits

(256K bytes)

5 DRAM (4M)

DRAM (4M)

8M bits

(1M bytes)

6 DRAM (16M)

DRAM (16M)

32M bits

(4M bytes)

Also, the S1C33L03 provides an SDRAM direct interface. Refer to "VI SDRAM Controller Block" for details.

Summary of Contents for CMOS 32-Bit Single Chip Microcomputer S1C33L03

Page 1: ...Technical Manual CMOS 32 BIT SINGLE CHIP MICROCOMPUTER S1C33L03 PRODUCT PART S1C33L03 FUNCTION PART S1C33L03 MF1574 01 ...

Page 2: ...uiring high level reliability such as medical products Moreover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to...

Page 3: ...E TCP BD 2 directions 0F Tape reel FRONT 0G TCP BT 4 directions 0H TCP BD 4 directions 0J TCP SL 2 directions 0K TCP SR 2 directions 0L Tape reel LEFT 0M TCP ST 2 directions 0N TCP SD 2 directions 0P TCP ST 4 directions 0Q TCP SD 4 directions 0R Tape reel RIGHT 99 Specs not fixed Specification Package D die form F QFP Model number Model name C microcomputer digital products Product classification ...

Page 4: ......

Page 5: ...Memory Map A 17 5 Power Down Control A 65 6 Basic External Wiring Diagram A 68 7 Precautions on Mounting A 69 8 Electrical Characteristics A 71 8 1 Absolute Maximum Rating A 71 8 2 Recommended Operating Conditions A 72 8 3 DC Characteristics A 73 8 4 Current Consumption A 75 8 5 A D Converter Characteristics A 76 8 6 AC Characteristics A 78 8 6 1 Symbol Description A 78 8 6 2 AC Characteristics Me...

Page 6: ...TECHNICAL MANUAL Appendix A Reference External Device Interface Timings A 113 A 1 DRAM 70ns A 114 A 2 DRAM 60ns A 117 A 3 ROM and Burst ROM A 121 A 4 SRAM 55ns A 123 A 5 SRAM 70ns A 125 A 6 8255A A 127 Appendix B Pin Characteristics A 128 ...

Page 7: ...ower on Reset B II 3 2 Reset Pulse B II 3 2 Boot Address B II 3 3 Notes Related to Initial Reset B II 3 3 II 4 BCU Bus Control Unit B II 4 1 Pin Assignment for External System Interface B II 4 1 I O Pin List B II 4 1 Combination of System Bus Control Signals B II 4 3 Memory Area B II 4 4 Memory Map B II 4 4 External Memory Map and Chip Enable B II 4 5 Using Internal Memory on External Memory Area ...

Page 8: ...cessing by the CPU B II 5 3 Clearing Standby Mode by Interrupts B II 5 3 Trap Table B II 5 4 Control of Maskable Interrupts B II 5 5 Structure of the Interrupt Controller B II 5 5 Processor Status Register PSR B II 5 5 Interrupt Factor Flag and Interrupt Enable Register B II 5 6 Interrupt Priority Register and Interrupt Levels B II 5 8 IDMA Invocation B II 5 9 HSDMA Invocation B II 5 11 I O Memory...

Page 9: ...grammable Timer B III 4 1 I O Pins of 16 Bit Programmable Timers B III 4 2 Uses of 16 Bit Programmable Timers B III 4 3 Control and Operation of 16 Bit Programmable Timer B III 4 4 Controlling Clock Output B III 4 7 16 Bit Programmable Timer Interrupts and DMA B III 4 9 I O Memory of 16 Bit Programmable Timers B III 4 12 Programming Notes B III 4 25 III 5 WATCHDOG TIMER B III 5 1 Configuration of ...

Page 10: ... Interface B III 8 12 Setting Asynchronous Interface B III 8 13 Control and Operation of Asynchronous Transfer B III 8 16 IrDA Interface B III 8 21 Outline of IrDA Interface B III 8 21 Setting IrDA Interface B III 8 21 Control and Operation of IrDA Interface B III 8 23 Serial Interface Interrupts and DMA B III 8 24 I O Memory of Serial Interface B III 8 28 Programming Notes B III 8 46 III 9 INPUT ...

Page 11: ...V 2 2 Programming Control Information B V 2 3 Setting the Registers in Dual Address Mode B V 2 3 Setting the Registers in Single Address Mode B V 2 6 Enabling Disabling DMA Transfer B V 2 7 Trigger Factor B V 2 8 Operation of HSDMA B V 2 9 Operation in Dual Address Mode B V 2 9 Operation in Single Address Mode B V 2 12 Timing Chart B V 2 13 Interrupt Function of HSDMA B V 2 15 I O Memory of HSDMA ...

Page 12: ...us Release Procedure B VI 2 19 I O Memory of SDRAM Interface B VI 2 21 Programming Notes B VI 2 32 Examples of SDRAM Controller Initialization Program B VI 2 33 VII LCD CONTROLLER BLOCK VII 1 INTRODUCTION B VII 1 1 VII 2 LCD CONTROLLER B VII 2 1 Overview B VII 2 1 Features B VII 2 1 Block Diagram B VII 2 3 I O Pins of the LCD Controller B VII 2 4 System Settings B VII 2 5 Setting the BCU B VII 2 5...

Page 13: ...ing and Blanking the Display B VII 2 25 Portrait Mode B VII 2 25 Power Save B VII 2 29 Controlling the GPIO Pins B VII 2 30 I O Memory of LCD Controller B VII 2 31 Programming Notes B VII 2 42 Precautions on Using ICD33 B VII 2 42 Examples of LCD Controller Setting Program B VII 2 43 APPENDIX I O MAP ...

Page 14: ......

Page 15: ...S1C33L03 PRODUCT PART ...

Page 16: ......

Page 17: ...SC CPU S1C33000 built in Basic instruction set 105 instructions 16 bit fixed size Sixteen 32 bit general purpose register 32 bit ALU and 8 bit shifter Multiplication division instructions and MAC multiplication and accumulation instruction are available 20 ns of minimum instruction execution time at 50 MHz operation Internal memory RAM 8K bytes Internal peripheral circuits Oscillation circuit High...

Page 18: ...mode and EDO page mode Supports self refresh and CAS before RAS refresh Supports SDRAM Supports SDRAM self refresh Supports burst ROM Operating conditions and power consumption Operating voltage Core VDD 1 8 V to 3 6 V I O VDDE 1 8 V to 5 5 V Operating clock frequency CPU operating clock frequency 50 MHz max core voltage 3 3 V 0 3 V LCD controller operating clock frequency 25 MHz max core voltage ...

Page 19: ... BUSREQ P34 BUSACK P35 BUSGET P31 DST 2 0 P10 12 DPCO P13 DCLK P14 T8UFx P10 13 SINx P00 P04 P27 P33 SOUTx P01 P05 P26 P16 SCLKx P02 P06 P25 P15 SRDYx P03 P07 P24 P32 FPDAT 7 4 FPDAT 3 0 GPO 6 3 FPFRAME FPLINE FPSHIFT DRDY MOD FPSHIFT2 LCDPWR S1C33L03 EXCLx P10 13 P15 P16 TMx P22 27 16 bit Programmable Timer 6 ch P00 07 P10 16 P20 27 P30 35 S1C33000 Bus Control Unit SDRAM Controller CPU Core Inter...

Page 20: ...RAS0 CE13 RAS2 SDCE0 VSS OSC2 OSC1 RESET P35 BUSACK GPIO1 P34 BUSREQ CE6 GPIO0 P33 DMAACK1 SIN3 SDA10 No 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pin name P32 DMAACK0 SRDY3 HDQM P31 BUSGET GARD GPIO2 P30 WAIT CE4 5 LCAS SDRAS HCAS SDCAS VDD P21 DWE GAAS SDWE P20 DRD SDCKE BCLK SDCLK VSS P16 EXCL5 DMAEND1 SOUT3 P15 EXCL4 DM...

Page 21: ...x48128 0 and SDRPC1 D2 0x39FFC0 0 default RAS1 Area 8 DRAM row strobe when CEFUNC 1 0 D A 9 0x48130 00 A8DRA D8 0x48128 1 and SDRPC1 D2 0x39FFC0 0 CE14 Area 14 chip enable when CEFUNC 1 0 D A 9 0x48130 01 or 1x A14DRA D8 0x48122 0 and SDRPC1 D2 0x39FFC0 0 RAS3 Area 14 DRAM row strobe when CEFUNC 1 0 D A 9 0x48130 01 or 1x A14DRA D8 0x48122 1 and SDRPC1 D2 0x39FFC0 0 SDCE1 SDRAM chip enable 1 when ...

Page 22: ...34 D4 0x402DC 1 GPIO1 LCDC general purpose I O when LCDCEN D5 0x39FFE3 1 and BREQEN D2 0x39FFFD 0 P30 WAIT CE4 5 75 I O P30 I O port when CFP30 D0 0x402DC 0 default WAIT Wait cycle request input when CFP30 D0 0x402DC 1 CE4 5 Areas 4 5 chip enable when CFP30 D0 0x402DC 1 and IOC30 D0 0x402DE 1 P20 DRD SDCKE 80 I O P20 I O port when CFP20 D0 0x402D8 0 and SDRENA D7 0x39FFC1 0 default DRD DRAM read s...

Page 23: ...FP04 D4 0x402D0 1 and CFEX4 D4 0x402DF 0 DMAACK2 HSDMA Ch 2 acknowledge output when CFEX4 D4 0x402DF 1 P06 SCLK1 DMAACK3 10 I O P06 I O port when CFP06 D6 0x402D0 0 and CFEX6 D6 0x402DF 0 default SCLK1 Serial I F Ch 1 clock input output when CFP06 D6 0x402D0 1 and CFEX6 D6 0x402DF 0 DMAACK3 HSDMA Ch 3 acknowledge output when CFEX6 D6 0x402DF 1 P15 EXCL4 DMAEND0 SCLK3 LDQM 84 I O P15 I O port when ...

Page 24: ...7 input when CFK67 D7 0x402C3 1 P00 SIN0 144 I O P00 I O port when CFP00 D0 0x402D0 0 default SIN0 Serial I F Ch 0 data input when CFP00 D0 0x402D0 1 P01 SOUT0 143 I O P01 I O port when CFP01 D1 0x402D0 0 default SOUT0 Serial I F Ch 0 data output when CFP01 D1 0x402D0 1 P02 SCLK0 142 I O P02 I O port when CFP02 D2 0x402D0 0 default SCLK0 Serial I F Ch 0 clock input output when CFP02 D2 0x402D0 1 P...

Page 25: ... D5 0x402D6 1 and SDRENA D7 0x39FFC1 0 SCLK3 Serial I F Ch 3 clock input output when SSCLK3 D2 0x402D7 1 CFP15 D5 0x402D4 0 and SDRENA D7 0x39FFC1 0 LDQM SDRAM data low byte input output mask signal when SDRENA D7 0x39FFC1 1 P16 EXCL5 DMAEND1 SOUT3 83 I O P16 I O port when CFP16 D6 0x402D4 0 default EXCL5 16 bit timer 5 event counter input when CFP16 D6 0x402D4 1 and IOC16 D6 0x402D6 0 DMAEND1 HSD...

Page 26: ...CK0 SRDY3 HDQM 73 I O P32 I O port when CFP32 D2 0x402DC 0 and SDRENA D7 0x39FFC1 0 default DMAACK0 HSDMA Ch 0 acknowledge output when CFP32 D2 0x402DC 1 and SDRENA D7 0x39FFC1 0 SRDY3 Serial I F Ch 3 ready signal input output when SSRDY3 D3 0x402D7 1 CFP32 D2 0x402DC 0 and SDRENA D7 0x39FFC1 0 HDQM SDRAM data high byte input output mask signal when SDRENA D7 0x39FFC1 1 P33 DMAACK1 SIN3 SDA10 72 I...

Page 27: ...illator or external clock input OSC2 67 O Low speed OSC1 oscillation output OSC3 129 I High speed OSC3 oscillation input crystal ceramic oscillator or external clock input OSC4 128 O High speed OSC3 oscillation output PLLS 1 0 112 113 I PLL set up pins PLLS1 PLLS0 fin fOSC3 fout fPSCIN 1 1 10 25MHz 20 50MHz 0 1 10 12 5MHz 40 50MHz 0 0 PLL is not used L PLLC 115 Capacitor connecting pin for PLL Tab...

Page 28: ...tem power supply AVDDE VDDE I O interface circuit CPU core Internal peripheral circuit VDD 1 8 to 3 6 V 1 8 to 5 5 V 1 8 to 5 5 V GND VDDE I O pins Analog circuits A D converter AVDDE VSS Figure 2 1 1 Power Supply System 2 2 Operating Voltage VDD VSS The core CPU and internal peripheral circuits operate with a voltage supplied between the VDD and VSS pins The following operating voltage can be use...

Page 29: ...m When an external clock is input to the OSC1 or OSC3 pin the clock signal level must be VDD The interface voltage level of the DSIO P10 P11 P12 P13 and P14 pins is VDD 2 4 Power Supply for Analog Circuits AVDDE The analog power supply pin AVDDE is provided separately from the VDD and VDDE pins in order that the digital circuits do not affect the analog circuit A D converter The AVDDE pin is used ...

Page 30: ...000000 External Memory External Memory External Memory External Memory Reserved For middleware use Reserved For CPU debug mode Mirror of internal peripheral circuits Mirror of internal peripheral circuits Internal peripheral circuits LCD controller SDRAM controller Mirror of internal RAM Internal RAM 8KB Figure 3 1 Memory Map Area 2 is used in debug mode only and it cannot be accessed in user mode...

Page 31: ... A 1 A 3 3 2 RAM The S1C33L03 has a built in 8KB RAM The RAM is allocated to Area 0 address 0x0000000 to address 0x0001FFF The internal RAM is a 32 bit sized device and data can be read written in 1 cycle regardless of data size byte half word or word ...

Page 32: ...ce Up to two 128M bit SDRAMs or a 256M bit SDRAM 32MB can be connected directly C33 Peripheral Block Prescaler Programmable clock generator for peripheral circuits 8 bit programmable timer 6 channels with clock output function 16 bit programmable timer 6 channels with event counter clock output and watchdog timer functions Serial interface 4 channels asynchronous mode clock synchronous mode and Ir...

Page 33: ...θ 1 0 Divided clk 1 θ 1 0 Divided clk 1 θ 1 0 Divided clk 1 θ 1 0 Divided clk 8 bit timer clock select register P16TON0 P16TS02 P16TS01 P16TS00 D7 4 D3 D2 D1 D0 reserved 16 bit timer 0 clock control 16 bit timer 0 clock division ratio selection 0 0 0 0 R W R W 0 when being read θ selected by Prescaler clock select register 0x40181 16 bit timer 0 can be used as a watchdog timer 0040147 B 1 On 0 Off...

Page 34: ...3 D2 D1 D0 reserved 16 bit timer 5 clock control 16 bit timer 5 clock division ratio selection 0 0 0 0 R W R W 0 when being read θ selected by Prescaler clock select register 0x40181 004014C B 1 On 0 Off 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 P16TS5 2 0 Division ratio θ 4096 θ 1024 θ 256 θ 64 θ 16 θ 4 θ 2 θ 1 16 bit timer 5 clock control register 1 On 0 Off P8TON1 P8TS12 P8TS11 P8TS10 P8T...

Page 35: ...n ratio θ 256 θ 128 θ 64 θ 32 θ 16 θ 8 θ 4 θ 2 TCRST TCRUN D7 2 D1 D0 reserved Clock timer reset Clock timer Run Stop control X X W R W 0 when being read 0 when being read 0040151 B 1 Reset 0 Invalid 1 Run 0 Stop Clock timer Run Stop register TCISE2 TCISE1 TCISE0 TCASE2 TCASE1 TCASE0 TCIF TCAF D7 D6 D5 D4 D3 D2 D1 D0 Clock timer interrupt factor selection Clock timer alarm factor selection Interru...

Page 36: ...r 0 to 65535 days high order 8 bits X X X X X X X X R W TCND15 TCND14 TCND13 TCND12 TCND11 TCND10 TCND9 TCND8 D7 D6 D5 D4 D3 D2 D1 D0 Clock timer day counter data high order 8 bits TCND15 MSB 0040158 B Clock timer day high order register 0 to 59 minutes Note Can be set within 0 63 TCCH5 TCCH4 TCCH3 TCCH2 TCCH1 TCCH0 D7 6 D5 D4 D3 D2 D1 D0 reserved Clock timer minute comparison data TCCH5 MSB TCCH0...

Page 37: ...ad 0 when being read 0040164 B 1 On 0 Off 1 Preset 0 Invalid 1 Run 0 Stop 8 bit timer 1 control register 0 to 255 RLD17 RLD16 RLD15 RLD14 RLD13 RLD12 RLD11 RLD10 D7 D6 D5 D4 D3 D2 D1 D0 8 bit timer 1 reload data RLD17 MSB RLD10 LSB X X X X X X X X R W 0040165 B 8 bit timer 1 reload data register 0 to 255 PTD17 PTD16 PTD15 PTD14 PTD13 PTD12 PTD11 PTD10 D7 D6 D5 D4 D3 D2 D1 D0 8 bit timer 1 counter ...

Page 38: ... when being read 0040174 B 1 On 0 Off 1 Preset 0 Invalid 1 Run 0 Stop 8 bit timer 4 control register 0 to 255 RLD47 RLD46 RLD45 RLD44 RLD43 RLD42 RLD41 RLD40 D7 D6 D5 D4 D3 D2 D1 D0 8 bit timer 4 reload data RLD47 MSB RLD40 LSB X X X X X X X X R W 0040175 B 8 bit timer 4 reload data register 0 to 255 PTD47 PTD46 PTD45 PTD44 PTD43 PTD42 PTD41 PTD40 D7 D6 D5 D4 D3 D2 D1 D0 8 bit timer 4 counter data...

Page 39: ...ting Init R W Remarks WRWD D7 D6 0 EWD write protection 0 R W 0 when being read 0040170 B 1 Write enabled 0 Write protect Watchdog timer write protect register EWD D7 2 D1 D0 Watchdog timer enable 0 R W 0 when being read 0 when being read 0040171 B 1 NMI enabled 0 NMI disabled Watchdog timer enable register ...

Page 40: ...wer control register PSCDT0 D7 1 D0 reserved Prescaler clock selection 0 0 R W 0040181 B Prescaler clock select register 1 OSC1 0 OSC3 PLL HLT2OP 8T1ON PF1ON D7 4 D3 D2 D1 D0 HALT clock option OSC3 stabilize waiting function reserved OSC1 external output control 0 1 0 0 R W R W R W 0 when being read Do not write 1 0040190 B 1 On 0 Off 1 Off 0 On 1 On 0 Off Clock option register Writing 10010110 0x...

Page 41: ...E2 B 1 Error 0 Normal 1 Transmitting 0 End 1 Error 0 Normal 1 Error 0 Normal 1 Empty 0 Buffer full 1 Buffer full 0 Empty Serial I F Ch 0 status register TXEN0 RXEN0 EPR0 PMD0 STPB0 SSCK0 SMD01 SMD00 D7 D6 D5 D4 D3 D2 D1 D0 Ch 0 transmit enable Ch 0 receive enable Ch 0 parity enable Ch 0 parity mode selection Ch 0 stop bit selection Ch 0 input clock selection Ch 0 transfer mode selection 1 1 0 0 1 ...

Page 42: ...hronous Clock sync Slave Clock sync Master 0 0 X X X X X X R W R W R W R W R W R W R W Valid only in asynchronous mode 00401E8 B Serial I F Ch 1 control register 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 SCLK1 0 Internal clock DIVMD1 IRTL1 IRRL1 IRMD11 IRMD10 D7 5 D4 D3 D2 D1 D0 Ch 1 async clock division ratio Ch 1 IrDA I F output logic inv...

Page 43: ...3 D2 D1 D0 Serial I F Ch 3 receive data RXD37 36 MSB RXD30 LSB X X X X X X X X R 00401F6 B Serial I F Ch 3 receive data register TEND3 FER3 PER3 OER3 TDBE3 RDBF3 D7 6 D5 D4 D3 D2 D1 D0 reserved Ch 3 transmit completion flag Ch 3 flaming error flag Ch 3 parity error flag Ch 3 overrun error flag Ch 3 transmit data buffer empty Ch 3 receive data buffer full 0 0 0 0 1 0 R R W R W R W R R 0 when being ...

Page 44: ... AD1 AD0 0 0 0 0 0 0 R W R W R 0 when being read 0040242 B 1 Continuous 0 Normal A D trigger register 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 CE 2 0 End channel AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 CS 2 0 Start channel AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 CE2 CE1 CE0 CS2 CS1 CS0 D7 6 D5 D4 D3 D2 D1 D0 A D converter end channel selection A D converter s...

Page 45: ...hen being read 0040263 B High speed DMA Ch 0 1 interrupt priority register 0 to 7 0 to 7 PHSD3L2 PHSD3L1 PHSD3L0 PHSD2L2 PHSD2L1 PHSD2L0 D7 D6 D5 D4 D3 D2 D1 D0 reserved High speed DMA Ch 3 interrupt level reserved High speed DMA Ch 2 interrupt level X X X X X X R W R W 0 when being read 0 when being read 0040264 B High speed DMA Ch 2 3 interrupt priority register 0 to 7 PDM2 PDM1 PDM0 D7 3 D2 D1 ...

Page 46: ...X R W R W 0 when being read 0 when being read 004026A B Serial I F Ch 1 A D interrupt priority register 0 to 7 PCTM2 PCTM1 PCTM0 D7 3 D2 D1 D0 reserved Clock timer interrupt level X X X R W Writing 1 not allowed 004026B B Clock timer interrupt priority register 0 to 7 0 to 7 PP5L2 PP5L1 PP5L0 PP4L2 PP4L1 PP4L0 D7 D6 D5 D4 D3 D2 D1 D0 reserved Port input 5 interrupt level reserved Port input 4 inte...

Page 47: ...R W R W R W R W 0 when being read 0 when being read 0040273 B 1 Enabled 0 Disabled 16 bit timer 2 3 interrupt enable register 1 Enabled 0 Disabled E16TC5 E16TU5 E16TC4 E16TU4 D7 D6 D5 4 D3 D2 D1 0 16 bit timer 5 comparison A 16 bit timer 5 comparison B reserved 16 bit timer 4 comparison A 16 bit timer 4 comparison B reserved 0 0 0 0 R W R W R W R W 0 when being read 0 when being read 0040274 B 1 E...

Page 48: ...ead 0040283 B 1 Factor is generated 0 No factor is generated 16 bit timer 2 3 interrupt factor flag register 1 Factor is generated 0 No factor is generated F16TC5 F16TU5 F16TC4 F16TU4 D7 D6 D5 4 D3 D2 D1 0 16 bit timer 5 comparison A 16 bit timer 5 comparison B reserved 16 bit timer 4 comparison A 16 bit timer 4 comparison B reserved X X X X R W R W R W R W 0 when being read 0 when being read 0040...

Page 49: ... W R W 0 when being read 0040293 B 1 IDMA request 0 Interrupt request 1 IDMA request 0 Interrupt request Serial I F Ch 1 A D port input 4 7 IDMA request register DE16TC0 DE16TU0 DEHDM1 DEHDM0 DEP3 DEP2 DEP1 DEP0 D7 D6 D5 D4 D3 D2 D1 D0 16 bit timer 0 comparison A 16 bit timer 0 comparison B High speed DMA Ch 1 High speed DMA Ch 0 Port input 3 Port input 2 Port input 1 Port input 0 0 0 0 0 0 0 0 0 ...

Page 50: ...eed DMA Ch 2 trigger set up 0 0 0 0 0 0 0 0 R W R W 0040299 B 0 1 2 3 4 5 6 7 8 9 A B C Software trigger K54 input falling edge K54 input rising edge Port 3 input Port 7 input 8 bit timer Ch 3 underflow 16 bit timer Ch 3 compare B 16 bit timer Ch 3 compare A 16 bit timer Ch 5 compare B 16 bit timer Ch 5 compare A SI F Ch 1 Rx buffer full SI F Ch 1 Tx buffer empty A D conversion completion 0 1 2 3 ...

Page 51: ...t data R R R R R 0 when being read 00402C1 B 1 High 0 Low K5 input port data register CFK67 CFK66 CFK65 CFK64 CFK63 CFK62 CFK61 CFK60 D7 D6 D5 D4 D3 D2 D1 D0 K67 function selection K66 function selection K65 function selection K64 function selection K63 function selection K62 function selection K61 function selection K60 function selection 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W 00402C3 B ...

Page 52: ...T6 SPPT5 SPPT4 SPPT3 SPPT2 SPPT1 SPPT0 D7 D6 D5 D4 D3 D2 D1 D0 FPT7 input polarity selection FPT6 input polarity selection FPT5 input polarity selection FPT4 input polarity selection FPT3 input polarity selection FPT2 input polarity selection FPT1 input polarity selection FPT0 input polarity selection 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W 00402C8 B Port input interrupt input polarity sel...

Page 53: ... W R W R W R W R W R W R W Extended functions 0x402DF 00402D0 B 1 SRDY1 0 P07 1 SCLK1 0 P06 1 SOUT1 0 P05 1 SIN1 0 P04 1 SRDY0 0 P03 1 SCLK0 0 P02 1 SOUT0 0 P01 1 SIN0 0 P00 P0 function select register P07D P06D P05D P04D P03D P02D P01D P00D D7 D6 D5 D4 D3 D2 D1 D0 P07 I O port data P06 I O port data P05 I O port data P04 I O port data P03 I O port data P02 I O port data P01 I O port data P00 I O ...

Page 54: ...rt data register IOC27 IOC26 IOC25 IOC24 IOC23 IOC22 IOC21 IOC20 D7 D6 D5 D4 D3 D2 D1 D0 P27 I O control P26 I O control P25 I O control P24 I O control P23 I O control P22 I O control P21 I O control P20 I O control 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W This register indicates the values of the I O control signals of the ports when it is read See detailed explanation 00402DA B 1 Output ...

Page 55: ...rved Areas 16 15 device size selection Areas 16 15 output disable delay time reserved Areas 16 15 wait control 1 8 bits 0 16 bits 1 8 bits 0 16 bits 0 1 1 1 1 1 0 1 1 1 1 1 R W R W R W R W R W R W 0 when being read 0 when being read 0 when being read 0 when being read 0048120 HW Areas 18 15 set up register 1 1 0 0 1 0 1 0 A18DF 1 0 Number of cycles 3 5 2 5 1 5 0 5 1 1 0 0 1 0 1 0 A16DF 1 0 Number ...

Page 56: ...10 9 output disable delay time reserved Areas 10 9 wait control 1 Used 0 Not used 1 Used 0 Not used 1 8 bits 0 16 bits 1 1 1 0 0 0 0 0 1 1 1 1 1 R W R W R W R W R W R W R W 0 when being read 0 when being read 0 when being read 0048126 HW 1 1 0 0 1 0 1 0 A10BW 1 0 Wait cycles 3 2 1 0 1 1 0 0 1 0 1 0 A10DF 1 0 Number of cycles 3 5 2 5 1 5 0 5 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 A10IR 2 0...

Page 57: ...D5 D4 D3 D2 D1 D0 TTBR register write protect 0 0 0 0 0 0 0 0 W Undefined in read 004812D B Writing 01011001 0x59 removes the TTBR 0x48134 write protection Writing other data sets the write protection TTBR write protect register RBCLK RBST8 REDO RCA1 RCA0 RPC2 RPC1 RPC0 RRA1 RRA0 SBUSST SEMAS SEPD SWAITE DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BCLK output control reserved Burst ROM burst m...

Page 58: ...ernal access Area 16 15 internal external access Area 14 13 internal external access Area 12 11 internal external access reserved Area 8 7 internal external access Area 6 internal external access Area 5 4 internal external access Area 18 17 endian control Area 16 15 endian control Area 14 13 endian control Area 12 11 endian control Area 10 9 endian control Area 8 7 endian control Area 6 endian con...

Page 59: ...ea 5 4 address strobe signal Area 18 17 read signal Area 16 15 read signal Area 14 13 read signal Area 12 11 read signal reserved Area 8 7 read signal Area 6 read signal Area 5 4 read signal 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 when being read 0 when being read 0048138 HW G A read signal control register 1 Enabled 0 Disabled 1 Enabled 0 Disabled...

Page 60: ...2 HW 16 bit timer 0 comparison register B 0 to 65535 TC015 TC014 TC013 TC012 TC011 TC010 TC09 TC08 TC07 TC06 TC05 TC04 TC03 TC02 TC01 TC00 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 bit timer 0 counter data TC015 MSB TC00 LSB X X X X X X X X X X X X X X X X R 0048184 HW 16 bit timer 0 counter data register SELFM0 SELCRB0 OUTINV0 CKSL0 PTM0 PRESET0 PRUN0 D7 D6 D5 D4 D3 D2 D1 D0 reserved 16 ...

Page 61: ...4818A HW 16 bit timer 1 comparison register B 0 to 65535 TC115 TC114 TC113 TC112 TC111 TC110 TC19 TC18 TC17 TC16 TC15 TC14 TC13 TC12 TC11 TC10 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 bit timer 1 counter data TC115 MSB TC10 LSB X X X X X X X X X X X X X X X X R 004818C HW 16 bit timer 1 counter data register SELFM1 SELCRB1 OUTINV1 CKSL1 PTM1 PRESET1 PRUN1 D7 D6 D5 D4 D3 D2 D1 D0 reserved...

Page 62: ...2 HW 16 bit timer 2 comparison register B 0 to 65535 TC215 TC214 TC213 TC212 TC211 TC210 TC29 TC28 TC27 TC26 TC25 TC24 TC23 TC22 TC21 TC20 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 bit timer 2 counter data TC215 MSB TC20 LSB X X X X X X X X X X X X X X X X R 0048194 HW 16 bit timer 2 counter data register SELFM2 SELCRB2 OUTINV2 CKSL2 PTM2 PRESET2 PRUN2 D7 D6 D5 D4 D3 D2 D1 D0 reserved 16 ...

Page 63: ...4819A HW 16 bit timer 3 comparison register B 0 to 65535 TC315 TC314 TC313 TC312 TC311 TC310 TC39 TC38 TC37 TC36 TC35 TC34 TC33 TC32 TC31 TC30 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 bit timer 3 counter data TC315 MSB TC30 LSB X X X X X X X X X X X X X X X X R 004819C HW 16 bit timer 3 counter data register SELFM3 SELCRB3 OUTINV3 CKSL3 PTM3 PRESET3 PRUN3 D7 D6 D5 D4 D3 D2 D1 D0 reserved...

Page 64: ...2 HW 16 bit timer 4 comparison register B 0 to 65535 TC415 TC414 TC413 TC412 TC411 TC410 TC49 TC48 TC47 TC46 TC45 TC44 TC43 TC42 TC41 TC40 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 bit timer 4 counter data TC415 MSB TC40 LSB X X X X X X X X X X X X X X X X R 00481A4 HW 16 bit timer 4 counter data register SELFM4 SELCRB4 OUTINV4 CKSL4 PTM4 PRESET4 PRUN4 D7 D6 D5 D4 D3 D2 D1 D0 reserved 16 ...

Page 65: ...481AA HW 16 bit timer 5 comparison register B 0 to 65535 TC515 TC514 TC513 TC512 TC511 TC510 TC59 TC58 TC57 TC56 TC55 TC54 TC53 TC52 TC51 TC50 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 bit timer 5 counter data TC515 MSB TC50 LSB X X X X X X X X X X X X X X X X R 00481AC HW 16 bit timer 5 counter data register SELFM5 SELCRB5 OUTINV5 CKSL5 PTM5 PRESET5 PRUN5 D7 D6 D5 D4 D3 D2 D1 D0 reserved...

Page 66: ...1 0 0 0 0 0 R W 0048200 HW IDMA base address low order register DBASEH11 DBASEH10 DBASEH9 DBASEH8 DBASEH7 DBASEH6 DBASEH5 DBASEH4 DBASEH3 DBASEH2 DBASEH1 DBASEH0 DF C DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 reserved IDMA base address high order 12 bits Initial value 0x0C003A0 0 0 0 0 1 1 0 0 0 0 0 0 R W Undefined in read 0048202 HW IDMA base address high order register 0 to 127 DSTART DCHN D7 D6 0 IDM...

Page 67: ...emory WR 0 Memory RD 0 0 X X X X X X X X R W R W R W Undefined in read 0048222 HW High speed DMA Ch 0 control register Note D Dual address mode S Single address mode S0ADRL15 S0ADRL14 S0ADRL13 S0ADRL12 S0ADRL11 S0ADRL10 S0ADRL9 S0ADRL8 S0ADRL7 S0ADRL6 S0ADRL5 S0ADRL4 S0ADRL3 S0ADRL2 S0ADRL1 S0ADRL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D Ch 0 source address 15 0 S Ch 0 memory address 15 ...

Page 68: ...RH2 D0ADRH1 D0ADRH0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch 0 transfer mode D Ch 0 destination address control S Invalid D Ch 0 destination address 27 16 S Invalid 0 0 0 0 X X X X X X X X X X X X R W R W R W 004822A HW High speed DMA Ch 0 high order destination address set up register Note D Dual address mode S Single address mode 1 1 0 0 1 0 1 0 D0MOD 1 0 Mode Invalid Block Successive ...

Page 69: ...emory WR 0 Memory RD 0 0 X X X X X X X X R W R W R W Undefined in read 0048232 HW High speed DMA Ch 1 control register Note D Dual address mode S Single address mode S1ADRL15 S1ADRL14 S1ADRL13 S1ADRL12 S1ADRL11 S1ADRL10 S1ADRL9 S1ADRL8 S1ADRL7 S1ADRL6 S1ADRL5 S1ADRL4 S1ADRL3 S1ADRL2 S1ADRL1 S1ADRL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D Ch 1 source address 15 0 S Ch 1 memory address 15 ...

Page 70: ...RH2 D1ADRH1 D1ADRH0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch 1 transfer mode D Ch 1 destination address control S Invalid D Ch 1 destination address 27 16 S Invalid 0 0 0 0 X X X X X X X X X X X X R W R W R W 004823A HW High speed DMA Ch 1 high order destination address set up register Note D Dual address mode S Single address mode 1 1 0 0 1 0 1 0 D1MOD 1 0 Mode Invalid Block Successive ...

Page 71: ...emory WR 0 Memory RD 0 0 X X X X X X X X R W R W R W Undefined in read 0048242 HW High speed DMA Ch 2 control register Note D Dual address mode S Single address mode S2ADRL15 S2ADRL14 S2ADRL13 S2ADRL12 S2ADRL11 S2ADRL10 S2ADRL9 S2ADRL8 S2ADRL7 S2ADRL6 S2ADRL5 S2ADRL4 S2ADRL3 S2ADRL2 S2ADRL1 S2ADRL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D Ch 2 source address 15 0 S Ch 2 memory address 15 ...

Page 72: ...RH2 D2ADRH1 D2ADRH0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch 2 transfer mode D Ch 2 destination address control S Invalid D Ch 2 destination address 27 16 S Invalid 0 0 0 0 X X X X X X X X X X X X R W R W R W 004824A HW High speed DMA Ch 2 high order destination address set up register Note D Dual address mode S Single address mode 1 1 0 0 1 0 1 0 D2MOD 1 0 Mode Invalid Block Successive ...

Page 73: ...emory WR 0 Memory RD 0 0 X X X X X X X X R W R W R W Undefined in read 0048252 HW High speed DMA Ch 3 control register Note D Dual address mode S Single address mode S3ADRL15 S3ADRL14 S3ADRL13 S3ADRL12 S3ADRL11 S3ADRL10 S3ADRL9 S3ADRL8 S3ADRL7 S3ADRL6 S3ADRL5 S3ADRL4 S3ADRL3 S3ADRL2 S3ADRL1 S3ADRL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D Ch 3 source address 15 0 S Ch 3 memory address 15 ...

Page 74: ...RH2 D3ADRH1 D3ADRH0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch 3 transfer mode D Ch 3 destination address control S Invalid D Ch 3 destination address 27 16 S Invalid 0 0 0 0 X X X X X X X X X X X X R W R W R W 004825A HW High speed DMA Ch 3 high order destination address set up register Note D Dual address mode S Single address mode 1 1 0 0 1 0 1 0 D3MOD 1 0 Mode Invalid Block Successive ...

Page 75: ...served SDRAM page size column range reserved SDRAM row addressing range Number of SDRAM banks reserved 0 0 0 0 0 R W R W R W 0 when being read 0 when being read 0 when being read 039FFC2 B 1 4 banks 0 2 banks SDRAM address configuration register 1 1 0 0 1 0 1 0 SDRRA 1 0 Addressing range reserved 8K SDA 12 0 4K SDA 11 0 2K SDA 10 0 1 1 0 0 1 0 1 0 SDRCA 1 0 Page size reserved 1K SDA 9 0 512 SDA 8 ...

Page 76: ... D0 reserved SDRAM auto refresh count 11 0 1 1 1 1 1 1 1 1 1 1 1 1 R W 0 when being read 039FFC6 HW SDRAM auto refresh count register 0 to 4096 SDRSRFC3 SDRSRFC2 SDRSRFC1 SDRSRFC0 D7 4 D3 D2 D1 D0 reserved SDRAM self refresh count 3 0 1 1 1 1 R W 0 when being read This register must not be set less than 0x02 039FFC8 B SDRAM self refresh count register 2 to 15 SDRSZ SDRBI D7 D6 D5 D4 0 reserved SDR...

Page 77: ...CDC mode register 1 1 1 0 0 1 0 1 0 BPP 1 0 Mode 8 bpp 4 bpp 2 bpp 1 bpp LCDCEN LPWREN LPSAVE1 LPSAVE0 D7 6 D5 D4 D3 2 D1 D0 reserved LCD controller enable LCDPWR enable reserved Power save mode 0 0 0 0 R W R W R W 0 when being read 0 when being read 039FFE3 B 1 Enabled 0 Disabled 1 Enabled 0 Disabled LCDC mode register 2 1 1 0 0 1 0 1 0 LPSAVE 1 0 Mode Normal operation Doze reserved Power save LD...

Page 78: ...creen 1 start address high order 8 bits 0 0 0 0 0 0 0 0 R W 039FFED B Screen 1 start address register 1 S2ADDR7 S2ADDR6 S2ADDR5 S2ADDR4 S2ADDR3 S2ADDR2 S2ADDR1 S2ADDR0 D7 D6 D5 D4 D3 D2 D1 D0 Screen 2 start address low order 8 bits 0 0 0 0 0 0 0 0 R W 039FFEE B Screen 2 start address register 0 S2ADDR15 S2ADDR14 S2ADDR13 S2ADDR12 S2ADDR11 S2ADDR10 S2ADDR9 S2ADDR8 D7 D6 D5 D4 D3 D2 D1 D0 Screen 2 s...

Page 79: ...onfiguration register 1 Output 0 Input 1 Output 0 Input 1 Output 0 Input GPO6D GPO5D GPO4D GPO3D GPIO2D GPIO1D GPIO0D D7 D6 D5 D4 D3 D2 D1 D0 reserved GPO6 data GPO5 data GPO4 data GPO3 data GPIO2 data GPIO1 data GPIO0 data 0 0 0 0 0 0 0 R W R W R W R W R W R W R W 0 when being read 039FFF9 B GPIO status control register 1 High 0 Low 1 High 0 Low 1 High 0 Low 1 High 0 Low 1 High 0 Low 1 High 0 Low...

Page 80: ...CST LCDCEC D7 D6 D5 D4 D3 D2 D1 D0 VRAM area select VRAM wait control number of wait cycles for SRAM External DMA enable External bus request enable A0 BSL select Big little endian select 0 0 0 0 0 0 0 0 R W R W R W R W R W R W 039FFFD B 1 Area 8 0 Area 7 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 BSL 0 A0 1 Big endian 0 Little endian LCDC system control register 0 7 ...

Page 81: ...t clocks HLT2OP D3 Clock option register 0x40190 that is used to select a HALT mode is set to 0 basic HALT mode at initial reset Notes In systems in which DRAM or SDRAM is connected directly to the device the refresh function is turned off during HALT2 and SLEEP modes However the SDRAM self refresh function can be used by activating it before the CPU enters HALT2 or SLEEP mode The standby mode is ...

Page 82: ...trol register 0x40148 ON OFF OFF 16 bit timer 1 Run Stop PRUN1 D0 16 bit timer 1 control register 0x4818E RUN STOP STOP 16 bit timer 2 clock control P16TON2 D3 16 bit timer 2 clock control register 0x40149 ON OFF OFF 16 bit timer 2 Run Stop PRUN2 D0 16 bit timer 2 control register 0x48196 RUN STOP STOP 16 bit timer 3 clock control P16TON3 D3 16 bit timer 3 clock control register 0x4014A ON OFF OFF...

Page 83: ...0 Default Prescaler operating clock switch over PSCDT0 D0 Prescaler clock select register 0x40181 OSC1 OSC3 PLL OSC3 PLL Power down control of the LCD controller The LCD controller provides the power save mode on its own Since the power save mode can be controlled by software set the mode when turning the LCD display off Function Control bit 11 00 Default Power save mode LPSAVE 1 0 D 1 0 LCDC mode...

Page 84: ...kHz CI Max 34 kΩ 10 pF 10 pF 10 MΩ 33 MHz Max 33 MHz Max 10 pF 10 pF 1 MΩ 4 7 kΩ 100 pF 5 pF Note The above table is simply an example and is not guaranteed to work 1 When the PLL is not used leave the PLLC pin open VDD VDDE AVDDE DSIO ICEMD EA10MD0 EA10MD1 X2SPD PLLC PLLS0 PLLS1 OSC3 OSC4 OSC1 OSC2 RESET VSS CD2 3 3V X tal2 or CR Rf2 A 23 0 D 15 0 RD EMEMRD DRD GARD GAAS WRL WR WE WRH BSH DWE SDW...

Page 85: ...S Sample VSS pattern OSC3 and OSC4 VSS PLLC VSS PLLC 3 When supplying an external clock to the OSC3 OSC1 pin the clock source should be connected to the OSC3 OSC1 pin in the shortest line Furthermore do not connect anything else to the OSC4 OSC2 pin In order to prevent unstable operation of the oscillation circuit due to current leak between OSC3 OSC1 and VDD please keep enough distance between OS...

Page 86: ...se caused by mutual inductance do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit and analog input unit When a signal line is parallel with a high speed line in long distance or intersects a high speed line noise may generated by mutual interference between the signals and it may cause a malfunction Do not arrange a high speed sign...

Page 87: ...ue Unit Supply voltage VDD 0 3 to 4 0 V C33 I O power voltage VDDE 0 3 to 7 0 V Input voltage VI 0 3 to VDDE 0 5 V High level output current IOH 1 pin 10 mA Total of all pins 40 mA Low level output current IOL 1 pin 10 mA Total of all pins 40 mA Analog power voltage AVDDE 0 3 to 7 0 V Analog input voltage AVIN 0 3 to AVDDE 0 3 V Storage temperature TSTG 65 to 150 C ...

Page 88: ... Condition Min Typ Max Unit Supply voltage VDD 2 70 3 60 V Input voltage VI VSS VDD V CPU operating clock frequency fCPU 50 MHz External bus operating clock frequency fBUS 35 MHz Low speed oscillation frequency fOSC1 32 768 kHz Operating temperature Ta 40 25 85 C Input rise time normal input tri 50 ns Input fall time normal input tfi 50 ns Input rise time schmitt input tri 5 ms Input fall time sch...

Page 89: ...in capacitance CI f 1MHz VDDE 0V 10 pF Output pin capacitance CO f 1MHz VDDE 0V 10 pF I O pin capacitance CIO f 1MHz VDDE 0V 10 pF 2 3 3 V single power source Unless otherwise specified VDDE VDD 2 7V to 3 6V Ta 40 C to 85 C Item Symbol Condition Min Typ Max Unit Static current consumption IDDS Static state Tj 85 C 90 µA Input leakage current ILI 1 1 µA Off state leakage current IOZ 1 1 µA High lev...

Page 90: ...voltage VOL IOL 0 6mA Type1 IOL 2mA Type2 IOL 4mA Type3 VDD Min 0 2 V High level input voltage VIH CMOS level VDD Max 1 6 V Low level input voltage VIL CMOS level VDD Min 0 3 V Positive trigger input voltage VT CMOS Schmitt 0 4 1 6 V Negative trigger input voltage VT CMOS Schmitt 0 3 1 4 V Hysteresis voltage VH CMOS Schmitt 0 V Pull up resistor RPU VI 0V Other than DSIO 120 480 1200 kΩ DSIO 60 240...

Page 91: ...Item Symbol Condition Min Typ Max Unit A D converter operating current AIDD1 VDD 3 6V VDDE AVDDE 5 0V 0 5V 800 1400 µA 6 VDD VDDE AVDDE 2 7V to 3 6V 500 800 4 LCD controller operating current Unless otherwise specified VDDE 2 7V to 5 5V VDD 2 7V to 3 6V VSS 0V Ta 40 C to 85 C Item Symbol Condition Min Typ Max Unit LCD controller operating current LIDD1 Display resolution 320 240 1bpp LCDC CLK 25MH...

Page 92: ...ess otherwise specified VDDE AVDDE VDD 2 7V to 3 6V VSS 0V Ta 40 C to 85 C ST 1 0 11 Item Symbol Condition Min Typ Max Unit Resolution 10 bit Conversion time 10 625 µs 1 Zero scale error EZS 0 2 4 LSB Full scale error EFS 2 2 LSB Integral linearity error EL 3 3 LSB Differential linearity error ED 3 3 LSB Permissible signal source impedance 5 kΩ Analog input capacitance 45 pF note 1 Indicates the m...

Page 93: ...error ED 1 LSB V N h V N 1 h 1LSB Digital output hex Analog input Ideal conversion characteristic Actual conversion characteristic V 000 h 0 5LSB V 000 h 004 003 002 001 000 VSS Zero scale error Zero scale error EZS LSB V 000 h 0 5LSB V 000 h 0 5LSB 1LSB Digital output hex Analog input Ideal conversion characteristic Actual conversion characteristic V 3FF h 1022 5LSB V 3FF h 3FF 3FE 3FD 3FC 3FB AV...

Page 94: ...if 1 wait cycle is set The write cycle is actually extended when 2 or more wait cycles are set When inserting wait cycles by controlling the WAIT pin from outside of the IC pay attention to the timing of the WAIT signal sampling Read cycles are terminated at the cycle in which the WAIT signal is negated Write cycles are terminated at the following cycle after the WAIT signal is negated C1 C2 C3 Cn...

Page 95: ...tIR 5 ns BCLK high level output delay time tCD1 35 ns BCLK low level output delay time tCD2 35 ns Minimum reset pulse width tRST 6 tCYC ns 3 2 0 V single power source Unless otherwise specified VDDE VDD 2 0V 0 2V VSS 0V Ta 40 C to 85 C Item Symbol Min Max Unit High speed clock cycle time tC3 50 ns OSC3 clock input duty tC3ED 45 55 OSC3 clock input rise time tIF 5 ns OSC3 clock input fall time tIR ...

Page 96: ...me 1 tCE1 10 ns CEx delay time 2 tCE2 10 ns Wait setup time tWTS 15 ns Wait hold time tWTH 0 ns Read signal delay time 1 tRDD1 10 ns 2 Read data setup time tRDS 15 ns Read data hold time tRDH 0 ns Write signal delay time 1 tWRD1 10 ns 3 Write data delay time 1 tWDD1 10 ns Write data delay time 2 tWDD2 0 10 ns Write data hold time tWDH 0 ns 3 2 0 V single power source Unless otherwise specified VDD...

Page 97: ... ns 3 2 0 V single power source Unless otherwise specified VDDE VDD 2 0V 0 2V VSS 0V Ta 40 C to 85 C Item Symbol Min Max Unit Read signal delay time 2 tRDD2 10 ns Read signal pulse width tRDW tCYC 0 5 WC 10 ns Read address access time 1 tACC1 tCYC 1 WC 60 ns Chip enable access time 1 tCEAC1 tCYC 1 WC 60 ns Read signal access time 1 tRDAC1 tCYC 0 5 WC 60 ns SRAM write cycle 1 3 3 V 5 0 V dual power...

Page 98: ...bol Min Max Unit RAS signal delay time 1 tRASD1 10 ns RAS signal delay time 2 tRASD2 10 ns RAS signal pulse width tRASW tCYC 2 WC 10 ns CAS signal delay time 1 tCASD1 10 ns CAS signal delay time 2 tCASD2 10 ns CAS signal pulse width tCASW tCYC 0 5 WC 10 ns Read signal delay time 3 tRDD3 10 ns Read signal pulse width 2 tRDW2 tCYC 2 WC 10 ns Write signal delay time 3 tWRD3 10 ns Write signal pulse w...

Page 99: ...C 60 ns RAS access time tRACF tCYC 1 5 WC 60 ns CAS access time tCACF tCYC 0 5 WC 60 ns EDO DRAM random access cycle and EDO DRAM page cycle 1 3 3 V 5 0 V dual power source Unless otherwise specified VDDE 5 0V 0 5V VDD 2 7V to 3 6V VSS 0V Ta 40 C to 85 C Item Symbol Min Max Unit Column address access time tACCE tCYC 1 5 WC 25 ns RAS access time tRACE tCYC 2 WC 25 ns CAS access time tCACE tCYC 1 WC...

Page 100: ...me t RDH 0 ns Write data delay time t WDD 11 ns Write data hold time t WDH T 11 ns 2 X2SPD 0 CPU SDRAM clock 2 1 3 3 V single power source Unless otherwise specified VDDE VDD 3 0V to 3 6V VSS 0V Ta 40 C to 85 C Item Symbol Min Max Unit OSC3 input clock frequency fOSC3 17 5 MHz BCLK clock output cycle time t C3x2 57 ns Address delay time t ADx2 T 11 ns SDA10 delay time t A10Dx2 T 11 ns SDCEx delay ...

Page 101: ...time 2 tRDAC2 tCYC 0 5 WC 60 ns Burst address access time tACCB tCYC 1 WC 60 ns External bus master and NMI 1 3 3 V 5 0 V dual power source Unless otherwise specified VDDE 5 0V 0 5V VDD 2 7V to 3 6V VSS 0V Ta 40 C to 85 C Item Symbol Min Max Unit BUSREQ signal setup time tBRQS 15 ns BUSREQ signal hold time tBRQH 0 ns BUSACK signal output delay time tBAKD 10 ns High impedance output delay time tZ2E...

Page 102: ...2 3 3 V single power source Unless otherwise specified VDDE VDD 2 7V to 3 6V VSS 0V Ta 40 C to 85 C Item Symbol Min Max Unit Input data setup time tINPS 20 ns Input data hold time tINPH 10 ns Output data delay time tOUTD 20 ns K port interrupt SLEEP HALT2 mode tKINW 30 ns input pulse width Others 2 tCYC ns 3 2 0 V single power source Unless otherwise specified VDDE VDD 2 0V 0 2V VSS 0V Ta 40 C to ...

Page 103: ...C Characteristic Timing Charts Clock OSC3 High speed clock tC3 BCLK Clock output tC3 tC3H tC3ED tC3H tC3 tCBD tCBH tC3 BCLK Clock output tC3 tCBH tCD1 tCD2 tIF tIR 1 When an external clock is input in x1 speed mode 2 When the high speed oscillation circuit is used for the operating clock ...

Page 104: ... measured with respect to the first signal change negation from among the RD CEx and A 23 0 signals SRAM read cycle when a wait cycle is inserted BCLK A 23 0 CEx RD D 15 0 WAIT C1 Cw wait cycle Cn last cycle tAD tCE1 tCE2 tRDD2 tRDD1 C1 only tRDAC1 tRDS tWTS tWTH tWTS tWTH tRDH tCEAC1 tACC1 tRDW tAD 1 tWTS tWTH 1 tRDH is measured with respect to the first signal change negation from among the RD C...

Page 105: ...0 CEx WR D 15 0 WAIT C1 C2 tAD tCE1 tCE2 tWRD2 tWRD1 tWTS tWTH tWDD1 tWDH tWRW tAD SRAM write cycle when wait cycles are inserted BCLK A 23 0 CEx WR D 15 0 WAIT C1 Cw wait cycle Cw wait cycle Cn last cycle tAD tCE1 tCE2 tWRD2 tWRD1 tWTS tWTH tWTS tWTS tWTH tWTH tWDD1 tWDH tWRW tAD Wait cycle follows Last cycle follows ...

Page 106: ...W tCACF 1 1 tRDH is measured with respect to the first signal change negation of either the RD or the A 23 0 signals DRAM fast page access cycle BCLK A 23 0 RAS HCAS LCAS RD D 15 0 WE D 15 0 RAS1 Data transfer 1 Data transfer 2 Next data transfer CAS1 CAS2 PRE1 precharge RAS1 tAD tAD tAD tRDS tACCF tRACF tRDH tRASD2 tRASD1 tRDD3 tRDD1 tWRD3 tWRD1 tWDD1 tWDD2 tWDD2 tCACF tACCF tRASW tRDW2 tCASD2 tC...

Page 107: ...ASW tCACE 1 1 tRDH is measured with respect to the first signal change negation of either the RD or the RASx signals EDO DRAM page access cycle BCLK A 23 0 RAS HCAS LCAS RD D 15 0 WE D 15 0 RAS1 Data transfer 1 Data transfer 2 Next data transfer CAS1 CAS2 PRE1 precharge RAS1 tAD tAD tAD tRDS tACCE tRACE tRASD2 tRASD1 tRDD3 tRDD1 tWRD3 tWRD1 tWDD1 tWDD2 tWDD2 tCACE tACCE tRASW tRDW2 tCASD2 tCASD1 t...

Page 108: ...CASD1 DRAM self refresh cycle BCLK RAS HCAS LCAS Self refresh mode setup Self refresh mode tCASD2 Self refresh mode canceration tRASD2 tRASD1 tCASD1 6 cycle precharge Fixed SDRAM clock OSC3 High speed clock BCLK SDRAM clock output tC3 tCBD tCBH tC3 tCBD tCBH tC3 BCLK SDRAM clock output tC3 tCBH tCBH 1 X2SPD high CPU clock SDRAM clock 1 1 2 X2SPD low CPU clock SDRAM clock 2 1 ...

Page 109: ... write nop H valid valid valid tA10D tCED1 tCED2 tWED1 tWED1 tWED2 tDQMD1 tWDH tWDD tDQMD2 valid valid valid valid valid valid nop Precharge tRASD1 tRASD2 tCASD1 tRDH tRDS Read CAS latency 2 burst length 2 Write single write SDRAM mode register set cycle tCASD2 BCLK SDCKE A 23 0 SDA10 SDCEx SDRAS SDCAS SDWE D 15 0 HDQM LDQM Mode register set tAD nop nop H valid tAD tCED1 tCED2 tWED1 tWED2 valid no...

Page 110: ...nop H tCED1 tCED2 tWED1 tWED2 nop nop tRASD1 tRASD2 tCASD1 A precharge cycle is necessary before entering the auto refresh mode SDRAM self refresh cycle BCLK SDCKE A 23 0 SDA10 SDCEx SDRAS SDCAS SDWE D 15 0 HDQM LDQM tCED1 tCED2 tWED1 Exit self refresh mode Enter self refresh mode tRASD1 tCASD1 tCKE1 tCKE2 A precharge cycle is necessary before entering the self refresh mode ...

Page 111: ...RDH tACCB 1 1 tRDH is measured with respect to the first signal change negation from among the RD CEx and A 23 0 signals BUSREQ BUSACK and NMI timing BCLK BUSREQ BUSACK eBUS_OUT signals 1 eBUS_OUT signals 1 NMI tBRQS Valid input tNMIW tBRQH tBAKD tZ2E tB2Z 1 eBUS_OUT indicates the following pins A 23 0 RD WRL WRH HCAS LCAS CE 17 4 D 15 0 Input output and I O port timing BCLK Kxx Pxx input data rea...

Page 112: ...gnals LCDPWR signal Active Inactive Inactive Active Inactive t1 t1 t4 t4 t3 t5 t6 t6 t2 11 11 00 00 00 Symbol Parameter Min Typ Max Unit t1 Power Save inactive to FPLINE FPFRAME FPSHIFT FPDAT DRDY active 1 Frame t2 FPLINE FPFRAME FPSHIFT FPDAT DRDY active to LCDPWR active 0 Frame t3 Power Save active to LCDPWR inactive 1 Frame t4 Power Save active to FPLINE FPFRAME FPSHIFT FPDAT DRDY inactive 1 Fr...

Page 113: ...ine 2 Line 4 Line 239 Line 240 HDP HNDP Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320 240 panel For this timing diagram FPSMASK D2 0x39FFE1 is set to 1 VDP Vertical Display Period LDVSIZE 9 0 1 lines LDVSIZE 9 0 0x39FFE5 D 1 0 0x39FFE6 VNDP Vertical Non Display Period VNDP 5 0 lines VNDP 5 0 D 5 0 0x39FFEA HDP Horizontal Display Period LDHSIZE 5 0 1 16 Ts LDHSIZE 5 0 D...

Page 114: ... period note 3 t4 Line Pulse width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 2 Ts t9 Shift Pulse period 4 Ts t10 Shift Pulse width low 2 Ts t11 Shift Pulse width high 2 Ts t12 FPDAT 7 4 setup to Shift Pulse fa...

Page 115: ...15 1 639 1 8 1 16 1 640 Line 2 Line 3 Line 1 Line 2 Line 4 Line 479 Line 480 HDP HNDP Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640 480 panel For this timing diagram FPSMASK D2 0x39FFE1 is set to 1 VDP Vertical Display Period LDVSIZE 9 0 1 lines LDVSIZE 9 0 0x39FFE5 D 1 0 0x39FFE6 VNDP Vertical Non Display Period VNDP 5 0 lines VNDP 5 0 D 5 0 0x39FFEA HDP Horizontal Di...

Page 116: ... period note 3 t4 Line Pulse width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 4 Ts t9 Shift Pulse period 8 Ts t10 Shift Pulse width low 4 Ts t11 Shift Pulse width high 4 Ts t12 FPDAT 7 0 setup to Shift Pulse fa...

Page 117: ...R4 1 G4 1 B4 1 B320 Line 2 Line 3 Line 1 Line 2 Line 4 Line 239 Line 240 HDP HNDP Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320 240 panel VDP Vertical Display Period LDVSIZE 9 0 1 lines LDVSIZE 9 0 0x39FFE5 D 1 0 0x39FFE6 VNDP Vertical Non Display Period VNDP 5 0 lines VNDP 5 0 D 5 0 0x39FFEA HDP Horizontal Display Period LDHSIZE 5 0 1 16 Ts LDHSIZE 5 0 D 5 0 0x39FFE4 ...

Page 118: ...t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 0 5 Ts t9 Shift Pulse period 1 Ts t10 Shift Pulse width low 0 5 Ts t11 Shift Pulse width high 0 5 Ts t12 FPDAT 7 4 setup to Shift Pulse falling edge 1 5 Ts t13 FPDAT 7 4 ho...

Page 119: ...G10 1 R11 1 B6 1 G7 1 R8 1 B8 1 G9 1 R10 1 B10 1 G11 1 B11 1 G12 1 R13 1 B13 1 G14 1 R15 1 B15 1 G16 1 R12 1 B12 1 G13 1 R14 1 B14 1 G15 1 R16 1 B16 Line 2 Line 3 Line 1 Line 2 Line 4 Line 479 Line 480 HDP HNDP Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640 480 panel VDP Vertical Display Period LDVSIZE 9 0 1 lines LDVSIZE 9 0 0x39FFE5 D 1 0 0x39FFE6 VNDP Vertical Non Di...

Page 120: ...lse rising edge note 5 t7a Shift Pulse 2 falling edge to Line Pulse falling edge note 6 t7b Shift Pulse falling edge to Line Pulse falling edge note 7 t8 Line Pulse falling edge to Shift Pulse rising Shift Pulse 2 falling edge t14 2 Ts t9 Shift Pulse 2 Shift Pulse period 4 Ts t10 Shift Pulse 2 Shift Pulse width low 2 Ts t11 Shift Pulse 2 Shift Pulse width high 2 Ts t12 FPDAT 7 0 setup to Shift Pul...

Page 121: ...5 1 R640 1 R3 1 B5 1 G640 1 G3 1 R6 1 G6 1 B6 1 R7 1 G7 1 B7 1 R8 1 G8 1 B8 1 B640 Line 2 Line 3 Line 1 Line 2 Line 4 Line 479 Line 480 HDP HNDP Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640 480 panel VDP Vertical Display Period LDVSIZE 9 0 1 lines LDVSIZE 9 0 0x39FFE5 D 1 0 0x39FFE6 VNDP Vertical Non Display Period VNDP 5 0 lines VNDP 5 0 D 5 0 0x39FFEA HDP Horizontal...

Page 122: ...width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 2 Ts t9 Shift Pulse period 2 Ts t10 Shift Pulse width low 1 Ts t11 Shift Pulse width high 1 Ts t12 FPDAT 7 0 setup to Shift Pulse falling edge 1 Ts t13 FPDAT 7 0...

Page 123: ...ng board capacitance 5 25 pF Frequency IC deviation f IC 10 10 ppm Frequency power voltage deviation f V 10 10 ppm V Frequency adjustment range f CG CG1 CD1 5 to 25pF 50 ppm 1 Q11C02RX Crystal resonator made by Seiko Epson 2 CG1 CD1 15pF includes board capacitance Unless otherwise specified VDD 2 0V VSS 0V crystal Q11C02RX 1 32 768kHz Rf1 20MΩ CG1 CD1 15pF 2 Ta 25 C Item Symbol Condition Min Typ M...

Page 124: ... 6 Murata Mfg corporation 1 This oscillator has a tendency to rise to the frequency of 0 3 8 8 PLL Characteristics Setting the PLLS0 and PLLS1 pins recommended operating condition VDD 2 7V to 3 6V PLLS1 PLLS0 Mode Fin OSC3 clock Fout 1 1 x2 10 to 25MHz 20 to 50MHz 0 1 x4 10 to 12 5MHz 40 to 50MHz 0 0 PLL not used VDD 2 0V 0 2V PLLS1 PLLS0 Mode Fin OSC3 clock Fout 1 1 x2 10MHz 20MHz 0 0 PLL not use...

Page 125: ...calculated from environment temperature Ta thermal package resistance θ and power consumption PD Chip temperature Tj Ta PD θ C As a guide normally keep the chip temperature Tj lower than 85 C The thermal resistance of the QFP20 144pin package is as follows Thermal resistance C W 110 to 120 C 90 to 100 C for Cu lead frame This thermal resistance is a value under the condition that the measured devi...

Page 126: ...T A 110 EPSON S1C33L03 PRODUCT PART 10 Pad Layout 10 1 Pad Layout Diagram X Y 0 0 1 5 10 15 20 25 30 35 40 120 115 110 105 100 95 90 85 45 50 55 60 65 70 75 80 160 155 150 145 140 135 130 125 5 97 mm 5 38 mm Die No ...

Page 127: ...20 0 2549 5 74 OSC2 2843 5 1320 0 25 VDDE 330 0 2549 5 75 OSC1 2843 5 1430 0 26 DRDY MOD FPSHIFT2 440 0 2549 5 76 RESET 2843 5 1540 0 27 FPFRAME 550 0 2549 5 77 P35 BUSACK GPIO1 2843 5 1650 0 28 FPLINE 660 0 2549 5 78 N C 2843 5 1760 0 29 FPSHIFT 770 0 2549 5 79 P34 BUSREQ CE6 GPIO0 2843 5 1870 0 30 N C 880 0 2549 5 80 P33 DMAACK1 SIN3 SDA10 2843 5 1980 0 31 LCDPWR 990 0 2549 5 81 P32 DMAACK0 SRDY...

Page 128: ...42 VDD 2843 5 0 0 113 A14 SDBA0 1210 0 2549 5 143 OSC4 2843 5 110 0 114 A15 SDBA1 1320 0 2549 5 144 OSC3 2843 5 220 0 115 A16 1430 0 2549 5 145 NMI 2843 5 330 0 116 A17 1540 0 2549 5 146 CE9 CE17 CE17 18 2843 5 440 0 117 VSS 1650 0 2549 5 147 VDDE 2843 5 550 0 118 N C 1760 0 2549 5 148 CE5 CE15 CE15 16 2843 5 660 0 119 A18 1870 0 2549 5 149 N C 2843 5 770 0 120 N C 1980 0 2549 5 150 CE3 2843 5 880...

Page 129: ...number of cycles should be determined by referring the manual or specification of the device to be used It is necessary to set the timing values allowing ample margin according to the load capacitance of the bus and signal lines number of devices to be connected operating temperature range I O levels and other conditions The number of cycles described in this section is an example and the conditio...

Page 130: ... 0 5 25 Column address setup time tASC 0 0 5 15 0 5 20 0 5 25 RAS CAS delay time tRCD 20 2 0 60 1 0 40 1 0 50 RAS column address delay time tRAD 15 1 5 45 0 5 20 0 5 25 Read cycle parameters RAS access time tRAC 70 4 5 135 2 5 100 2 5 125 CAS access time tCAC 20 2 5 75 1 5 60 1 5 75 Address access time tAA 35 3 0 90 2 0 80 2 0 100 OE access time tOAC 20 4 5 135 2 5 100 2 5 125 Output buffer turn o...

Page 131: ...RP 2 BCLK A 11 0 RAS CAS RD D 15 0 RD WE D 15 0 WR ROW 1 RD data ROW 2 tDH tDS WR data COL 1 DRAM 70ns CPU 33MHz page mode read write cycle 2 RAS cycle CAS cycle RAS precharge 3 CAS cycle 3 tPC tACP tCP tRAS 2 BCLK A 11 0 RAS CAS RD D 15 0 RD WE D 15 0 WR ROW 1 RD data RD data WR data WR data COL 1 COL 2 DRAM 70ns CPU 33MHz CAS before RAS refresh cycle 1 1 RPC delay Fixed Refresh RAS pulse width 3...

Page 132: ...D 15 0 RD WE D 15 0 WR ROW 1 RD data ROW 2 WR data COL 1 DRAM 70ns CPU 25 20MHz page mode read write cycle 1 RAS cycle CAS cycle RAS precharge 2 CAS cycle 2 2 tRAS BCLK A 11 0 RAS CAS RD D 15 0 RD WE D 15 0 WR ROW 1 RD data RD data WR data WR data COL 1 COL 2 DRAM 70ns CPU 25 20MHz CAS before RAS refresh cycle 1 1 RPC delay Fixed Refresh RAS pulse width 2 RAS precharge 2 tRPC tCSR tCHR tRAS BCLK R...

Page 133: ...5 20 0 5 25 Column address setup time tASC 0 0 5 15 0 5 20 0 5 25 RAS CAS delay time tRCD 20 2 0 60 1 0 40 1 0 50 RAS column address delay time tRAD 15 1 5 45 0 5 20 0 5 25 Read cycle parameters RAS access time tRAC 60 3 5 105 2 5 100 2 5 125 CAS access time tCAC 15 1 5 45 1 5 60 1 5 75 Address access time tAA 30 2 0 60 2 0 80 2 0 100 OE access time tOAC 15 3 5 105 2 5 100 2 5 125 Output buffer tu...

Page 134: ... BCLK A 11 0 RAS CAS RD D 15 0 RD WE D 15 0 WR ROW 1 RD data ROW 2 tDH tDS WR data COL 1 DRAM 60ns CPU 33MHz page mode read write cycle 2 RAS cycle CAS cycle RAS precharge 2 CAS cycle 2 tPC tACP tCP tRAS 2 BCLK A 11 0 RAS CAS RD D 15 0 RD WE D 15 0 WR ROW 1 RD data RD data WR data WR data COL 1 COL 2 DRAM 60ns CPU 33MHz CAS before RAS refresh cycle 1 1 RPC delay Fixed Refresh RAS pulse width 3 RAS...

Page 135: ...AS RD D 15 0 RD WE D 15 0 WR ROW 1 RD data ROW 2 WR data COL 1 DRAM 60ns CPU 25MHz page mode read write cycle 1 RAS cycle CAS cycle RAS precharge 2 CAS cycle 2 2 tRAS BCLK A 11 0 RAS CAS RD D 15 0 RD WE D 15 0 WR ROW 1 RD data RD data WR data WR data COL 1 COL 2 DRAM 60ns CPU 25MHz CAS before RAS refresh cycle 1 1 RPC delay Fixed Refresh RAS pulse width 2 RAS precharge 2 tRPC tCSR tCHR tRAS BCLK R...

Page 136: ... D 15 0 RD WE D 15 0 WR ROW 1 RD data ROW 2 WR data COL 1 DRAM 60ns CPU 20MHz page mode read write cycle 1 RAS cycle CAS cycle RAS precharge 2 CAS cycle 2 1 tRAS BCLK A 11 0 RAS CAS RD D 15 0 RD WE D 15 0 WR ROW 1 RD data RD data WR data WR data COL 1 COL 2 DRAM 60ns CPU 20MHz CAS before RAS refresh cycle 1 1 RPC delay Fixed Refresh RAS pulse width 2 RAS precharge 1 tRPC tCSR tCHR tRAS BCLK RAS CA...

Page 137: ...timing Burst ROM and mask ROM interface 33MHz 25MHz 20MHz Parameter Symbol Min Max Cycle Time Cycle Time Cycle Time Access time tACC 100 5 150 4 160 3 150 CE output delay time tCE 100 5 150 4 160 3 150 OE output delay time tOE 50 4 5 135 3 5 140 2 5 125 Burst access time tBAC 50 3 90 2 80 2 100 Output disable delay time tDF 0 40 1 5 45 1 5 60 1 5 75 ROM 100ns CPU 33MHz normal read tACC tCE tOE BCL...

Page 138: ... RD D 15 0 RD data ROM 100ns CPU 25MHz burst read Normal read cycle Burst read cycle BCLK A 23 0 CE9 10 RD D 15 0 RD data RD data RD data RD data ROM 100ns CPU 20MHz normal read BCLK A 23 0 CE9 10 RD D 15 0 RD data ROM 100ns CPU 20MHz burst read Normal read cycle Burst read cycle BCLK A 23 0 CE9 10 RD D 15 0 RD data RD data RD data RD data ...

Page 139: ...time tRC 55 3 90 3 120 2 100 Address access time tACC 55 3 90 3 120 2 100 CE access time tACS 55 3 90 3 120 2 100 OE access time tOE 30 2 5 75 2 5 100 1 5 75 Output disable delay time tOHZ 0 30 1 5 45 1 5 60 1 5 75 Write cycle Write cycle time tWC 55 3 90 3 120 2 100 Address enable time tAW 50 2 5 75 2 5 100 1 5 75 Write pulse width tWP 45 2 60 2 80 1 50 Input data setup time tDW 30 2 60 2 80 1 50...

Page 140: ...A REFERENCE EXTERNAL DEVICE INTERFACE TIMINGS A 124 EPSON S1C33L03 PRODUCT PART SRAM 55ns CPU 20MHz read cycle BCLK A 23 0 CEx RD D 15 0 RD data SRAM 55ns CPU 20MHz write cycle BCLK A 23 0 CEx WR D 15 0 WR data ...

Page 141: ...me tRC 70 4 120 3 120 3 150 Address access time tACC 70 4 120 3 120 3 150 CE access time tACS 70 4 120 3 120 3 150 OE access time tOE 40 3 5 105 2 5 100 2 5 125 Output disable delay time tOHZ 0 30 1 5 45 1 5 60 1 5 75 Write cycle Write cycle time tWC 70 4 120 3 120 3 150 Address enable time tAW 60 3 5 105 2 5 100 2 5 125 Write pulse width tWP 55 3 90 2 80 2 100 Input data setup time tDW 30 3 90 2 ...

Page 142: ...EFERENCE EXTERNAL DEVICE INTERFACE TIMINGS A 126 EPSON S1C33L03 PRODUCT PART SRAM 70ns CPU 25 20MHz read cycle BCLK A 23 0 CEx RD D 15 0 RD data SRAM 70ns CPU 25 20MHz write cycle BCLK A 23 0 CEx WR D 15 0 WR data ...

Page 143: ... 400 14 420 11 440 9 450 Input data setup time tDW 100 14 420 11 440 9 450 Input data hold time 3 tDH 30 0 5 15 0 5 20 0 5 25 1 The S1C33L03 enables up to 7 cycles of wait cycle insertion If a number of wait cycles more than 7 cycles needs to be inserted input the WAIT signal from external hardware Note that the interface must be set for SRAM type devices to insert wait cycles using the WAIT pin R...

Page 144: ...VTTL Type3 VDDE 20 FPDAT0 GPO3 XHBC3BT CMOS LVTTL Type3 VDDE 21 VDDE HVDD 22 DRDY MOD FPSHIFT2 XHBC3BT CMOS LVTTL Type3 VDDE 23 FPFRAME XHBC3BT CMOS LVTTL Type3 VDDE 24 FPLINE XHBC3BT CMOS LVTTL Type3 VDDE 25 FPSHIFT XHBC3BT CMOS LVTTL Type3 VDDE 26 LCDPWR XHTB1T Type1 VDDE 27 VSS VSS 28 K67 AD7 XHIBCLINW CMOS LVTTL AVDDE note 1 29 K66 AD6 XHIBCLINW CMOS LVTTL AVDDE note 1 30 K65 AD5 XHIBCLINW CMO...

Page 145: ...1 SIN3 SDA10 XHBH1T CMOS LVTTL SCHMITT Type1 VDDE 73 P32 DMAACK0 SRDY3 HDQM XHBH1T CMOS LVTTL SCHMITT Type1 VDDE 74 P31 BUSGET GARD GPIO2 XHBH1T CMOS LVTTL SCHMITT Type1 VDDE 75 P30 WAIT CE4 5 XHBH1T CMOS LVTTL SCHMITT Type1 VDDE 76 LCAS SDRAS XHTB1T Type1 VDDE 77 HCAS SDCAS XHTB1T Type1 VDDE 78 VDD LVDD 79 P21 DWE GAAS SDWE XHBH1T CMOS LVTTL SCHMITT Type1 VDDE 80 P20 DRD SDCKE XHBH1T CMOS LVTTL S...

Page 146: ...note 2 123 EA10MD1 XHIBCP2 CMOS LVTTL Pull up VDDE 124 EA10MD0 XHIBC CMOS LVTTL VDDE 125 ICEMD XITST1 Pull down Test pin 126 EMEMRD XHTB1T Type1 VDDE 127 VDD LVDD 128 OSC4 XLLOT VDD 129 OSC3 XLLIN VDD note 2 130 NMI XHIBHP2 CMOS LVTTL SCHMITT Pull up VDDE 131 CE9 CE17 CE17 18 XHBC1T note 3 Type1 VDDE 132 VDDE HVDD 133 CE5 CE15 CE15 16 XHBC1T note 3 Type1 VDDE 134 N C 135 CE3 XHTB1T Type1 VDDE 136 ...

Page 147: ...S1C33L03 FUNCTION PART ...

Page 148: ......

Page 149: ...S1C33L03 FUNCTION PART I OUTLINE ...

Page 150: ......

Page 151: ... function 16 bits 16 bits 64 bits 2 clock per MAC 25 MOPS in 50 MHz Registers 32 bits 16 general registers and 32 bits 5 special registers Memory space 256M bytes 28 bits linear space code data IO shared type External bus I F 15 configurable memory areas Direct connection to external memory Interrupts Reset NMI up to 128 external interrupts 4 software interrupts 2 exceptions Reset boot Cold reset ...

Page 152: ...I OUTLINE INTRODUCTION B I 1 2 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK ...

Page 153: ...e S1C33 blocks CORE_PAD Pads C33_SBUS C33 Core Block C33 LCD Controller Block Pads PERI_PAD Pads C33_PERI Prescaler 8 bit timer 16 bit timer Clock timer Serial interface Ports C33 Peripheral Block C33 Analog Block C33_CORE CPU BCU ITC CLG DBG C33_ADC A D converter C33 Internal Memory Block Internal RAM Area 0 Internal ROM Area 10 C33 DMA Block C33_DMA IDMA HSDMA C33_SDRAMC SDRAM interface C33_LCDC...

Page 154: ...four channels of serial interface input and I O ports and a clock timer C33 Analog Block The C33 Analog Block consists of an A D converter with eight input channels C33 DMA Block The C33 DMA Block is configured with two types of DMA controllers HSDMA High Speed DMA that has on chip registers for controlling DMA command information and IDMA Intelligent DMA that uses a memory area for storing DMA co...

Page 155: ...en CEFUNC 1 0 D A 9 0x48130 01 or 1x A14DRA D8 0x48122 0 and SDRPC1 D2 0x39FFC0 0 RAS3 Area 14 DRAM row strobe when CEFUNC 1 0 D A 9 0x48130 01 or 1x A14DRA D8 0x48122 1 and SDRPC1 D2 0x39FFC0 0 SDCE1 SDRAM chip enable 1 when SDRPC1 D2 0x39FFC0 1 and SDRENA D7 0x39FFC1 1 CE7 RAS0 CE13 RAS2 SDCE0 65 O CE7 Area 7 chip enable when CEFUNC 1 0 D A 9 0x48130 00 A7DRA D7 0x48128 0 and SDRPC0 D3 0x39FFC0 ...

Page 156: ...I O port when CFP30 D0 0x402DC 0 default WAIT Wait cycle request input when CFP30 D0 0x402DC 1 CE4 5 Areas 4 5 chip enable when CFP30 D0 0x402DC 1 and IOC30 D0 0x402DE 1 P20 DRD SDCKE 80 I O P20 I O port when CFP20 D0 0x402D8 0 and SDRENA D7 0x39FFC1 0 default DRD DRAM read signal output for successive RAS mode when CFP20 D0 0x402D8 1 and SDRENA D7 0x39FFC1 0 SDCKE SDRAM clock enable signal when S...

Page 157: ...input when CFP04 D4 0x402D0 1 and CFEX4 D4 0x402DF 0 DMAACK2 HSDMA Ch 2 acknowledge output when CFEX4 D4 0x402DF 1 P06 SCLK1 DMAACK3 10 I O P06 I O port when CFP06 D6 0x402D0 0 and CFEX6 D6 0x402DF 0 default SCLK1 Serial I F Ch 1 clock input output when CFP06 D6 0x402D0 1 and CFEX6 D6 0x402DF 0 DMAACK3 HSDMA Ch 3 acknowledge output when CFEX6 D6 0x402DF 1 P15 EXCL4 DMAEND0 SCLK3 LDQM 84 I O P15 I ...

Page 158: ...rter Ch 7 input when CFK67 D7 0x402C3 1 P00 SIN0 144 I O P00 I O port when CFP00 D0 0x402D0 0 default SIN0 Serial I F Ch 0 data input when CFP00 D0 0x402D0 1 P01 SOUT0 143 I O P01 I O port when CFP01 D1 0x402D0 0 default SOUT0 Serial I F Ch 0 data output when CFP01 D1 0x402D0 1 P02 SCLK0 142 I O P02 I O port when CFP02 D2 0x402D0 0 default SCLK0 Serial I F Ch 0 clock input output when CFP02 D2 0x4...

Page 159: ...402D4 1 IOC15 D5 0x402D6 1 and SDRENA D7 0x39FFC1 0 SCLK3 Serial I F Ch 3 clock input output when SSCLK3 D2 0x402D7 1 CFP15 D5 0x402D4 0 and SDRENA D7 0x39FFC1 0 LDQM SDRAM data low byte input output mask signal when SDRENA D7 0x39FFC1 1 P16 EXCL5 DMAEND1 SOUT3 83 I O P16 I O port when CFP16 D6 0x402D4 0 default EXCL5 16 bit timer 5 event counter input when CFP16 D6 0x402D4 1 and IOC16 D6 0x402D6 ...

Page 160: ...P32 DMAACK0 SRDY3 HDQM 73 I O P32 I O port when CFP32 D2 0x402DC 0 and SDRENA D7 0x39FFC1 0 default DMAACK0 HSDMA Ch 0 acknowledge output when CFP32 D2 0x402DC 1 and SDRENA D7 0x39FFC1 0 SRDY3 Serial I F Ch 3 ready signal input output when SSRDY3 D3 0x402D7 1 CFP32 D2 0x402DC 0 and SDRENA D7 0x39FFC1 0 HDQM SDRAM data high byte input output mask signal when SDRENA D7 0x39FFC1 1 P33 DMAACK1 SIN3 SD...

Page 161: ...crystal oscillator or external clock input OSC2 67 O Low speed OSC1 oscillation output OSC3 129 I High speed OSC3 oscillation input crystal ceramic oscillator or external clock input OSC4 128 O High speed OSC3 oscillation output PLLS 1 0 112 113 I PLL set up pins PLLS1 PLLS0 fin fOSC3 fout fPSCIN 1 1 10 25MHz 20 50MHz 0 1 10 12 5MHz 40 50MHz 0 0 PLL is not used L PLLC 115 Capacitor connecting pin ...

Page 162: ...I OUTLINE LIST OF PINS B I 3 8 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK ...

Page 163: ...S1C33L03 FUNCTION PART II CORE BLOCK ...

Page 164: ......

Page 165: ...facing with on chip Peripheral Macro Cells CORE_PAD Pads C33_SBUS C33 Core Block C33 LCD Controller Block Pads PERI_PAD Pads C33_PERI Prescaler 8 bit timer 16 bit timer Clock timer Serial interface Ports C33 Peripheral Block C33 Analog Block C33_CORE CPU BCU ITC CLG DBG C33_ADC A D converter C33 Internal Memory Block Internal RAM Area 0 Internal ROM Area 10 C33 DMA Block C33_DMA IDMA HSDMA C33_SDR...

Page 166: ...II CORE BLOCK INTRODUCTION B II 1 2 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK ...

Page 167: ... multiplication and accumulation instruction and the multiplication division instructions are available All the internal registers of the S1C33000 can be used The CPU registers and CPU address bus can handle 28 bit addresses However the core block has a 24 bit external address bus A 0 23 so the low order 24 bits of address data can only be delivered to the external address bus and the internal add...

Page 168: ...truction into the stack Therefore when the interrupt processing routine is terminated by the reti instruction the program flow returns to the instruction that follows the halt instruction Note that the HALT mode cannot be canceled with an interrupt factor except for reset and NMI if the PSR is set into interrupt disabled status SLEEP Mode When the CPU executes the slp instruction it suspends the p...

Page 169: ...the chip enable signals are negated In basic HALT mode the BCLK bus clock signal is output and DRAM refresh cycles are generated DMA also operates In HALT2 or SLEEP mode the BCLK signal stops therefore DRAM refresh cycles cannot be generated and DMA stops Additional The contents of the CPU registers and input output port status are retained in the standby mode Almost all control and data registers...

Page 170: ...rupt 2 Edge rising or falling or level High or Low 3 13 19 Base 4C Port input interrupt 3 Edge rising or falling or level High or Low 4 14 20 Base 50 Key input interrupt 0 Rising or falling edge 15 21 Base 54 Key input interrupt 1 Rising or falling edge 16 22 Base 58 High speed DMA Ch 0 High speed DMA Ch 0 end of transfer 5 17 23 Base 5C High speed DMA Ch 1 High speed DMA Ch 1 end of transfer 6 18...

Page 171: ... buffer empty 26 63 reserved 40 64 Base 100 A D converter A D converter end of conversion 27 41 65 Base 104 Clock timer Falling edge of 32 Hz 8 Hz 2 Hz or 1 Hz signal 1 minuet 1 hour or specified time count up 66 67 reserved 44 68 Base 110 Port input interrupt 4 Edge rising or falling or level High or Low 28 45 69 Base 114 Port input interrupt 5 Edge rising or falling or level High or Low 29 46 70...

Page 172: ...II CORE BLOCK CPU AND OPERATING MODE B II 2 6 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK ...

Page 173: ...e vector at the boot address is loaded to the PC CPU PSR All the PSR bits are reset to 0 CPU Other registers Undefined CPU Operating clock The CPU operates with the OSC3 clock External bus status 0x48120 0x4813F Initialized Status is retained Oscillation circuit Both the OSC1 and OSC3 circuits start oscillating I O pin status 0x402C0 0x402DF Initialized Status is retained Other peripheral circuit ...

Page 174: ...e or more 3 0 V VDD 3 3 V 0 5VDD 0 1VDD Power on Figure 3 2 Power on Reset Timing Maintain the RESET pin at 0 1 VDD or less low level after turning the power on until the supply voltage rises at least to the oscillation start voltage 3 0 V Furthermore maintain the RESET pin at 0 5 VDD or less until the high speed OSC3 oscillation circuit stabilizes oscillating Note The OSC3 oscillation start time ...

Page 175: ...ained at low until the OSC3 oscillation stabilizes when performing a power on reset or resetting while the high speed OSC3 oscillation circuit is stopped Low speed OSC1 oscillation circuit A power on reset or an initial reset when the low speed OSC1 oscillation circuit is off starts the OSC1 oscillation The low speed OSC1 oscillation circuit takes a longer stabilization time 3 sec max under the st...

Page 176: ...II CORE BLOCK INITIAL RESET B II 3 4 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK ...

Page 177: ...E7 RAS0 CE13 RAS2 SDCE0 O Area 7 13 chip enable DRAM Row strobe SDRAM chip enable 0 CE6 CE7 8 O Area 6 7 8 chip enable CE5 CE15 CE15 16 O Area 5 15 15 16 chip enable CE4 CE11 CE11 12 O Area 4 11 11 12 chip enable RD O Read signal EMEMRD O Read signal for area 3 10 emulation mode WRL WR WE O Write Low byte Write DRAM write WRH BSH O Write High byte Bus strobe High byte HCAS SDCAS O DRAM column addr...

Page 178: ... 1 This signal goes low when the CPU write 8 low order bit data to the user logic Internal_wrh_x O Write high byte signal WRH when SBUSST D3 0x4812E 0 default Bus strobe high byte signal BSH when SBUSST D3 0x4812E 1 This signal goes low when the CPU write 8 high order bit data to the user logic Internal_osc3_clk O High speed OSC3 oscillation clock output This can be used as a source clock for the ...

Page 179: ... BSL system SBUSST D3 0x4812E 1 DRAM interface 2CAS system fixed None SBUSST is initialized to 0 at cold start When the IC is hot started these bits retain their status before the chip was reset Table 4 4 shows combinations of control signals classified by each interface method Table 4 4 Combinations of Bus Control Signals External system interface DRAM interface A0 system BSL system 2CAS system A...

Page 180: ...FFF 0x1000000 0x0FFFFFF 0x0C00000 Area Area 18 SRAM type 8 or 16 bits Area 17 SRAM type 8 or 16 bits Area 16 SRAM type 8 or 16 bits Area 15 SRAM type 8 or 16 bits Area 14 SRAM type DRAM type 8 or 16 bits Area 13 SRAM type DRAM type 8 or 16 bits Area 12 SRAM type 8 or 16 bits Area 11 SRAM type 8 or 16 bits Area 10 SRAM type Burst ROM type 8 or 16 bits Address External memory 8MB External memory 8MB...

Page 181: ...more when CEFUNC is set to 10 or 11 five chip enable signals are expanded into two area size Although the C33 Core Block has only 24 address output pins it features 28 bit internal address processing Figure 4 2 shows a memory map for an external system 0x0FFFFFF 0x0C00000 0x0BFFFFF 0x0800000 0x07FFFFF 0x0600000 0x05FFFFF 0x0400000 0x03FFFFF 0x0380000 0x037FFFF 0x0300000 0x02FFFFF 0x0200000 0x01FFF...

Page 182: ... CEFUNC 10 or 11 External memory 7 16MB External memory 7 16MB Mirror of External memory 7 Mirror of External memory 7 External memory 6 16MB External memory 6 16MB Mirror of External memory 6 Mirror of External memory 6 Figure 4 2 External System Memory Map Furthermore the CE4 CE5 and CE6 signals can be output from the P30 and P34 terminals respectively This function expands the accessible area w...

Page 183: ...t is used to enable disable the read signal When 1 is written to the bit the exclusive signal for the corresponding area s is enabled and when 0 is written it is disabled disabled by default The bit names and the corresponding areas are as follows A18AS DF A18RD D7 Areas 17 and 18 A16AS DE A16RD D6 Areas 15 and 16 A14AS DD A14RD D5 Areas 13 and 14 A12AS DC A12RD D4 Areas 11 and 12 A8AS DA A8RD D2 ...

Page 184: ...s min 16 KB max 2 MB using the A10IR 2 0 D E C Areas 10 9 set up register 0x48126 This ROM begins with address 0xC00000 and can be read in one cycle the same as that of area 3 For the remained area within area 10 the external memory will be accessed if it is available External ROM boot mode The CPU boots by the external ROM ROM Flash SRAM etc This mode uses the bus condition set by the BCU registe...

Page 185: ...F External memory is accessed Set up example 25 MHz 5 wait Internal or emulation memory is accessed Set up example 25 MHz X2SPD 1 25 MHz X2SPD 0 No wait 16KB 32KB 64KB 128KB 256KB 512KB 1MB or 2MB selected by A10IR 2 0 Figure 4 4 Area 10 Memory Map Area 3 Area 3 is reserved for S1C33 middleware To use this area external emulation memory is used When external emulation memory is used A3EEN DB 0x481...

Page 186: ...A9DRA D7 Areas 10 9 set up register 0x48126 8 X A8DRA D8 Areas 8 7 set up register 0x48128 7 X A7DRA D7 Areas 8 7 set up register 0x48128 6 4 X X None Can be connected X Cannot be connected When connecting burst ROM or DRAM write 1 to each corresponding control bit These control bits are reset to 0 SRAM type at cold start The device size can be set to 8 or 16 bits once every two areas except for a...

Page 187: ...area using the control bit the BCU extends the bus cycle for a duration equivalent to the wait cycles set when it accesses the area Set the desired wait cycles according to the bus clock frequency and the external device s access time Separately from the wait cycles set here a wait request from an external device can also be accepted using the WAIT pin Since the settings of wait cycles using softw...

Page 188: ...e following conditions immediately after a write cycle and during a successive read from the same external device Setting Timing Conditions of Burst ROM Wait cycles If burst ROM is selected for area 10 or 9 the wait cycles to be inserted in the burst read cycle can be selected in a range from 0 to 3 cycles A10BW 1 0 D A 9 Areas 10 9 set up register 0x48126 is used for this selection This selection...

Page 189: ...s on exact boundary addresses in order to minimize invalid areas Bus Operation of External Memory The external data bus is 16 bits wide For this reason more than one bus operation occurs depending on the device size and the data size of the instruction executed as shown in Table 4 13 Table 4 13 Number of Bus Operation Cycles Data size to be accessed Devise size Number of bus operation cycles Remar...

Page 190: ...0 0 A1 0 1 No 1 2 Byte 2 Byte 1 Byte 0 Bus operation 2 1 Byte 3 Byte 2 Byte 1 Byte 0 31 0 Destination general purpose register A 1 0 00 A 1 0 10 Source 16 bit device 15 0 15 0 Big endian Figure 4 6 Word Data Reading from a 16 bit Device Byte 1 15 Data bus 0 WRL 0 WRH 0 A0 0 A1 No 1 Byte 0 Byte 3 Byte 2 Byte 1 Byte 0 31 0 A 1 0 0 0 1 15 Source general purpose register Destination 16 bit device Bus ...

Page 191: ... A1 0 0 1 1 No 1 2 3 4 Byte 0 Data retained Byte 1 Data retained Byte 2 Data retained Byte 3 Byte 3 Byte 2 Byte 1 Byte 0 31 0 A 1 0 10 A 1 0 00 A 1 0 11 A 1 0 01 8 0 1 4 8 8 8 0 0 0 Source general purpose register Destination 8 bit device 3 2 Bus operation X Not connected Unused Little endian Byte 3 15 Data bus 0 WRL 1 1 1 1 WRH 0 0 0 0 A0 0 1 0 1 A1 0 0 1 1 No 1 2 3 4 Data retained Byte 2 Data re...

Page 192: ...A0 0 1 A1 No 1 2 Ignored Byte 0 Ignored Byte 1 Byte 0 31 0 A 1 0 1 A 1 0 0 0 2 8 8 0 1 Bus operation Destination general purpose register Sign or Zero extension Big endian Uniformly 1 or 0 Figure 4 14 Half word Data Reading from an 8 bit Device Data retained 15 Data bus 0 WRL 0 WRH X A0 A1 No 1 Byte 0 Byte 3 Byte 2 Byte 1 Byte 0 31 0 A 1 0 0 1 8 Source general purpose register Destination 8 bit de...

Page 193: ...RENA SD_CLK SDRAMC 1 1 or 1 2 Refresh counter BCLK pin PLL_CLK and CPU_CLK BCU_CLK SD_CLK When X2SPD 1 OSC3_CLK PLL off PLL_CLK PLL x2 mode PLL_CLK PLL x4 mode A CPU_CLK CLKDT 1 1 CPU_CLK CLKDT 1 2 CPU_CLK CLKDT 1 4 CPU_CLK CLKDT 1 8 CPU_CLK BCU_CLK X2SPD 1 x1 speed mode BCU_CLK X2SPD 0 x2 speed mode when the CPU system clock source is OSC3 1 1 Access to the internal RAM 2 Access to the external m...

Page 194: ...x2 speed mode CPU bus clock ratio is 2 1 is set In x2 speed mode the bus clock will be dynamically varied according to the memory to be accessed When an external memory area is accessed the bus clock frequency becomes half of the CPU system clock When the internal RAM ROM area is accessed the bus clock frequency becomes equal to the CPU system clock In x1 speed mode area 1 internal I O area is acc...

Page 195: ...Sample DRAM Connection SRAM Read Cycles Basic read cycle with no wait mode BCLK A 23 0 CExx D 15 0 RD WAIT addr data C1 Figure 4 19 Basic Read Cycle with No Wait Read cycle with wait mode Example When the BCU has no internal wait mode and 2 wait cycles via WAIT pin are inserted BCLK A 23 0 CExx D 15 0 RD WAIT C1 CW CW addr data Figure 4 20 Read Cycle with Wait The WAIT signal is sampled at the fal...

Page 196: ...dress and chip enable signals BCLK A 23 0 CE4 CE7 RD addr Hazard occurrence This hazard causes an erroneous RD operation on the next area Figure 4 21 Trouble Case Output disable cycle When an output disable cycle set with output disable delay time parameter is inserted the chip enable CExx signal temporarily goes high This makes an interval between the next read cycle Note however that no output d...

Page 197: ... BSL BSH addr data C1 C2 Figure 4 22 Half word Write Cycle with No Wait BCLK A 23 0 CExx WRH WRL D 15 8 D 7 0 C1 C2 C3 C4 addr Undefined Valid Valid Undefined Figure 4 23 Byte Write Cycle with No Wait A0 system little endian BCLK A 23 0 CExx BSH BSL WRL D 15 8 D 7 0 C1 C2 C3 C4 addr Undefined Valid Valid Undefined Figure 4 24 Byte Write Cycle with No Wait BSL system little endian ...

Page 198: ...for waiting The above example shows a write cycle when a wait mode is inserted via the WAIT signal A wait mode consisting of 2 to 7 cycles can also be inserted using the wait control bits The settings of these bits also can be used in combination with the WAIT signal In this case as well the WAIT signal is sampled at the falling edge of the transition of BCLK However even when the WAIT signal is i...

Page 199: ...ive bursts 2 Word 32 bit data read out Note A 16 bit output is supported for the burst ROM Set the device size to 16 bits Wait cycles during burst read In the first bus operation 0 to 7 wait cycles can be inserted using the wait control bits A10WT 2 0 D 2 0 Areas 10 9 set up register 0x48126 in the same way as for ordinary SRAM For the wait cycles to be inserted in the burst cycle that follows use...

Page 200: ...eas 8 and 7 default CE8 and CE7 function as RAS0 and RAS1 respectively CEFUNC 00 DRAM can be connected to areas 14 and 13 CE14 and CE13 function as RAS2 and RAS3 respectively Figure 4 27 shows a sample DRAM connection Table 4 15 and Table 4 16 show examples of connectable DRAMs and typical configurations A 9 1 D 15 0 RD RASx CEx HCAS LCAS WE S1C33 A 8 0 I O 15 0 OE RAS HCAS LCAS WE 4M DRAM 256K x ...

Page 201: ...C 1 0 D 1 0 DRAM timing set up register 0x48130 Page mode The DRAM interface allows EDO DRAM to be connected directly Therefore the EDO page mode is supported along with the fast page mode Use REDO to choose the desired page mode that suits the DRAM to be used REDO 1 EDO page mode REDO 0 Fast page mode default Successive RAS mode For applications that require high speed DRAM access the DRAM interf...

Page 202: ...o 9 bits 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 T T T T T T T T 3 Row address when column address is set to 10 bits 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 T T T T T T T T 4 Row address when column address is set to 11 bits 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 T T T T T T T T T T T T T T Figure 4 28 Example of Row Column Address Mapping Refresh enable U...

Page 203: ...Number of RAS precharge cycles Use RPRC to choose the number of RAS precharge cycles Table 4 20 Number of RAS Precharge Cycles RPRC1 RPRC0 Number of cycles 1 1 4 cycles 1 0 3 cycles 0 1 2 cycles 0 0 1 cycle The initial default value is 1 cycle CAS cycle control Use CASC to choose the number of CAS cycles when accessing DRAM Table 4 21 Number of CAS Cycles CASC1 CASC0 Number of cycles 1 1 4 cycles ...

Page 204: ...ure 4 29 DRAM Random Read Cycle DRAM read cycle fast page mode Example RAS 1 cycle CAS 2 cycles Precharge 1 cycle BCLK A 11 0 RASx HCAS LCAS RD D 15 0 ROW COL 1 COL 2 data data RAS cycle CAS cycle 1 CAS cycle 2 Precharge cycle Figure 4 30 DRAM Read Cycle fast page mode DRAM read cycle EDO page mode Example RAS 1 cycle CAS 2 cycles Precharge 1 cycle BCLK A 11 0 RASx HCAS LCAS RD D 15 0 ROW COL 1 CO...

Page 205: ...e Example RAS 1 cycle CAS 2 cycles Precharge 1 cycle word write sample ROW COL 1 COL 2 write data RAS cycle CAS cycle 1 CAS cycle 2 Precharge cycle BCLK A 11 0 RASx HCAS LCAS WE D 15 0 write data Figure 4 33 DRAM Word Write Cycle fast page or EDO page mode Example RAS 1 cycle CAS 2 cycles Precharge 1 cycle byte write sample little endian ROW COL write data BCLK A 11 0 RASx HCAS LCAS WE D 15 8 D 7 ...

Page 206: ...ins asserted while some other device is accessed In this case a cycle to temporarily deassert DRD DWE is inserted before accessing the other device 3 If access to the same page in the same DRAM area as in 1 is requested after 2 DRD DWE is asserted back again to restart the page mode 4 A precharge cycle is executed when one of the following conditions that cause the page mode to suspend is encounte...

Page 207: ...erminated the HCAS LCAS signal boot timing is 0 5 cycles before that of RAS Consequently the pulse width of HCAS LCAS is determined by the refresh RAS pulse width that was set using RRA The number of precharge cycles after the refresh cycle is defined by the value that was set using RPRC the same value that is used for both random cycles and page mode accesses Self refresh To support DRAM chips eq...

Page 208: ...ontrol of the bus is released This sequence is described below 1 The external bus master device requesting control of the bus ownership lowers the BUSREQ pin 2 The CPU keeps monitoring the status of the BUSREQ pin so that when this pin is lower the CPU terminates the bus cycle being executed and places the signals listed below in high impedance state one cycle later A 23 0 D 15 0 RD WRL WRH HCAS L...

Page 209: ...h request signal output from the 8 bit programmable timer 0 2 Interrupt request signal from the interrupt controller to the CPU 3 Startup request signal from the interrupt controller to the IDMA If the BUSGET signal is found to be active when the external bus master is monitoring it release BUSREQ back high to drop the request for bus ownership control When using the BUSGET signal to only monitor ...

Page 210: ...served Areas 16 15 device size selection Areas 16 15 output disable delay time reserved Areas 16 15 wait control 1 8 bits 0 16 bits 1 8 bits 0 16 bits 0 1 1 1 1 1 0 1 1 1 1 1 R W R W R W R W R W R W 0 when being read 0 when being read 0 when being read 0 when being read 0048120 HW Areas 18 15 set up register 1 1 0 0 1 0 1 0 A18DF 1 0 Number of cycles 3 5 2 5 1 5 0 5 1 1 0 0 1 0 1 0 A16DF 1 0 Numbe...

Page 211: ...selection Areas 10 9 output disable delay time reserved Areas 10 9 wait control 1 Used 0 Not used 1 Used 0 Not used 1 8 bits 0 16 bits 1 1 1 0 0 0 0 0 1 1 1 1 1 R W R W R W R W R W R W R W 0 when being read 0 when being read 0 when being read 0048126 HW 1 1 0 0 1 0 1 0 A10BW 1 0 Wait cycles 3 2 1 0 1 1 0 0 1 0 1 0 A10DF 1 0 Number of cycles 3 5 2 5 1 5 0 5 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1...

Page 212: ...3 2 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 A5WT 2 0 Wait cycles 7 6 5 4 3 2 1 0 RBCLK RBST8 REDO RCA1 RCA0 RPC2 RPC1 RPC0 RRA1 RRA0 SBUSST SEMAS SEPD SWAITE DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BCLK output control reserved Burst ROM burst mode selection DRAM page mode selection Column address size selection Refresh enable Refresh method selection Refresh RPC delay setup Ref...

Page 213: ...ternal external access Area 5 4 internal external access Area 18 17 endian control Area 16 15 endian control Area 14 13 endian control Area 12 11 endian control Area 10 9 endian control Area 8 7 endian control Area 6 endian control Area 5 4 endian control 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 when being read 0048132 HW Access control register...

Page 214: ...he output disable delay time Table 4 24 Output Disable Delay Time AxxDF1 AxxDF0 Delay time 1 1 3 5 cycles 1 0 2 5 cycles 0 1 1 5 cycles 0 0 0 5 cycles When using a device that has a long output disable time set a delay time to ensure that no contention for the data bus occurs during the bus operation immediately after a device is read At cold start these bits are set to 11 3 5 cycles At hot start ...

Page 215: ...g initialized A10IR2 A10IR0 Area 10 internal ROM size selection D E C Areas 10 9 set up register 0x48126 Select an area 10 internal emulation memory size Table 4 25 Area 10 Internal ROM Size A10IR2 A10IR1 A10IR0 ROM size 0 0 0 16 KB 0 0 1 32 KB 0 1 0 64 KB 0 1 1 128 KB 1 0 0 256 KB 1 0 1 512 KB 1 1 0 1 MB 1 1 1 2 MB At cold start A10IR is set to 111 2 MB At hot start A10IR retains its status befor...

Page 216: ...bled by writing 0 to RBCLK The bus clock output from the BCLK pin also is stopped in the HALT2 and the SLEEP modes At cold start the RBCLK is set to 0 output enabled At hot start RBCLK retains its status before being initialized RBST8 Burst mode selection DD Bus control register 0x4812E Set the operation mode during a burst read Write 1 8 successive burst mode Write 0 4 successive burst mode Read ...

Page 217: ...art RPC2 retains its status before being initialized RPC1 Refresh method selection D8 Bus control register 0x4812E Select the DRAM refresh method Write 1 Self refresh Write 0 CAS before RAS refresh Read Valid To perform a CAS before RAS refresh set RPC1 to 0 and then RPC2 to 1 This causes the underflow output signal of the 8 bit programmable timer 0 is fed to the DRAM interface at which timing a r...

Page 218: ...d start SBUSST is set to 0 A0 system At hot start SBUSST retains its status before being initialized SEMAS External bus master setup D2 Bus control register 0x4812E Specify whether an external bus master exists Write 1 Existing Write 0 Nonexistent Read Valid A request for bus ownership control via the BUSREQ pin is made acceptable by writing 1 to SEMAS If the system does not have any external bus ...

Page 219: ... Select area 3 emulation mode Write 1 Internal ROM mode Write 0 Emulation mode Read Valid When 0 is written to A3EEN internal ROM emulation mode is selected and the external device will be accessed with the same condition as the internal ROM When 1 is written the internal ROM will be used for accessing area 3 This bit functions the same as the EA3MD pin The bit status and the pin status are logica...

Page 220: ...4 29 Number of RAS Precharge Cycles RPRC1 RPRC0 Number of cycles 1 1 4 cycles 1 0 3 cycles 0 1 2 cycles 0 0 1 cycle The contents set here are applied to all of areas 14 13 8 and 7 that are set for DRAM At cold start RPRC is set to 0 1 cycle At hot start RPRC retains its status before being initialized CASC1 CASC0 Number of CAS cycles D 4 3 DRAM timing set up register 0x48130 Select the number of C...

Page 221: ...ntrol register 0x48132 A8EC Areas 8 7 little big endian method selection D2 Access control register 0x48132 A6EC Area 6 little big endian method selection D1 Access control register 0x48132 A5EC Areas 5 4 little big endian method selection D0 Access control register 0x48132 Select either little endian or big endian method for accessing each area Write 1 Big endian Write 0 Little endian Read Valid ...

Page 222: ...peed oscillation is stopped by executing the SLP instruction 3 When the OSC3 high speed oscillation is stopped using the CLG register Note that the PLL_CLK clock is out of phase with the CPU operating clock OSC3_CLK OSC3 high speed oscillation circuit output clock This clock is stable and kept as output except in the following cases 1 When the OSC3 high speed oscillation is stopped by executing th...

Page 223: ...e HALT2 and the SLEEP modes At cold start SDRENA is set to 0 disabled At hot start SDRENA retains its status before being initialized A1X1MD Area 1 access speed D3 BCLK select register 0x4813A Select a number of access cycles for area 1 in x2 speed mode Write 1 2 cycles Write 0 4 cycles Read Valid When x2 speed mode is set X2SPD pin 0 and A1X1MD 1 area 1 is read written in 2 cycles of the CPU syst...

Page 224: ...II CORE BLOCK BCU Bus Control Unit B II 4 48 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK ...

Page 225: ...Intelligent DMA end of transfer 27 29 reserved 12 1E 30 Base 78 16 bit programmable timer 0 Timer 0 comparison B 7 13 1F 31 Base 7C Timer 0 comparison A 8 32 33 reserved 14 22 34 Base 88 16 bit programmable timer 1 Timer 1 comparison B 9 15 23 35 Base 8C Timer 1 comparison A 10 36 37 reserved 16 26 38 Base 98 16 bit programmable timer 2 Timer 2 comparison B 11 17 27 39 Base 9C Timer 2 comparison A...

Page 226: ...t they are written here Maskable interrupt generating conditions A maskable interrupt to the CPU occurs when all of the conditions described below are met The interrupt enable register for the interrupt factor that has occurred is set to 1 The IE Interrupt Enable bit of the Processor Status Register PSR in the CPU is set to 1 The interrupt factor that has occurred has a higher priority level than ...

Page 227: ...the interrupt processing routine In this case since the IL has been changed in 3 only an interrupt that has a higher priority than that of the currently processed interrupt is accepted When the interrupt processing routine is terminated by the reti instruction the PSR is restored to its previous status before the interrupt has occurred The program restarts processing after branching to the instruc...

Page 228: ...ast the reset vector be written to the above address TTBR0 and TTBR3 are read only bits which are fixed at 0 Therefore the trap table starting address always begins with a 1KB boundary address The TTBR register is normally write protected to prevent them from being inadvertently rewritten To remove this write protection function another register TBRP D 7 0 TTBR write protect register 0x4812D byte ...

Page 229: ...rupt request When this bit is reset to 0 no maskable interrupt request is accepted by the CPU When the CPU accepts an interrupt request or some other trap occurs it saves the PSR to the stack and resets the IE bit to 0 Consequently no maskable interrupt request occurring thereafter will be accepted unless the IE bit is set to 1 in software program or the interrupt trap processing routine is termin...

Page 230: ... flag is reset by writing 1 Although multiple interrupt factor flags are located at the same address of the interrupt control register the interrupt factor flags for which 0 has been written can be neither set nor reset Therefore this method ensures that only a specific factor flag is reset However when using read modify write instructions e g bset bclr or bnot note that an interrupt factor flag t...

Page 231: ...interrupt factor or when clearing standby mode HALT or SLEEP mode too the corresponding interrupt enable bit must be set to 1 The interrupt controller outputs an interrupt request to the CPU when the following conditions are met An interrupt factor has occurred and the interrupt factor flag is set to 1 The bit of the interrupt enable register for the interrupt factor that has occurred is set to 1 ...

Page 232: ... level to those of the new interrupt factor before they are output to the CPU The first interrupt request is left pending Roles of the interrupt priority register in CPU processing The CPU compares the content of the interrupt priority register received from the interrupt controller with the interrupt level that is set in the IL of the PSR to determine whether or not to accept the interrupt reques...

Page 233: ...ting 0 and set by writing 1 In this case all IDMA request bits for which 0 has been written are reset Even in a read modify write operation an IDMA request bit can be reset by the hardware between the read and the write so be careful when using this method IDMA enable register To perform IDMA transfer using an interrupt factor the corresponding bit of the IDMA enable register must be set to 1 If t...

Page 234: ...ctor occurs next time as well To ensure that no unwanted IDMA request occurs this setup must be performed after resetting the interrupt factor flag Figure 5 2 shows the hardware sequence when DINTEN is set to 1 3 2 1 0 IDMA trigger interrupt factor flag Transfer counter Data transfer Reset A signal reset interrupt factor flag Reset B signal reset IDMA request bit IDMA request bit Interrupt request...

Page 235: ...8 bit timer 2 underflow 8 bit timer 3 underflow 0110 16 bit timer 0 compare B 16 bit timer 1 compare B 16 bit timer 2 compare B 16 bit timer 3 compare B 0111 16 bit timer 0 compare A 16 bit timer 1 compare A 16 bit timer 2 compare A 16 bit timer 3 compare A 1000 16 bit timer 4 compare B 16 bit timer 5 compare B 16 bit timer 4 compare B 16 bit timer 5 compare B 1001 16 bit timer 4 compare A 16 bit ...

Page 236: ...to 7 0 to 7 PHSD1L2 PHSD1L1 PHSD1L0 PHSD0L2 PHSD0L1 PHSD0L0 D7 D6 D5 D4 D3 D2 D1 D0 reserved High speed DMA Ch 1 interrupt level reserved High speed DMA Ch 0 interrupt level X X X X X X R W R W 0 when being read 0 when being read 0040263 B High speed DMA Ch 0 1 interrupt priority register 0 to 7 0 to 7 PHSD3L2 PHSD3L1 PHSD3L0 PHSD2L2 PHSD2L1 PHSD2L0 D7 D6 D5 D4 D3 D2 D1 D0 reserved High speed DMA ...

Page 237: ...ng read 0 when being read 004026C B Port input 4 5 interrupt priority register 0 to 7 0 to 7 PP7L2 PP7L1 PP7L0 PP6L2 PP6L1 PP6L0 D7 D6 D5 D4 D3 D2 D1 D0 reserved Port input 7 interrupt level reserved Port input 6 interrupt level X X X X X X R W R W 0 when being read 0 when being read 004026D B Port input 6 7 interrupt priority register EK1 EK0 EP3 EP2 EP1 EP0 D7 6 D5 D4 D3 D2 D1 D0 reserved Key in...

Page 238: ...ed DMA Ch 0 X X X X X R W R W R W R W R W 0 when being read 0040281 B DMA interrupt factor flag register 1 Factor is generated 0 No factor is generated F16TC1 F16TU1 F16TC0 F16TU0 D7 D6 D5 4 D3 D2 D1 0 16 bit timer 1 comparison A 16 bit timer 1 comparison B reserved 16 bit timer 0 comparison A 16 bit timer 0 comparison B reserved X X X X R W R W R W R W 0 when being read 0 when being read 0040282 ...

Page 239: ...rt input 7 Port input 6 Port input 5 Port input 4 reserved A D converter SIF Ch 1 transmit buffer empty SIF Ch 1 receive buffer full 0 0 0 0 0 0 0 R W R W R W R W R W R W R W 0 when being read 0040293 B 1 IDMA request 0 Interrupt request 1 IDMA request 0 Interrupt request Serial I F Ch 1 A D port input 4 7 IDMA request register DE16TC0 DE16TU0 DEHDM1 DEHDM0 DEP3 DEP2 DEP1 DEP0 D7 D6 D5 D4 D3 D2 D1...

Page 240: ...gger set up register HSD3S3 HSD3S2 HSD3S1 HSD3S0 HSD2S3 HSD2S2 HSD2S1 HSD2S0 D7 D6 D5 D4 D3 D2 D1 D0 High speed DMA Ch 3 trigger set up High speed DMA Ch 2 trigger set up 0 0 0 0 0 0 0 0 R W R W 0040299 B 0 1 2 3 4 5 6 7 8 9 A B C Software trigger K54 input falling edge K54 input rising edge Port 3 input Port 7 input 8 bit timer Ch 3 underflow 16 bit timer Ch 3 compare B 16 bit timer Ch 3 compare ...

Page 241: ...rrupt factor TM16 function switching register 1 SIO Ch 3 RXD Err 0 TM16 Ch 3 comp A 1 SIO Ch 2 RXD Err 0 TM16 Ch 3 comp B 1 SIO Ch 3 TXD Emp 0 TM16 Ch 4 comp A 1 SIO Ch 3 RXD Full 0 TM16 Ch 4 comp B 1 SIO Ch 2 TXD Emp 0 TM16 Ch 5 comp A 1 SIO Ch 2 RXD Full 0 TM16 Ch 5 comp B 1 T8 Ch 5 UF 0 TM16 Ch 2 comp A 1 T8 Ch 4 UF 0 TM16 Ch 2 comp B TBRP7 TBRP6 TBRP5 TBRP4 TBRP3 TBRP2 TBRP1 TBRP0 D7 D6 D5 D4 ...

Page 242: ...16KB 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 A10WT 2 0 Wait cycles 7 6 5 4 3 2 1 0 Areas 10 9 set up register The following collectively explains the basic functions of each control register bit For details about individual interrupt systems and the contents classified by an interrupt factor refer to the descriptions of the peripheral circuits in this manual Pxxx2 Pxxx0 Interrupt priority ...

Page 243: ...r flag must be reset and the PSR must be set up again by setting the IL below the level indicated by the interrupt priority register and setting the IE bit to 1 or executing the reti instruction The interrupt factor flag can only be reset by a write instruction in the software application If the PSR is again set up to accept interrupts or the reti instruction is executed without resetting the inte...

Page 244: ...ected interrupt factor flags can be read and written as for other registers Therefore the flag is reset by writing 0 and set by writing 1 In this case all factor flags for which 0 has been written are reset Even in a read modify write operation an interrupt factor can occur between read and write instructions so be careful when using this method After an initial reset RSTONLY is set to 1 reset onl...

Page 245: ...an interrupt enable bit can be reset by the hardware between the read and the write so be careful when using this method After an initial reset DENONLY is set to 1 set only method SIO2ES0 SIO Ch 2 receive error FP0 interrupt factor switching D0 Interrupt factor FP function switching register 0x402C5 Switches the interrupt factor Write 1 SIO Ch 2 receive error Write 0 FP0 input Read Valid Set to 1 ...

Page 246: ...underflow FP5 interrupt factor switching D5 Interrupt factor FP function switching register 0x402C5 Switches the interrupt factor Write 1 8 bit timer 4 underflow Write 0 FP5 input Read Valid Set to 1 to use the 8 bit timer 4 underflow interrupt Set to 0 to use the FP5 input interrupt At power on this bit is set to 0 SIO3TS0 SIO Ch 3 transmit buffer empty FP6 interrupt factor switching D6 Interrupt...

Page 247: ... Ch 4 compare B interrupt factor switching D2 Interrupt factor TM16 function switching register 0x402CB Switches the interrupt factor Write 1 SIO Ch 3 receive buffer full Write 0 TM16 Ch 4 compare B Read Valid Set to 1 to use the SIO Ch 3 receive buffer full interrupt Set to 0 to use the TM16 Ch 4 compare B interrupt At power on this bit is set to 0 SIO3TS1 SIO Ch 3 transmit buffer empty TM16 Ch 4...

Page 248: ... to 0 to use the TM16 Ch 2 compare B interrupt At power on this bit is set to 0 T8CH5S1 8 bit timer 5 underflow TM16 Ch 2 compare A interrupt factor switching D7 Interrupt factor TM16 function switching register 0x402CB Switches the interrupt factor Write 1 8 bit timer 5 underflow Write 0 TM16 Ch 2 compare A Read Valid Set to 1 to use the 8 bit timer 5 underflow interrupt Set to 0 to use the TM16 ...

Page 249: ...e the high speed OSC3 oscillation circuit also starts operating However if an interrupt to be generated upon completion of IDMA is disabled at the setting of IDMA side no interrupt request is signaled to the CPU Therefore the CPU remains idle until the next interrupt request is generated 2 As the S1C33000 Core CPU function the IL allows interrupt levels to be set in the range of 0 to 15 However si...

Page 250: ...II CORE BLOCK ITC Interrupt Controller B II 5 26 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK ...

Page 251: ...scaler and Low Speed OSC1 Oscillation Circuit of the Peripheral Block Figure 6 1 shows the configuration of the clock generator High speed OSC3 oscillation circuit Clock switch CLKCHG To CPU SLEEP OSC3 OSC4 HALT HALT2 SLEEP SOSC3 Oscillation ON OFF CLKDT 1 0 Divider 1 1 to 1 8 To BCU and DMA HALT2 SLEEP To peripheral circuits To peripheral circuits and clock timer SLEEP PLL PLLC PLLS0 PLLS1 Low sp...

Page 252: ...illation circuit Optionally an external clock source can be used Figure 6 2 shows the structure of the high speed OSC3 oscillation circuit VSS OSC4 OSC3 Rf CD2 CG2 Oscillation circuit control signal SLEEP status Oscillation circuit control signal SLEEP status X tal2 or Ceramic fOSC3 OSC4 OSC3 External clock N C VSS VDD fOSC3 1 Crystal ceramic oscillation circuit 2 External clock input Figure 6 2 H...

Page 253: ...ave the PLLC pin open Controlling Oscillation The high speed OSC3 oscillation circuit can be turned on or off using SOSC3 D1 Power control register 0x40180 The oscillation circuit is turned off by writing 0 to SOSC3 and turned back on again by writing 1 SOSC3 is set to 1 at initial reset so the oscillation circuit is turned on Notes When the high speed OSC3 oscillation circuit is used as the clock...

Page 254: ...ocessing in low speed operation is possible and the CPU can process its jobs at a low clock speed the CPU operating clock can be switched to the OSC1 clock thereby reducing current consumption Use CLKCHG D2 Power control register 0x40180 to switch over the operating clock Procedure for switching over from the OSC3 clock to the OSC1 clock 1 Turn on the low speed OSC1 oscillation circuit by writing ...

Page 255: ...es 10 ms max when using a 3 3 V crystal resonator for its oscillation to stabilize after oscillation starts To prevent the CPU from operating erratically upon restart during this period the C33 Core Block is designed to allow the OSC3 clock supply to the CPU to be disabled in the hardware after SLEEP mode is exited Use 8T1ON D2 Clock option register 0x40190 to select this function Use 8 bit progra...

Page 256: ...r off Write 1 OSC1 oscillation turned on Write 0 OSC1 oscillation turned off Read Valid The oscillation of the low speed OSC1 oscillation circuit is stopped by writing 0 to SOSC1 and started again by writing 1 Since a duration of maximum three seconds is required for oscillation to stabilize after the oscillation has been restarted at least this length of time must pass before the OSC1 clock can b...

Page 257: ... 0 is set to 0b10010110 At initial reset CLKDT is set to 0 fout 1 8T1ON High speed OSC3 oscillation waiting function D2 Clock option register 0x40190 Sets the function for waiting until the high speed OSC3 oscillation stabilizes after SLEEP mode is exited Write 1 Off Write 0 On Read Valid After SLEEP mode is exited the high speed OSC3 oscillation waiting function is effective by writing 1 to 8T1ON...

Page 258: ...not masked interrupt factors Note however that an interrupt from a peripheral circuit can restart the CPU only when the operating clock is supplied to the peripheral circuit SLEEP mode The CPU clock is stopped CPU stop status BCU clock is stopped BCU stop status Clocks for the peripheral circuits are stopped The high speed oscillation circuit is stopped The low speed oscillation circuit maintains ...

Page 259: ... HALT mode not HALT2 mode with a setting of 0 in clock option register HLT2OP D3 0x40190 that operation will be an unpredictable erroneous operation If a DMA trigger occurs and DMA is invoked while the CPU is stopped after HALT mode execution erroneous operation will result Ensure that DMA is not invoked in HALT mode In HALT2 mode DMA is not invoked since the DMA and BCU clocks are stopped 7 In th...

Page 260: ... driven with these clocks debugging functions such as memory dump as well as program execution may not operate correctly Therefore prescribe remedies for malfunctions when debugging for example changing the number of wait cycles and other parameters in the BCU registers using the debugger so that the program can be executed and debugged without problems even when the division ratio changes to 1 1 ...

Page 261: ...output for debugging DST2 O 0 3 3 V Status output 2 for debugging DST1 O 1 3 3 V Status output 1 for debugging DST0 O 1 3 3 V Status output 0 for debugging DPCO O 1 3 3 V PC output for debugging DSIO I O With pull up 1 Input 3 3 V Serial I O for debugging The DCLK DST 2 0 and DPCO outputs are extended functions of the I O port pins P14 P1 2 0 and P13 respectively At initial reset these pins are se...

Page 262: ...II CORE BLOCK DBG Debug Unit B II 7 2 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK ...

Page 263: ...S1C33L03 FUNCTION PART III PERIPHERAL BLOCK ...

Page 264: ......

Page 265: ...SC1 oscillation circuit and a clock timer CORE_PAD Pads C33_SBUS C33 Core Block C33 LCD Controller Block Pads PERI_PAD Pads C33_PERI Prescaler 8 bit timer 16 bit timer Clock timer Serial interface Ports C33 Peripheral Block C33 Analog Block C33_CORE CPU BCU ITC CLG DBG C33_ADC A D converter C33 Internal Memory Block Internal RAM Area 0 Internal ROM Area 10 C33 DMA Block C33_DMA IDMA HSDMA C33_SDRA...

Page 266: ...III PERIPHERAL BLOCK INTRODUCTION B III 1 2 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK ...

Page 267: ...rammable timer 5 0 A D converter Figure 2 1 Configuration of Prescaler and Clock Control Circuit Source Clock The source clock for the prescaler can be selected using PSCDT0 D0 Prescaler clock select register 0x40181 When PSCDT0 0 the OSC3 clock when the PLL is not used or the PLL output clock when the PLL is used is selected When PSCDT0 1 the OSC1 clock typ 32 kHz is selected At initial reset the...

Page 268: ... 0x4014F 1 to 4 See Table 2 2 Table 2 2 Division Ratio Bit setting 7 6 5 4 3 2 1 0 1 θ 4096 θ 1024 θ 256 θ 64 θ 16 θ 4 θ 2 θ 1 2 θ 256 θ 128 θ 64 θ 32 θ 16 θ 8 θ 4 θ 2 3 θ 4096 θ 2048 θ 1024 θ 512 θ 256 θ 128 θ 64 θ 32 4 θ 4096 θ 2048 θ 64 θ 32 θ 16 θ 8 θ 4 θ 2 θ Source clock selected by PSCDT0 Current consumption can be reduced by turning off the clock output to the peripheral circuits that are u...

Page 269: ...k selection 8 bit timer 2 clock selection 8 bit timer 1 clock selection 8 bit timer 0 clock selection 0 0 0 0 R W R W R W R W 0 when being read θ selected by Prescaler clock select register 0x40181 0040146 B 1 θ 1 0 Divided clk 1 θ 1 0 Divided clk 1 θ 1 0 Divided clk 1 θ 1 0 Divided clk 8 bit timer clock select register P16TON0 P16TS02 P16TS01 P16TS00 D7 4 D3 D2 D1 D0 reserved 16 bit timer 0 clock...

Page 270: ...0 D7 4 D3 D2 D1 D0 reserved 16 bit timer 5 clock control 16 bit timer 5 clock division ratio selection 0 0 0 0 R W R W 0 when being read θ selected by Prescaler clock select register 0x40181 004014C B 1 On 0 Off 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 P16TS5 2 0 Division ratio θ 4096 θ 1024 θ 256 θ 64 θ 16 θ 4 θ 2 θ 1 16 bit timer 5 clock control register 1 On 0 Off P8TON1 P8TS12 P8TS11 P8...

Page 271: ...ved CPU operating clock switch High speed OSC3 oscillation On Off Low speed OSC1 oscillation On Off 1 On 0 Off 1 OSC3 0 OSC1 1 On 0 Off 1 On 0 Off 0 0 1 0 1 1 1 R W R W R W R W R W Writing 1 not allowed 0040180 B 1 1 0 0 1 0 1 0 CLKDT 1 0 Division ratio 1 8 1 4 1 2 1 1 Power control register PSCDT0 D7 1 D0 reserved Prescaler clock selection 0 0 R W 0040181 B Prescaler clock select register 1 OSC1 ...

Page 272: ...bit timer 0 clock control register 0x40147 P16TS1 2 0 16 bit timer 1 clock division ratio D 2 0 16 bit timer 1 clock control register 0x40148 P16TS2 2 0 16 bit timer 2 clock division ratio D 2 0 16 bit timer 2 clock control register 0x40149 P16TS3 2 0 16 bit timer 3 clock division ratio D 2 0 16 bit timer 3 clock control register 0x4014A P16TS4 2 0 16 bit timer 4 clock division ratio D 2 0 16 bit ...

Page 273: ...ol the clock supply to each peripheral circuit Write 1 On Write 0 Off Read Valid The clock selected using the division ratio setup bits is output to the corresponding peripheral circuit by writing 1 to these bits The clock is not output by writing 0 If the peripheral circuits do not need to be operated write 0 to these bits This helps to reduce current consumption At initial reset all of these bit...

Page 274: ...n the prescaler is turned off PSCON D5 Power control register 0x40180 0 as well as the peripheral circuits that use the prescaler output clock The prescaler status affects the peripheral circuits shown below A Peripheral circuits that use the clock generated by the prescaler 16 bit programmable timers watchdog timer 8 bit programmable timers DRAM refresh serial interface A D converter B Peripheral...

Page 275: ... input 8 bit timer 1 output DST1 output CFP11 D1 P1 function select register 0x402D4 CFEX1 D1 Port function extension register 0x402DF P12 EXCL2 T8UF2 I O I O port 16 bit timer 2 event counter input 8 bit timer 2 output DST2 output CFP12 D2 P1 function select register 0x402D4 CFEX0 D0 Port function extension register 0x402DF P13 EXCL3 T8UF3 I O I O port 16 bit timer 3 event counter input 8 bit tim...

Page 276: ...xternal bus the underflow signal from timer 0 can be used as a DRAM refresh request signal This enables the intervals of the refresh cycle to be programmed To use this function write 1 to the BCU s control bit RPC2 D9 Bus control register 0x4812E to enable the DRAM refresh A D conversion start trigger The A D converter enables a trigger for starting the A D conversion to be selected from among fou...

Page 277: ...rammed To use this function write 0 to the serial interface control bit SSCK1 D2 Serial I F Ch 1 control register 0x401E8 to select the internal clock 8 bit programmable timer 4 Clock supply to the Ch 2 serial interface When using the Ch 2 serial interface in the clock synchronized master mode or the internal clock based asynchronous mode the output clock derived from the underflow signal of the 8...

Page 278: ...S5 2 0 D 6 4 P8TON5 D7 8 bit timer 4 5 clock control register 0x40145 Note that the division ratios differ for each timer see Table 3 2 Furthermore the prescaler input clock can be directly supplied to the 8 bit timer by writing 1 to the P8TPCKx bit in the 8 bit timer clock select register 0x40146 Timer 0 clock selection P8TPCK0 D0 8 bit timer clock select register 0x40146 Timer 1 clock selection ...

Page 279: ...er 5 preset PSET5 D1 8 bit timer 5 control register 0x40178 2 When the down counter underflown during counting Since the reload data is preset in the down counter upon underflow its underflow cycle is determined by the value that is set in the reload data register This underflow signal controls each function described in the preceding section Before starting the 8 bit programmable timer set the in...

Page 280: ...A6 0x10 0xF3 Figure 3 2 Basic Operation Timing of Counter Reading out counter data The counter data is read out via a PTDx data buffer The counter data can be read out at any time Timer 0 data PTD0 7 0 D 7 0 8 bit timer 0 counter data register 0x40162 Timer 1 data PTD1 7 0 D 7 0 8 bit timer 1 counter data register 0x40166 Timer 2 data PTD2 7 0 D 7 0 8 bit timer 2 counter data register 0x4016A Time...

Page 281: ...nterface A clock generated from the underflow signal by dividing it by 2 is output to the serial interface through this control The clock output is turned off by writing 0 to PTOUTx and the external output is fixed at 0 and the internal clock output is fixed at 1 Figure 3 3 shows the waveforms of the output signals Underflow signal Underflow signal 2 PTOUTx External output T8UFx pin Clock output F...

Page 282: ...e lowest An interrupt request to the CPU is accepted on the condition that no other interrupt request of a higher priority has been generated It is only when the PSR s IE bit 1 interrupts enabled and the set value of the IL is smaller than the timer interrupt level set by the interrupt priority register that a timer interrupt request is actually accepted by the CPU For details on these interrupt c...

Page 283: ...up register 0x40299 Timer 3 3 HSD3S 3 0 D 7 4 HSDMA Ch 2 3 trigger set up register 0x40299 For HSDMA to be invoked the trigger set up bits should be set to 0101 in advance Transfer conditions etc must also be set on the HSDMA side If the 8 bit timer is selected as the HSDMA trigger the HSDMA channel is invoked through generation of the interrupt factor For details on HSDMA transfer refer to HSDMA ...

Page 284: ...D2 D1 D0 reserved 8 bit timer 1 clock output control 8 bit timer 1 preset 8 bit timer 1 Run Stop control 0 0 R W W R W 0 when being read 0 when being read 0040164 B 1 On 0 Off 1 Preset 0 Invalid 1 Run 0 Stop 8 bit timer 1 control register 0 to 255 RLD17 RLD16 RLD15 RLD14 RLD13 RLD12 RLD11 RLD10 D7 D6 D5 D4 D3 D2 D1 D0 8 bit timer 1 reload data RLD17 MSB RLD10 LSB X X X X X X X X R W 0040165 B 8 bi...

Page 285: ...6 RLD45 RLD44 RLD43 RLD42 RLD41 RLD40 D7 D6 D5 D4 D3 D2 D1 D0 8 bit timer 4 reload data RLD47 MSB RLD40 LSB X X X X X X X X R W 0040175 B 8 bit timer 4 reload data register 0 to 255 PTD47 PTD46 PTD45 PTD44 PTD43 PTD42 PTD41 PTD40 D7 D6 D5 D4 D3 D2 D1 D0 8 bit timer 4 counter data PTD47 MSB PTD40 LSB X X X X X X X X R 0040176 B 8 bit timer 4 counter data register PTOUT5 PSET5 PTRUN5 D7 3 D2 D1 D0 r...

Page 286: ... 0 0 0 0 0 0 R W R W R W R W R W R W R W R W 0040296 B 1 IDMA enabled 0 IDMA disabled 16 bit timer 5 8 bit timer serial I F Ch 0 IDMA enable register CFP16 CFP15 CFP14 CFP13 CFP12 CFP11 CFP10 D7 D6 D5 D4 D3 D2 D1 D0 reserved P16 function selection P15 function selection P14 function selection P13 function selection P12 function selection P11 function selection P10 function selection 0 0 0 0 0 0 0 ...

Page 287: ... depends on the peripheral circuit status and may not indicate the value written to the IOC register At cold start IOC1x is set to 0 input mode At hot start the bit retains its state from prior to the initial reset CFEX1 P10 P11 P13 port extended function D1 Port function extension register 0x402DF CFEX0 P12 P14 port extended function D0 Port function extension register 0x402DF Sets whether the fu...

Page 288: ...d data in the counter Write 1 Preset Write 0 Invalid Read Always 0 The reload data of RLDx is preset in the counter of timer x by writing 1 to PSETx If the counter is preset when in a RUN state the counter starts counting immediately after the reload data is preset If the counter is preset when in a STOP state the reload data that has been preset is retained Writing 0 results in No Operation Since...

Page 289: ...ammable timer interrupt in the range of 0 to 7 At initial reset the content of the P8TM register becomes indeterminate E8TU0 Timer 0 interrupt enable D0 8 bit timer interrupt enable register 0x40275 E8TU1 Timer 1 interrupt enable D1 8 bit timer interrupt enable register 0x40275 E8TU2 Timer 2 interrupt enable D2 8 bit timer interrupt enable register 0x40275 E8TU3 Timer 3 interrupt enable D3 8 bit t...

Page 290: ...ter or by executing the reti instruction The interrupt factor flag can be reset only by writing to it in the software Note that if the PSR is set again to accept interrupts generated or if the reti instruction is executed without resetting the interrupt factor flag the same interrupt occurs again Note also that the value to be written to reset the flag is 1 when the reset only method RSTONLY 1 is ...

Page 291: ...ster bit is set to 0 the IDMA request is disabled After an initial reset DE8TUx is set to 0 IDMA disabled Programming Notes 1 The 8 bit programmable timer operates only when the prescaler is operating 2 Do not use a clock that is faster than the CPU operating clock for the 8 bit programmable timer 3 When setting an input clock make sure the 8 bit programmable timer is turned off 4 Since the underf...

Page 292: ...III PERIPHERAL BLOCK 8 BIT PROGRAMMABLE TIMERS B III 3 18 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK ...

Page 293: ...t Comparison B interrupt Comparison match B Comparison match A Comparison A Comparison B Timer x Interrupt controller External clock EXCLx Figure 4 1 Structure of 16 Bit Programmable Timer In each timer a 16 bit up counter TCx as well as two 16 bit comparison data registers CRxA CRxB and their buffers CRBxA CRBxB are provided The 16 bit counter can be reset to 0 by software and counts up using the...

Page 294: ... register 0x402D8 P25 TM3 I O I O port 16 bit timer 3 output CFP25 D5 P2 function select register 0x402D8 P26 TM4 I O I O port 16 bit timer 4 output CFP26 D6 P2 function select register 0x402D8 P27 TM5 I O I O port 16 bit timer 5 output CFP27 D7 P2 function select register 0x402D8 I Input mode O Output mode Ex Extended function TMx output pin of the 16 bit programmable timer This pin outputs a clo...

Page 295: ... signal can be output from the chip to the outside The clock cycle is determined by comparison data B and the duty ratio is determined by comparison data A This output can be used to control external devices The output pins of each timer are described in the preceding section A D converter start trigger The A D converter allows a trigger to start the A D conversion to be selected from among four a...

Page 296: ...imer 4 control register 0x481A6 Timer 5 input clock selection CKSL5 D3 16 bit timer 5 control register 0x481AE An external clock is selected by writing 1 to CKSLx and the internal clock is selected by writing 0 At initial reset CKSLx is set for the internal clock An external clock can be used for the timer for which the pin is set for input Internal clock When the internal clock is selected as a t...

Page 297: ...llowing registers are used to set these values Timer 0 comparison data A CR0A 15 0 D F 0 16 bit timer 0 comparison data A set up register 0x48180 Timer 0 comparison data B CR0B 15 0 D F 0 16 bit timer 0 comparison data B set up register 0x48182 Timer 1 comparison data A CR1A 15 0 D F 0 16 bit timer 1 comparison data A set up register 0x48188 Timer 1 comparison data B CR1B 15 0 D F 0 16 bit timer 1...

Page 298: ...e timer has stopped counting the counter retains its count so that the timer can start counting again from that point If the count of the counter matches the set value of the comparison data register during count up the timer generates a comparison match interrupt When the counter matches comparison data B an interrupt is generated and the counter is reset At the same time the values set in the co...

Page 299: ...able clock to be supplied to external devices After a cold start the output pins are set for the I O ports and set in input mode The pins go into high impedance status When the pin function is switched to the timer output the pin goes low if OUTINVx is set to 0 or goes high if OUTINVx is set to 1 Starting clock output To output the TMx clock write 1 to the clock output control bit PTMx Clock outpu...

Page 300: ...r value Comparison match A signal Comparison match B signal TMx output when OUTINVx 0 TMx output when OUTINVx 1 0 1 2 3 4 5 0 1 2 3 4 5 0 1 Figure 4 4 Clock Output in Fine Mode As shown in the figure above in fine mode the output clock duty ratio can be adjusted in the half cycle of the input clock However when the CRxA value is 0 the timer outputs a pulse with a 1 cycle width as the input clock t...

Page 301: ...f the interrupt enable register bit corresponding to that interrupt factor flag has been set to 1 an interrupt request is generated An interrupt caused by a timer can be disabled by leaving the interrupt enable register bit for that timer set to 0 The interrupt factor flag is always set to 1 by the timer s comparison match state regardless of how the interrupt enable register is set even when set ...

Page 302: ...d trigger set up bit corresponding to each timer Table 4 6 HSDMA Trigger Set up Bits Interrupt factor HSDMA Ch Trigger set up bits Timer 0 comparison A 0 HSD0S 3 0 D 3 0 HSDMA Ch 0 1 trigger set up register 0x40298 0111 Timer 0 comparison B 0 HSD0S 3 0 D 3 0 HSDMA Ch 0 1 trigger set up register 0x40298 0110 Timer 1 comparison A 1 HSD1S 3 0 D 7 4 HSDMA Ch 0 1 trigger set up register 0x40298 0111 Ti...

Page 303: ...er 2 comparison A 0x0C0009C Timer 3 comparison B 0x0C000A8 Timer 3 comparison A 0x0C000AC Timer 4 comparison B 0x0C000B8 Timer 4 comparison A 0x0C000BC Timer 5 comparison B 0x0C000C8 Timer 5 comparison A 0x0C000CC The base address of the trap table can be changed using the TTBR register 0x48134 to 0x48137 Precaution Serial interface Ch 2 and Ch 3 share interrupt signals with the 16 bit timers A re...

Page 304: ...0 16 bit timer 3 comparison A 16 bit timer 3 comparison B reserved 16 bit timer 2 comparison A 16 bit timer 2 comparison B reserved 0 0 0 0 R W R W R W R W 0 when being read 0 when being read 0040273 B 1 Enabled 0 Disabled 16 bit timer 2 3 interrupt enable register 1 Enabled 0 Disabled E16TC5 E16TU5 E16TC4 E16TU4 D7 D6 D5 4 D3 D2 D1 0 16 bit timer 5 comparison A 16 bit timer 5 comparison B reserve...

Page 305: ...4 B 1 IDMA enabled 0 IDMA disabled Port input 0 3 high speed DMA Ch 0 1 16 bit timer 0 IDMA enable register DE16TC4 DE16TU4 DE16TC3 DE16TU3 DE16TC2 DE16TU2 DE16TC1 DE16TU1 D7 D6 D5 D4 D3 D2 D1 D0 16 bit timer 4 comparison A 16 bit timer 4 comparison B 16 bit timer 3 comparison A 16 bit timer 3 comparison B 16 bit timer 2 comparison A 16 bit timer 2 comparison B 16 bit timer 1 comparison A 16 bit t...

Page 306: ...A12 CR0A11 CR0A10 CR0A9 CR0A8 CR0A7 CR0A6 CR0A5 CR0A4 CR0A3 CR0A2 CR0A1 CR0A0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 bit timer 0 comparison data A CR0A15 MSB CR0A0 LSB X X X X X X X X X X X X X X X X R W 0048180 HW 16 bit timer 0 comparison data A set up register 0 to 65535 CR0B15 CR0B14 CR0B13 CR0B12 CR0B11 CR0B10 CR0B9 CR0B8 CR0B7 CR0B6 CR0B5 CR0B4 CR0B3 CR0B2 CR0B1 CR0B0 DF DE DD DC...

Page 307: ...C13 TC12 TC11 TC10 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 bit timer 1 counter data TC115 MSB TC10 LSB X X X X X X X X X X X X X X X X R 004818C HW 16 bit timer 1 counter data register SELFM1 SELCRB1 OUTINV1 CKSL1 PTM1 PRESET1 PRUN1 D7 D6 D5 D4 D3 D2 D1 D0 reserved 16 bit timer 1 fine mode selection 16 bit timer 1 comparison buffer 16 bit timer 1 output inversion 16 bit timer 1 input cl...

Page 308: ... timer 2 comparison buffer 16 bit timer 2 output inversion 16 bit timer 2 input clock selection 16 bit timer 2 clock output control 16 bit timer 2 reset 16 bit timer 2 Run Stop control 0 0 0 0 0 0 0 0 R W R W R W R W R W W R W 0 when being read 0 when being read 0048196 B 1 Enabled 0 Disabled 1 Fine mode 0 Normal 1 Invert 0 Normal 1 External clock 0 Internal clock 1 On 0 Off 1 Reset 0 Invalid 1 Ru...

Page 309: ...Disabled 1 Fine mode 0 Normal 1 Invert 0 Normal 1 External clock 0 Internal clock 1 On 0 Off 1 Reset 0 Invalid 1 Run 0 Stop 16 bit timer 3 control register 0 to 65535 CR4A15 CR4A14 CR4A13 CR4A12 CR4A11 CR4A10 CR4A9 CR4A8 CR4A7 CR4A6 CR4A5 CR4A4 CR4A3 CR4A2 CR4A1 CR4A0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 bit timer 4 comparison data A CR4A15 MSB CR4A0 LSB X X X X X X X X X X X X X X X...

Page 310: ...imer 5 comparison data A set up register 0 to 65535 CR5B15 CR5B14 CR5B13 CR5B12 CR5B11 CR5B10 CR5B9 CR5B8 CR5B7 CR5B6 CR5B5 CR5B4 CR5B3 CR5B2 CR5B1 CR5B0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 bit timer 5 comparison data B CR5B15 MSB CR5B0 LSB X X X X X X X X X X X X X X X X R W 00481AA HW 16 bit timer 5 comparison data B set up register 0 to 65535 TC515 TC514 TC513 TC512 TC511 TC510 T...

Page 311: ...nded function D0 Port function extension register 0x402DF Sets whether the function of an I O port pin is to be extended Write 1 Function extended pin Write 0 I O port peripheral circuit pin Read Valid When CFEX 1 0 is set to 1 the P14 P10 ports function as debug signal output ports When CFEX 1 0 0 the CFP1 4 0 bit becomes effective so the settings of these bits determine whether the P14 P10 ports...

Page 312: ... register 0x4819E SELCRB4 Timer 4 comparison register buffer enable D5 16 bit timer 4 control register 0x481A6 SELCRB5 Timer 5 comparison register buffer enable D5 16 bit timer 5 control register 0x481AE Enables or disables writing to the comparison register buffer Write 1 Enabled Write 0 Disabled Read Valid When SELCRBx is set to 1 comparison data is read and written from to the comparison regist...

Page 313: ...ontrol register 0x4818E PTM2 Timer 2 clock output control D2 16 bit timer 2 control register 0x48196 PTM3 Timer 3 clock output control D2 16 bit timer 3 control register 0x4819E PTM4 Timer 4 clock output control D2 16 bit timer 4 control register 0x481A6 PTM5 Timer 5 clock output control D2 16 bit timer 5 control register 0x481AE Controls the output of the TMx signal timer output clock Write 1 On ...

Page 314: ... 0 comparison data is directly read or writing from to the comparison data register A When SELCRBx is set to 1 comparison data is read or written from to the comparison register buffer A The content of the buffer is loaded to the comparison data register A when the counter is reset The data set in this register is compared with each corresponding counter data When the contents match a comparison A...

Page 315: ...mer 1 interrupt enable D6 D7 16 bit timer 0 1 interrupt enable register 0x40272 E16TU2 E16TC2 Timer 2 interrupt enable D2 D3 16 bit timer 2 3 interrupt enable register 0x40273 E16TU3 E16TC3 Timer 3 interrupt enable D6 D7 16 bit timer 2 3 interrupt enable register 0x40273 E16TU4 E16TC4 Timer 4 interrupt enable D2 D3 16 bit timer 4 5 interrupt enable register 0x40274 E16TU5 E16TC5 Timer 5 interrupt ...

Page 316: ...only by writing to it in the software Note that if the PSR is set again to accept interrupts generated or if the reti instruction is executed without resetting the interrupt factor flag the same interrupt occurs again Note also that the value to be written to reset the flag is 1 when the reset only method RSTONLY 1 is used and 0 when the read write method RSTONLY 0 is used At initial reset all the...

Page 317: ...e output signal Therefore do not set the comparison registers as A B There is no problem when the interrupt function only is used 4 When using the output clock set the comparison data registers as A 0 and B 1 The minimum settings are A 0 and B 1 In this case the timer output clock cycle is the input clock 1 2 5 When the comparison data registers are set as A B in normal mode no comparison A interr...

Page 318: ...III PERIPHERAL BLOCK 16 BIT PROGRAMMABLE TIMERS B III 4 26 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK ...

Page 319: ...ock control register 0x40147 and the comparison data B set in CR0B 15 0 D F 0 16 bit timer 0 comparison register B 0x48182 The NMI generating interval is calculated using the following equation NMI generating interval CR0B 1 sec fPSCIN pdr fPSCIN Prescaler input clock frequency Hz pdr Prescaler s division ratio set by the P16TS0 register 1 4096 1 1024 1 256 1 64 1 16 1 4 1 2 1 1 CR0B Set value of ...

Page 320: ...ble base address can be changed using the TTBR registers 0x48134 to 0x48137 Operation in Standby Modes During HALT mode In HALT mode basic mode or HALT2 mode the prescaler and watchdog timer are operating Consequently if HALT mode continues beyond the NMI generation interval HALT mode is cleared by the NMI To disable the watchdog timer in HALT mode set EWD to 0 before executing the halt instructio...

Page 321: ...D 1 EWD becomes write protected again At initial reset WRWD is set to 0 write protected EWD NMI enable D1 Watchdog timer enable register 0x40171 Controls the generation of a nonmaskable interrupt NMI by the watchdog timer Write 1 NMI is enabled Write 0 NMI is disabled Read Valid The watchdog timer s interrupt signal is masked by writing 0 to EWD so a nonmaskable interrupt NMI to the CPU is not gen...

Page 322: ...III PERIPHERAL BLOCK WATCHDOG TIMER B III 5 4 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK ...

Page 323: ...ration of Clock System The CPU operating clock can be switched to the output OSC1 clock of the low speed OSC1 oscillation circuit in a program Furthermore the oscillation circuit can be stopped in a program If the OSC3 clock is unnecessary such as when performing clock processing only set the OSC1 clock for operation of the CPU peripheral circuits and turn off the high speed OSC3 oscillation circu...

Page 324: ...t Figure 6 2 Low Speed OSC1 Oscillation Circuit When using a crystal oscillation for this circuit connect a crystal resonator X tal1 32 768 kHz Typ and feedback resistor Rf between the OSC1 and OSC2 pins and two capacitors CG1 CD1 between the OSC1 pin and VSS and the OSC2 pin and VSS respectively When an external clock source is used leave the OSC2 pin open and input a square wave clock to the OSC...

Page 325: ... can be switched to the OSC1 clock thereby reducing current consumption Use CLKCHG D2 Power control register 0x40180 to switch over the operating clock Procedure for switching over from the OSC3 clock to the OSC1 clock 1 Turn on the low speed OSC1 oscillation circuit by writing 1 to SOSC1 2 Wait until the OSC1 oscillation stabilizes three seconds or more 3 Change the CPU operating clock by writing...

Page 326: ...lation circuit before entering or after exiting HALT mode The low speed OSC1 oscillation circuit does not stop operating in SLEEP mode set by executing the slp sleep instruction Therefore if the CPU was operating using the OSC1 clock before SLEEP mode was entered the CPU keeps operating using the OSC1 clock in SLEEP mode OSC1 Clock Output to External Devices The low speed OSC1 oscillation clock ca...

Page 327: ... clock option register 0x40190 Writing another value set the write protection CLGP7 CLGP6 CLGP5 CLGP4 CLGP3 CLGP2 CLGP1 CLGP0 D7 D6 D5 D4 D3 D2 D1 D0 Power control register protect flag 0 0 0 0 0 0 0 0 R W 004019E B Power control protect register CFP16 CFP15 CFP14 CFP13 CFP12 CFP11 CFP10 D7 D6 D5 D4 D3 D2 D1 D0 reserved P16 function selection P15 function selection P14 function selection P13 funct...

Page 328: ...r 0x40180 Selects the CPU operating clock Write 1 OSC3 clock Write 0 OSC1 clock Read Valid The OSC3 clock is selected as the CPU operating clock by writing 1 to CLKCHG and OSC1 is selected by writing 0 The operating clock can be switched over in this way only when both the high speed OSC3 and low speed OSC1 oscillation circuits are on In addition writing to CLKCHG is effective only when CLGP 7 0 i...

Page 329: ...ck is stopped BCU stop status Clocks for the peripheral circuits are stopped The high speed oscillation circuit is stopped The low speed oscillation circuit maintains the status before entering SLEEP mode Reset NMI Enabled not masked input port interrupt factors Clock timer interrupt when the low speed oscillation circuit is being operated PF1ON OSC1 external output control D0 Clock option registe...

Page 330: ...tains its state from prior to the initial reset Programming Notes 1 Immediately after the low speed OSC1 oscillation circuit is turned on a certain period of time is required for oscillation to stabilize 3 sec max To prevent the device from operating erratically do not use the clock until its oscillation has stabilized 2 The oscillation circuit used for the CPU operating clock cannot be turned off...

Page 331: ...l peripheral circuits are placed in standby mode HALT or SLEEP Normally this clock timer should be used for a clock and various other clocking functions Figure 7 1 shows the structure of the clock timer Note Since the clock timer is driven by a clock originating from the low speed OSC1 oscillation circuit this timer cannot be used unless the low speed OSC1 oscillation circuit 32 768 kHz Typ is use...

Page 332: ...eset bit TCRST and the clock timer RUN STOP control bit TCRUN are located at the same address 0x40151 However the clock timer cannot be reset at the same time it is set to RUN by writing 1 to both In this case the reset input is ignored and the timer starts counting up from the counter values then in effect Always make sure TCRUN 0 before resetting the timer When the counters are cleared as the cl...

Page 333: ... Hz 2 Hz 1 Hz 1 second 1 minute 1 hour 1 day If 0 is written to TCRUN the clock timer is stopped at a rising edge of the low speed OSC1 oscillation clock to prevent device malfunction caused by the concurrent termination of counting falling edge of the 256 Hz clock Even when the clock timer is stopped each counter retains the data set at that point When the timer is made to RUN again while in that...

Page 334: ...minutes or 23 hours the data is not considered invalid The values set in these registers are compared with those of each counter and when they match the alarm factor generation flag TCAF D0 Clock timer interrupt control register 0x40152 is set to 1 If clock timer interrupts have been enabled using the interrupt controller an interrupt is generated when the flag is set The day comparison data regis...

Page 335: ...er A D interrupt factor flag register 0x40287 Interrupt enable ECTM D1 Port input 4 7 clock timer A D interrupt enable register 0x40277 Interrupt level PCTM 2 0 D 2 0 Clock timer interrupt priority register 0x4026B When an interrupt factor occurs the clock timer sets the interrupt actor flag to 1 as described above At this time if the interrupt enable register bit is set to 1 an interrupt request ...

Page 336: ...e is reset before a three day period has elapsed the device operates as follows The CPU starts up using the OSC3 clock The clock timer counters are not reset They remain in the RUN state The time during which the CPU has been idle can be checked by reading out the clock timer counters For using the clock timer as RTC Example in which the clock timer is kept operating and an alarm is generated at 1...

Page 337: ...4 Hz Clock timer data 8 Hz Clock timer data 16 Hz Clock timer data 32 Hz Clock timer data 64 Hz Clock timer data 128 Hz X X X X X X X X R R R R R R R R 0040153 B 1 High 0 Low 1 High 0 Low 1 High 0 Low 1 High 0 Low 1 High 0 Low 1 High 0 Low 1 High 0 Low 1 High 0 Low Clock timer divider register TCMD5 TCMD4 TCMD3 TCMD2 TCMD1 TCMD0 D7 6 D5 D4 D3 D2 D1 D0 reserved Clock timer second counter data TCMD5...

Page 338: ...d Port input 4 7 clock timer A D interrupt enable register FP7 FP6 FP5 FP4 FCTM FADE D7 6 D5 D4 D3 D2 D1 D0 reserved Port input 7 Port input 6 Port input 5 Port input 4 Clock timer A D converter X X X X X X R W R W R W R W R W R W 0 when being read 0040287 B 1 Factor is generated 0 No factor is generated Port input 4 7 clock timer A D interrupt factor flag register TCRST Clock timer reset D1 Clock...

Page 339: ... high order bits at each address of the second minute and hour counter data are always 0 when read out The counter data is not initialized at initial reset TCCH5 TCCH0 Minute comparison data D 5 0 Clock timer minute comparison register 0x40159 TCCD4 TCCD0 Hour comparison data D 4 0 Clock timer hour comparison register 0x4015A TCCN4 TCCN0 Day comparison data D 4 0 Clock timer day comparison registe...

Page 340: ...urred Read 0 No interrupt factor has occurred Write 1 Flag is reset Write 0 Invalid TCIF is set to 1 when an interrupt factor selected using TCISE occurs Since there is only one source for the clock timer interrupt use this flag to differentiate it from interrupts caused by an alarm Once set to 1 TCIF remains set until it is reset by writing 1 TCIF is not initialized at initial reset This bit does...

Page 341: ...to the CPU is generated 1 The corresponding interrupt enable register bit is set to 1 2 No other interrupt request of a higher interrupt priority is generated 3 The IE bit of the PSR is set to 1 interrupt enabled 4 The corresponding interrupt priority register is set to a value higher than the CPU interrupt level IL The interrupt factor flag is always set to 1 when an interrupt factor occurs no ma...

Page 342: ...tarts counting up from the counter values then in effect When resetting the timer always make sure TCRUN 0 timer stopped 4 When the counters are cleared as the clock timer is reset an interrupt may be generated depending on the register settings Therefore before resetting the clock timer first disable the clock timer interrupt and after resetting the clock timer reset the interrupt factor flag and...

Page 343: ...synchronous mode only The receive and transmit units are constructed with a double buffer structure allowing for successive receive and transmit operations Data transfers using IDMA or HSDMA are possible Three types of interrupts transmit data empty receive data full and receive error can be generated Figure 8 1 shows the configuration of the serial interface one channel Control registers Transmit...

Page 344: ...elect register 0x402D8 SSRDY2 D3 Function select register 0x402DB P33 DMAACK1 SIN3 I O I O port Serial IF Ch 3 data input CFP33 D3 Function select register 0x402DC SSIN3 D0 Function select register 0x402D7 P16 EXCL5 DMAAND1 SOUT3 I O I O port Serial IF Ch 3 data output CFP16 D6 Function select register 0x402D4 SSOUT3 D1 Function select register 0x402D7 P15 EXCL4 DMAAND0 SCLK3 I O I O port Serial I...

Page 345: ...SINx SOUTx SCLKx SRDYx 8 bit asynchronous Data input Data output Clock input P port P port 7 bit asynchronous Data input Data output Clock input P port P port Clock synchronized slave Data input Data output Clock input Ready output Clock synchronized master Data input Data output Clock output Ready input All four pins are used in the clock synchronized mode In the asynchronous mode since SRDYx is ...

Page 346: ...al serial input output device is ready to transmit or receive when ready in a low level Clock synchronized slave mode SMDx 1 0 01 In this mode clock synchronized 8 bit serial transfers in which the serial interface functions as a slave can be performed using the synchronizing clock that is supplied by an external master side serial input output device The synchronizing clock is input from the SCLK...

Page 347: ...is used to set the interface mode normal or IrDA interface Write 00 to IRMDx 1 0 to choose the ordinary interface Since IRMDx 1 0 becomes indeterminate at initial reset it must be initialized Setting the transfer mode Use SMDx to set the transfer mode of the serial interface as described earlier When using the serial interface as the master for clock synchronized transfer set SMDx 1 0 to 00 when u...

Page 348: ...details on how to control the prescaler and 8 bit programmable timers refer to Prescaler and 8 Bit Programmable Timers The serial interface control register contains an SSCKx bit to select the clock source used for the asynchronous mode Although this bit does not affect the clock in the clock synchronized mode its content becomes indeterminate at initial reset Therefore be sure to initialize this ...

Page 349: ...it data buffer which are provided independently of those used for a receive operation Ch 0 transmit data TXD0 7 0 D 7 0 Serial I F Ch 0 transmit data register 0x401E0 Ch 1 transmit data TXD1 7 0 D 7 0 Serial I F Ch 1 transmit data register 0x401E5 Ch 2 transmit data TXD2 7 0 D 7 0 Serial I F Ch 2 transmit data register 0x401F0 Ch 3 transmit data TXD3 7 0 D 7 0 Serial I F Ch 3 transmit data registe...

Page 350: ... is transferred to the shift register synchronously with the first falling edge of the clock At the same time the LSB of the data transferred to the shift register is output from the SOUTx pin 4 The data in the shift register is shifted 1 bit by the next falling edge of the clock and the bit following the LSB is output from SOUTx This operation is repeated until all 8 bits of data are transmitted ...

Page 351: ...6 Serial I F Ch 0 control register 0x401E3 Ch 1 receive enable RXEN1 D6 Serial I F Ch 1 control register 0x401E8 Ch 2 receive enable RXEN2 D6 Serial I F Ch 2 control register 0x401F3 Ch 3 receive enable RXEN3 D6 Serial I F Ch 3 control register 0x401F8 When receive operations are enabled by writing 1 to this bit clock input to the shift register is enabled ready for input thereby starting a data r...

Page 352: ...Mode 1 If the SRDYx signal from the slave is on a high level the master waits until it turns to a low level ready to receive 2 If SRDYx is on a low level synchronizing clock input to the serial interface begins The synchronizing clock is also output from the SCLKx pin to the slave device 3 The slave device outputs each bit of data synchronously with the falling edges of the clock The LSB is output...

Page 353: ...completed before the receive data register is read out the receive data register is overwritten with the new data Therefore the receive data register must always be read out before a receive operation for the next data is completed When the receive data register is overwritten an overrun error is generated and the overrun error flag is set to 1 Ch 0 overrun error flag OER0 D2 Serial I F Ch 0 statu...

Page 354: ...formed simultaneously is also possible Figure 8 8 shows an example of how input output pins are connected for transfers in the asynchronous mode Data input Data output External clock SINx SOUTx SCLKx SINx SOUTx External serial device 1 When external clock is used 2 When internal clock is used S1C33 Data input Data output External serial device S1C33 Figure 8 8 Example of Connection in Asynchronous...

Page 355: ...or 10 when using the serial interface as an IrDA interface This setting must be made before a transfer mode is set Setting the transfer mode Use SMDx to set the transfer mode of the serial interface as described earlier When using the serial interface in the 8 bit asynchronous mode set SMDx 1 0 to 11 when using the serial interface in the 7 bit asynchronous mode set SMDx 1 0 to 10 Setting the inpu...

Page 356: ...4 1 2048 1 4096 8 bit programmable timer 3 5 1 2 1 4 1 8 1 16 1 32 1 64 1 128 1 256 Table 8 4 shows examples of prescaler division ratios and the reload data settings of the programmable timer in cases in which the internal division ratio of the serial interface is set to 1 16 Table 8 4 Example of Transfer Rate Settings Transfer rate fPSCIN 20 MHz fPSCIN 25 MHz fPSCIN 33 MHz bps RLD pdr Error RLD ...

Page 357: ...Its duty ratio low high ratio is 6 10 or 2 6 when divided by 8 and not 50 Since the receive data is sampled in the middle point of each bit the sampling clock recognizes the start bit first and then changes the level from high to low at the second falling edge of TCLK And at the 8th 4th for 1 8 falling edge of TCLK it changes the level from low to high This change in levels is repeated for the fol...

Page 358: ...nsmit enable TXEN3 D7 Serial I F Ch 3 control register 0x401F8 When transmit is enabled by writing 1 to this bit the clock input to the shift register is enabled ready for input thus allowing data to be transmitted Transmit is disabled by writing 0 to TXENx Note Do not set TXENx to 0 during a transmit operation 2 Transmit procedure The serial interface has a transmit shift register and a transmit ...

Page 359: ...falling edge of the sampling clock At the same time the SOUTx pin is setting to a low level to send the start bit 2 Each bit of data in the shift register is transmitted beginning with the LSB at each falling edge of the subsequent sampling clock This operation is repeated until all 8 or 7 bits of data are transmitted 3 After sending the MSB the parity bit if EPRx 1 and the stop bit are transmitte...

Page 360: ...ll RDBF0 D0 Serial I F Ch 0 status register 0x401E2 Ch 1 receive data buffer full RDBF1 D0 Serial I F Ch 1 status register 0x401E7 Ch 2 receive data buffer full RDBF2 D0 Serial I F Ch 2 status register 0x401F2 Ch 3 receive data buffer full RDBF3 D0 Serial I F Ch 3 status register 0x401F7 This bit is set to 1 buffer full when data is transferred from the shift register to the receive data register ...

Page 361: ...en the data received in the shift register is transferred to the receive data register in order to check conformity with PMDx settings odd or even parity If any nonconformity is found in this check a parity error is assumed and the parity error flag is set to 1 Ch 0 parity error flag PER0 D3 Serial I F Ch 0 status register 0x401E2 Ch 1 parity error flag PER1 D3 Serial I F Ch 1 status register 0x40...

Page 362: ...or is generated and the overrun error flag is set to 1 Ch 0 overrun error flag OER0 D2 Serial I F Ch 0 status register 0x401E2 Ch 1 overrun error flag OER1 D2 Serial I F Ch 1 status register 0x401E7 Ch 2 overrun error flag OER2 D2 Serial I F Ch 2 status register 0x401F2 Ch 3 overrun error flag OER3 D2 Serial I F Ch 3 status register 0x401F7 Even when this error occurs the received data in error is...

Page 363: ...refer to Asynchronous Interface for details on how to set and control the data formats and data transfers Setting IrDA Interface When performing infrared ray communication the following settings must be made before communication can be started 1 Setting input output pins 2 Selecting the interface mode IrDA interface function 3 Setting the transfer mode 4 Setting the input clock 5 Setting the data ...

Page 364: ...he circuit connected externally to the chip The logic of the internal serial interface is active low If the input output signals are active high the logic of these signals must be inverted before they can be used The input SINx and output SOUTx logic can be set individually through the use of the IRRLx and IRTLx bits respectively Table 8 8 IrDA Input Output Logic Inversion Bits Ch 0 Serial I F Ch ...

Page 365: ...of the serial interface output signal is set to 3 16 before the signal is output from the SOUTx pin TCLK PPM modulator input I F output PPM modulator output SOUTx 1 2 3 8 9 10 11 16 3 TCLK 16 TCLK Figure 8 16 Data Modulation by PPM Circuit When receiving During data reception the pulse width of the input signal from SINx is set to 16 3 before the signal is transferred to the serial interface TCLK ...

Page 366: ...ter are met an interrupt to the CPU is generated Since all three types of errors generate the same interrupt factor check the error flags PERx parity error OERx overrun error and FERx framing error to identify the type of error that has occurred In the clock synchronized mode parity and framing errors do not occur Note If a receive error parity or framing error occurs the receive error interrupt a...

Page 367: ...IO Ch 2 RXD Err FPT0 Timer 3 compare B Switching between the above interrupt factors is performed by means of the interrupt factor FP function switching register 0x402C5 and the interrupt factor TM16 function switching register 0x402CB For the setting of the interrupt controller in the CPU core the setting for the selected interrupt factor is used Refer to ITC Interrupt Controller in the Core Bloc...

Page 368: ...5 compare A 18 SIO Ch 2 RXD Full FPT1 2 Timer 5 compare B 17 SIO Ch 2 RXD Err FPT0 1 Timer 3 compare B 13 For example when port input interrupts are selected Serial I F Ch 2 transmit buffer empty corresponds to port 3 and to IDMA Ch 4 Therefore IDMA can be invoked by setting both IDMA request bit RP3 D3 0x40290 and IDMA enable bit DEP3 D3 0x40294 to 1 High speed DMA Ch 0 and Ch 1 The receive buffe...

Page 369: ...01 must be set when the Ch 1 trigger factor value D 7 4 0x40298 has been set to 1000 HSDMA can also be invoked by the reverse combination of set values Similarly to use 16 bit timer 4 compare A and B on Serial I F Ch 3 HSDMA can be invoked by setting an HSDMA Ch 2 value of 1001 when the Ch 0 value has been set to 1000 HSDMA can also be invoked by the reverse combination of set values With interrup...

Page 370: ... full 1 Buffer full 0 Empty Serial I F Ch 0 status register TXEN0 RXEN0 EPR0 PMD0 STPB0 SSCK0 SMD01 SMD00 D7 D6 D5 D4 D3 D2 D1 D0 Ch 0 transmit enable Ch 0 receive enable Ch 0 parity enable Ch 0 parity mode selection Ch 0 stop bit selection Ch 0 input clock selection Ch 0 transfer mode selection 1 1 0 0 1 0 1 0 SMD0 1 0 Transfer mode 8 bit asynchronous 7 bit asynchronous Clock sync Slave Clock syn...

Page 371: ...24 TXD23 TXD22 TXD21 TXD20 D7 D6 D5 D4 D3 D2 D1 D0 Serial I F Ch 2 transmit data TXD27 26 MSB TXD20 LSB X X X X X X X X R W 00401F0 B Serial I F Ch 2 transmit data register 0x0 to 0xFF 0x7F RXD27 RXD26 RXD25 RXD24 RXD23 RXD22 RXD21 RXD20 D7 D6 D5 D4 D3 D2 D1 D0 Serial I F Ch 2 receive data RXD27 26 MSB RXD20 LSB X X X X X X X X R 00401F1 B Serial I F Ch 2 receive data register TEND2 FER2 PER2 OER2...

Page 372: ... 0 0 X X X X X X R W R W R W R W R W R W R W Valid only in asynchronous mode 00401F8 B Serial I F Ch 3 control register 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 SCLK3 0 Internal clock DIVMD3 IRTL3 IRRL3 IRMD31 IRMD30 D7 5 D4 D3 D2 D1 D0 reserved Ch 3 async clock division ratio Ch 3 IrDA I F output logic inversion Ch 3 IrDA I F input logic ...

Page 373: ...mer 5 comparison B 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W 0040296 B 1 IDMA enabled 0 IDMA disabled 16 bit timer 5 8 bit timer serial I F Ch 0 IDMA enable register DEP7 DEP6 DEP5 DEP4 DEADE DESTX1 DESRX1 D7 D6 D5 D4 D3 D2 D1 D0 Port input 7 Port input 6 Port input 5 Port input 4 reserved A D converter SIF Ch 1 transmit buffer empty SIF Ch 1 receive buffer full 0 0 0 0 0 0 0 R W R W R W R W...

Page 374: ...D5 D4 D3 D2 D1 D0 P07 port extended function P06 port extended function P05 port extended function P04 port extended function P31 port extended function P21 port extended function P10 P11 P13 port extended function P12 P14 port extended function 0 0 0 0 0 0 1 1 R W R W R W R W R W R W R W R W 00402DF B Port function extension register 1 DMAEND3 0 P07 etc 1 DMAACK3 0 P06 etc 1 DMAEND2 0 P05 etc 1 D...

Page 375: ...s set to 0 SSRDY3 Serial I F Ch 3 SRDY selection D3 Port SIO function extension register 0x402D7 Switches the function of pin P32 DMAACK0 SRDY3 Write 1 SRDY3 Write 0 P32 DMAACK0 Read Valid To use the pin as SRDY3 set SSRDY3 D3 0x402D7 to 1 and CFP32 D2 0x402DC to 0 To use the pin as P32 or DMAACK0 set this bit to 0 At power on this bit is set to 0 SSIN2 Serial I F Ch 2 SIN selection D0 Port SIO fu...

Page 376: ...whether the P07 P04 ports function as I O port s or serial interface Ch 1 signal output ports At cold start CFEX 7 4 is set to 0 I O port serial I O pin At hot start CFEX 7 4 retains its state from prior to the initial reset TXD07 TXD00 Ch 0 transmit data D 7 0 Serial I F Ch 0 transmit data register 0x401E0 TXD17 TXD10 Ch 1 transmit data D 7 0 Serial I F Ch 1 transmit data register 0x401E5 TXD27 T...

Page 377: ...smit completion flag D5 Serial I F Ch 0 status register 0x401E2 TEND1 Ch 1 transmit completion flag D5 Serial I F Ch 1 status register 0x401E7 TEND2 Ch 2 transmit completion flag D5 Serial I F Ch 2 status register 0x401F2 TEND3 Ch 3 transmit completion flag D5 Serial I F Ch 3 status register 0x401F7 Indicates the transmission status Read 1 During transmitting Read 0 End of transmission Write Inval...

Page 378: ...1F2 OER3 Ch 3 overrun error flag D2 Serial I F Ch 3 status register 0x401F7 Indicates whether an overrun error occurred Read 1 An error occurred Read 0 No error occurred Write 1 Invalid Write 0 Reset to 0 The OERx flag is an error flag indicating whether an overrun error occurred When an error has occurred it is set to 1 An overrun error occurs when the next receive operation is completed before t...

Page 379: ...al I F Ch 2 control register 0x401F3 TXEN3 Ch 3 transmit enable D7 Serial I F Ch 3 control register 0x401F8 Enables each channel for transmit operations Write 1 Transmit enabled Write 0 Transmit disabled Read Valid When TXENx for a channel is set to 1 the channel is enabled for transmit operations When TXENx is set to 0 the channel is disabled for transmit operations Always make sure the TXENx 0 b...

Page 380: ...ister 0x401E8 PMD2 Ch 2 parity mode selection D4 Serial I F Ch 2 control register 0x401F3 PMD3 Ch 3 parity mode selection D4 Serial I F Ch 3 control register 0x401F8 Selects an odd or even parity Write 1 Odd parity Write 0 Even parity Read Valid Odd parity is selected by writing 1 to PMDx and even parity is selected by writing 0 Parity check and the addition of a parity bit are only effective in a...

Page 381: ...r 0x401F3 SMD31 SMD30 Ch 3 transfer mode selection D 1 0 Serial I F Ch 3 control register 0x401F8 Sets the transfer mode of the serial interface as shown in Table 8 15 below Table 8 15 Setting of Transfer Mode SMDx1 SMDx0 Transfer mode 1 1 8 bit asynchronous mode 1 0 7 bit asynchronous mode 0 1 Clock synchronized slave mode 0 0 Clock synchronized master mode The SMDx bit can be read as well as wri...

Page 382: ...c of the signal that is input from an external infrared ray communication circuit to the chip to suit the serial interface If IRRLx is set to 1 a high pulse is input as a logic 0 If IRRLx is set to 0 a low pulse is input as a logic 0 At initial reset IRRLx becomes indeterminate IRMD01 IRMD00 Ch 0 IrDA interface mode selection D 1 0 Serial I F Ch 0 IrDA register 0x401E4 IRMD11 IRMD10 Ch 1 IrDA inte...

Page 383: ...ter to the receive data register A receive error interrupt factor occurs when a parity framing or overrun error is detected during reception of data At this time if the following conditions are met an interrupt to the CPU is generated 1 The corresponding interrupt enable register bit is set to 1 2 No other interrupt request of a higher priority has been generated 3 The PSR s IE bit is set to 1 int...

Page 384: ... these bits are set to 0 interrupt request DESRX0 DESTX0 Ch 0 IDMA enable D6 D7 16 bit timer 5 8 bit timer serial I F Ch 0 IDMA enable register 0x40296 DESRX1 DESTX1 Ch 1 IDMA enable D0 D1 Serial I F Ch 1 A D IDMA enable register 0x40297 Enables IDMA transfer by means of an interrupt factor When using the set only method default Write 1 IDMA enabled Write 0 Not changed Read Valid When using the re...

Page 385: ...pty FP3 interrupt factor switching D3 Interrupt factor FP function switching register 0x402C5 Switches the interrupt factor Write 1 SIO Ch 2 transmit buffer empty Write 0 FP3 input Read Valid Set to 1 to use the SIO Ch 2 transmit buffer empty interrupt Set to 0 to use the FP3 input interrupt At power on this bit is set to 0 SIO3RS0 SIO Ch 3 receive buffer full FP4 interrupt factor switching D4 Int...

Page 386: ...r TM16 function switching register 0x402CB Switches the interrupt factor Write 1 SIO Ch 2 receive buffer full Write 0 TM16 Ch 5 compare B Read Valid Set to 1 to use the SIO Ch 2 receive buffer full interrupt Set to 0 to use the TM16 Ch 5 compare B interrupt At power on this bit is set to 0 SIO2TS1 SIO Ch 2 transmit buffer empty TM16 Ch 5 compare A interrupt factor switching D1 Interrupt factor TM1...

Page 387: ...TM16 Ch 3 compare A interrupt factor switching D5 Interrupt factor TM16 function switching register 0x402CB Switches the interrupt factor Write 1 SIO Ch 3 receive error Write 0 TM16 Ch 3 compare A Read Valid Set to 1 to use the SIO Ch 3 receive error interrupt Set to 0 to use the TM16 Ch 3 compare A interrupt At power on this bit is set to 0 T8CH4S1 8 bit timer 4 underflow TM16 Ch 2 compare B inte...

Page 388: ...rrence of an interrupt always be sure to reset the interrupt factor flag before setting the PSR again or executing the reti instruction 7 Follow the procedure described below to initialize the serial interface Set IRMDx 1 0 Set SMDx 1 0 Other settings Enable transmitting receiving 00 normal I F or 10 IrDA I F Transfer mode setting Data format and clock selection Internal division ratio IrDA I O lo...

Page 389: ...cture of Input Port Each input port pin is connected directly to the internal data bus via a three state buffer The state of the input signal when read at an input port is directly taken into the internal circuit as data When K50 is used as an input port and K60 to K67 are used as general purpose input ports the power supply for the port input buffers is AVDDE Therefore when these ports are used a...

Page 390: ...2C3 K64 AD4 I Input port AD converter input 4 CFK64 D4 K6 function select register 0x402C3 K65 AD5 I Input port AD converter input 5 CFK65 D5 K6 function select register 0x402C3 K66 AD6 I Input port AD converter input 6 CFK66 D6 K6 function select register 0x402C3 K67 AD7 I Input port AD converter input 7 CFK67 D7 K6 function select register 0x402C3 At cold start all pins are set for input ports K...

Page 391: ...select register K67D K66D K65D K64D K63D K62D K61D K60D D7 D6 D5 D4 D3 D2 D1 D0 K67 input port data K66 input port data K65 input port data K64 input port data K63 input port data K62 input port data K61 input port data K60 input port data R R R R R R R R 00402C4 B 1 High 0 Low K6 input port data register CFK54 CFK50 K5 4 0 function selection D 4 0 K5 function select register 0x402C0 CFK67 CFK60 K...

Page 392: ... CFEX5 D5 Port function extension register 0x402DF P06 SCLK1 DMAACK3 I O I O port Serial IF Ch 1 clock input output DMAACK3 output Ex CFP06 D6 P0 function select register 0x402D0 CFEX6 D6 Port function extension register 0x402DF P07 SRDY1 DMAEND3 I O I O port Serial IF Ch 1 ready input output DMAEND3 output Ex CFP07 D7 P0 function select register 0x402D0 CFEX7 D7 Port function extension register 0...

Page 393: ... this case refer to the description of each peripheral circuit in this manual At hot start the pins retain their state from prior to the reset In addition to being an I O port the P10 P13 P15 P16 P30 and P34 pins are shared with two types three types for P10 P13 of peripheral circuits The type of peripheral circuit for which these pins are used is determined by the direction input or output in whi...

Page 394: ...trol 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W This register indicates the values of the I O control signals of the ports when it is read See detailed explanation 00402D2 B 1 Output 0 Input P0 I O control register CFP16 CFP15 CFP14 CFP13 CFP12 CFP11 CFP10 D7 D6 D5 D4 D3 D2 D1 D0 reserved P16 function selection P15 function selection P14 function selection P13 function selection P12 function ...

Page 395: ... I O control P20 I O control 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W This register indicates the values of the I O control signals of the ports when it is read See detailed explanation 00402DA B 1 Output 0 Input P2 I O control register SSRDY2 SSCLK2 SSOUT2 SSIN2 D7 4 D3 D2 D1 D0 reserved Serial I F Ch 2 SRDY selection Serial I F Ch 2 SCLK selection Serial I F Ch 2 SOUT selection Serial I F...

Page 396: ...t to 1 the corresponding pin is set for use with peripheral circuits see Table 9 3 The pins for which register bits are set to 0 can be used as general purpose I O ports At cold start CFP is set to 0 I O port At hot start CFP retains its state from prior to the initial reset P07D P00D P0 7 0 I O port data D 7 0 P0 I O port data register 0x402D1 P16D P10D P1 6 0 I O port data D 6 0 P1 I O port data...

Page 397: ...using the CFEX and CFP registers the value written to the IOC register is read out as is When peripheral function is selected the read value depends on the peripheral circuit status and may not indicate the value written to the IOC register However the read values of the IOC bits for P10 P13 P15 P16 P30 and P34 are the same as the written value even if the peripheral function is selected SSIN3 Ser...

Page 398: ...h 2 SOUT selection D1 Port SIO function extension register 0x402DB Switches the function of pin P26 TM4 SOUT2 Write 1 SOUT2 Write 0 P26 TM4 Read Valid To use the pin as SOUT2 set SSOUT2 D1 0x402DB to 1 and CFP26 D6 0x402D8 to 0 To use the pin as P26 or TM4 set this bit to 0 At power on this bit is set to 0 SSCLK2 Serial I F Ch 2 SCLK selection D2 Port SIO function extension register 0x402DB Switch...

Page 399: ...n extension D5 Port function extension register 0x402DF CFEX6 P06 function extension D6 Port function extension register 0x402DF CFEX7 P07 function extension D7 Port function extension register 0x402DF Sets whether the function of an I O port pin is to be extended Write 1 Function extended pin Write 0 I O port peripheral circuit pin Read Valid When CFEXx is set to 1 the corresponding pin is set to...

Page 400: ...9 3 Configuration of Port Input Interrupt Circuit Selecting input pins The interrupt factors allows selection of an input pin from the four predefined pins independently Table 9 5 shows the control bits and the selectable pins for each factor Table 9 5 Selecting Pins for Port Input Interrupts Interrupt SPT settings factor Control bit 11 10 01 00 FPT7 SPT7 1 0 D 7 6 Port input interrupt select regi...

Page 401: ...et to 0 the FPTx interrupt will be generated by the input signal level Furthermore the signal polarity can be selected using the SPPTx bit of the input porarity select register 0x402C8 With these registers the port input interrupt condition is decided as shown in Table 9 6 Table 9 6 Port Input Interrupt Condition SEPTx SPPTx FPTx interrupt condition 1 1 Rising edge 1 0 Falling edge 0 1 High level ...

Page 402: ...nal data bus K54 K64 P04 P24 K53 K63 P03 P23 K52 K62 P02 P22 K50 K60 P00 P20 Input comparison register SCPK0 Input mask register SMPK0 Address Address K51 K61 P01 P21 K50 K60 P00 P20 Input port selection SPPK0 FPK0 Interrupt request Interrupt signal generation FPK0 system K63 K67 P07 P27 K62 K66 P06 P26 K60 K64 P04 P24 Input comparison register SCPK1 Input mask register SMPK1 Address Address K61 K...

Page 403: ...gister SCPK is used to select whether an interrupt for each input port is to be generated at the rising or falling edge of the input A change in state occurs so that the input pin enabled for interrupt by the interrupt mask register SMPK and the content of the input comparison register SCPK become unmatched after being matched the interrupt factor flag FK is set to 1 and if other interrupt conditi...

Page 404: ...FPT1 FP1 D1 0x40280 EP1 D1 0x40270 PP1L 2 0 D 6 4 0x40260 FPT0 FP0 D0 0x40280 EP0 D0 0x40270 PP0L 2 0 D 2 0 0x40260 FPK1 FK1 D5 0x40280 EK1 D5 0x40270 PK1L 2 0 D 6 4 0x40262 FPK0 FK0 D4 0x40280 EK0 D4 0x40270 PK0L 2 0 D 2 0 0x40262 When the interrupt generation condition described above is met the corresponding interrupt factor flag is set to 1 If the interrupt enable register bit for that interru...

Page 405: ...rated at that point An interrupt request is generated after the DMA transfer is completed The registers can also be set so as not to generate an interrupt with only DMA transfers performed For details on IDMA transfers and interrupt control upon completion of IDMA transfer refer to IDMA Intelligent DMA Trap vectors The trap vector address of each input default interrupt factor is set as follows FP...

Page 406: ...P4L0 D7 D6 D5 D4 D3 D2 D1 D0 reserved Port input 5 interrupt level reserved Port input 4 interrupt level X X X X X X R W R W 0 when being read 0 when being read 004026C B Port input 4 5 interrupt priority register 0 to 7 0 to 7 PP7L2 PP7L1 PP7L0 PP6L2 PP6L1 PP6L0 D7 D6 D5 D4 D3 D2 D1 D0 reserved Port input 7 interrupt level reserved Port input 6 interrupt level X X X X X X R W R W 0 when being rea...

Page 407: ...onverter SIF Ch 1 transmit buffer empty SIF Ch 1 receive buffer full 0 0 0 0 0 0 0 R W R W R W R W R W R W R W 0 when being read 0040297 B 1 IDMA enabled 0 IDMA disabled 1 IDMA enabled 0 IDMA disabled Serial I F Ch 1 A D port input 4 7 IDMA enable register SPT31 SPT30 SPT21 SPT20 SPT11 SPT10 SPT01 SPT00 D7 D6 D5 D4 D3 D2 D1 D0 FPT3 interrupt input port selection FPT2 interrupt input port selection...

Page 408: ...ister SMPK13 SMPK12 SMPK11 SMPK10 D7 4 D3 D2 D1 D0 reserved FPK13 input mask FPK12 input mask FPK11 input mask FPK10 input mask 0 0 0 0 R W R W R W R W 0 when being read 00402CF B 1 Interrupt enabled 0 Interrupt disabled Key input interrupt FPK1 input mask register SPT71 SPT70 FPT7 interrupt input port selection D 7 6 Port input interrupt select register 2 0x402C7 SPT61 SPT60 FPT6 interrupt input ...

Page 409: ...by the level high or low specified with the SPPTx bit At cold start SEPT is set to 0 level At hot start SEPT retains its state from prior to the initial reset SPPK11 SPPK10 FPK1 interrupt input port selection D 3 2 Key input interrupt select register 0x402CA SPPK01 SPPK00 FPK0 interrupt input port selection D 1 0 Key input interrupt select register 0x402CA Select an input pin group for key interru...

Page 410: ... 6 4 Port input 4 5 interrupt priority register 0x4026C PP6L2 PP6L0 Port input 6 interrupt level D 2 0 Port input 6 7 interrupt priority register 0x4026D PP7L2 PP7L0 Port input 7 interrupt level D 6 4 Port input 6 7 interrupt priority register 0x4026D PK0L2 PK0L0 Key input 0 interrupt level D 2 0 Key input interrupt priority register 0x40262 PK1L2 PK1L0 Key input 1 interrupt level D 6 4 Key input ...

Page 411: ... 4 The value set in the corresponding interrupt priority register is higher than the interrupt level IL of the CPU When using the interrupt factor of the port input to request IDMA note that even when the above conditions are met no interrupt request to the CPU is generated for the interrupt factor that has occurred If interrupts are enabled at the setting of IDMA an interrupt is generated under t...

Page 412: ...interrupt factor occurs thereby performing a programmed data transfer If the bit is set to 0 normal interrupt processing is performed without invoking IDMA For details on IDMA refer to IDMA Intelligent DMA At initial reset RP is set to 0 interrupt request DEP3 DEP0 Port input 3 0 IDMA enable D 3 0 Port input 0 3 high speed DMA 16 bit timer 0 IDMA enable register 0x40294 DEP7 DEP4 Port input 7 4 ID...

Page 413: ...ge interrupt setting Restarted by high level input In case of falling edge interrupt setting Restarted by low level input In normal operation a restart begins following the elapse of a given time after execution of the SLP instruction but when restart by a falling rising level edge is set the operation is as follows The restart is effected immediately after execution of the SLP instruction As port...

Page 414: ...III PERIPHERAL BLOCK INPUT OUTPUT PORTS B III 9 26 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK ...

Page 415: ...S1C33L03 FUNCTION PART IV ANALOG BLOCK ...

Page 416: ......

Page 417: ...PERI_PAD Pads C33_PERI Prescaler 8 bit timer 16 bit timer Clock timer Serial interface Ports C33 Peripheral Block C33 Analog Block C33_CORE CPU BCU ITC CLG DBG C33_ADC A D converter C33 Internal Memory Block Internal RAM Area 0 Internal ROM Area 10 C33 DMA Block C33_DMA IDMA HSDMA C33_SDRAMC SDRAM interface C33_LCDC LCD panel interface C33 SDRAM Controller Block Figure 1 1 Analog Block Note Intern...

Page 418: ...IV ANALOG BLOCK INTRODUCTION B IV 1 2 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK ...

Page 419: ...on of multiple channels can be performed in each mode Four types of A D conversion start triggers can be selected Triggered by the external pin ADTRG Triggered by the compare match B of the 16 bit programmable timer 0 Triggered by the underflow of the 8 bit programmable timer 0 Triggered by the software A D conversion results can be read out from a 10 bit data register An interrupt is generated up...

Page 420: ...AVDDE VDDE Note When the A D converter is set to enabled state a current flows between AVDDE and VSS and power is consumed even when A D operations are not performed Therefore when the A D converter is not used it must be set to the disabled state default 0 setting of ADE D2 in the A D enable register 0x40244 AD 7 0 analog signal input pins The analog input pins AD7 Ch 7 through AD0 Ch 0 are share...

Page 421: ...for this selection Table 2 2 Input Clock Selection PSAD2 PSAD1 PSAD0 Division ratio 1 1 1 fPSCIN 256 1 1 0 fPSCIN 128 1 0 1 fPSCIN 64 1 0 0 fPSCIN 32 0 1 1 fPSCIN 16 0 1 0 fPSCIN 8 0 0 1 fPSCIN 4 0 0 0 fPSCIN 2 fPSCIN Prescaler input clock frequency The selected clock is output from the prescaler to the A D converter by writing 1 to PSONAD D3 A D clock control register 0x4014F Notes The A D conver...

Page 422: ...executed successively until stopped by the software At initial reset the normal mode is selected Selecting a trigger Use TS 1 0 D 4 3 A D trigger register 0x40242 to select a trigger to start A D conversion from among the four types shown in Table 2 4 Table 2 4 Trigger Selection TS1 TS0 Trigger 1 1 External trigger K52 ADTRG 1 0 8 bit programmable timer 0 0 1 16 bit programmable timer 0 0 0 Softwa...

Page 423: ...r ADST A D operation ADD ADF Conversion result read OWE Interrupt request AD0 1 AD0 1 Sampling Conversion AD0 2 AD0 2 Sampling Conversion AD0 3 AD0 1 converted data AD0 2 converted data When only AD0 is converted Reset in software invalid Sampling Conversion 2 Continuous mode Figure 2 2 Operation of A D Converter Starting up the A D converter circuit After the settings specified in the preceding s...

Page 424: ...rsion results If ADD 9 0 is updated when the conversion complete flag ADF 1 before the converted data is read out the overwrite error flag OWE D0 A D enable register 0x40244 is set to 1 The conversion complete flag ADF is reset to 0 when the converted data is read out If ADD 9 0 is updated when ADF 0 OWE remains at 0 indicating that the operation has been completed normally When reading out data a...

Page 425: ...curred refer to ITC Interrupt Controller Intelligent DMA The A D converter can invoke the intelligent DMA IDMA through the use of its interrupt factor This allows the conversion results to be transferred to a specified memory location with no need to execute an interrupt processing routine The IDMA channel number assigned to the A D converter is 0x1B Before IDMA can be invoked the IDMA request and...

Page 426: ...ERTER B IV 2 8 EPSON S1C33L03 FUNCTION PART Trap vector The A D converter s interrupt trap vector default address is set to 0x0C00100 The base address of the trap table can be changed using the TTBR register 0x48134 to 0x48137 ...

Page 427: ...ersion channel status 1 1 0 0 1 0 1 0 TS 1 0 Trigger ADTRG pin 8 bit timer 0 16 bit timer 0 Software 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 CH 2 0 Channel AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 0 0 0 0 0 R W R W R 0 when being read 0040242 B 1 Continuous 0 Normal A D trigger register 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 CE 2 0 End channel AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 1 1 1 1 0 0 ...

Page 428: ...4 reserved A D converter SIF Ch 1 transmit buffer empty SIF Ch 1 receive buffer full 0 0 0 0 0 0 0 R W R W R W R W R W R W R W 0 when being read 0040297 B 1 IDMA enabled 0 IDMA disabled 1 IDMA enabled 0 IDMA disabled Serial I F Ch 1 A D port input 4 7 IDMA enable register CFK54 CFK53 CFK52 CFK51 CFK50 D7 5 D4 D3 D2 D1 D0 reserved K54 function selection K53 function selection K52 function selection...

Page 429: ... ADTRG 1 0 8 bit programmable timer 0 0 1 16 bit programmable timer 0 0 0 Software When an external trigger is used use the CFK52 bit to set the K52 pin for ADTRG When a programmable timer is used since its underflow signal 8 bit timer or comparison match B signal 16 bit timer serves as a trigger set the cycle and other parameters for the programmable timer At initial reset TS is set to 0 software...

Page 430: ...cally At initial reset ADE is set to 0 disabled ADST A D conversion control status D1 A D enable register 0x40244 Controls A D conversion Write 1 Software trigger Write 0 A D conversion is stopped Read Valid If A D conversion is to be started by a software trigger set ADST to 1 If any other trigger is used ADST is automatically set to 1 by the hardware ADST remains set while A D conversion is unde...

Page 431: ...E A D converter interrupt factor flag D0 Port input 4 7 clock timer A D interrupt factor flag register 0x40287 Indicates the status of an A D converter interrupt factor generated When read Read 1 Interrupt factor has occurred Read 0 No interrupt factor has occurred When written using the reset only method default Write 1 Interrupt factor flag is reset Write 0 Invalid When written using the read wr...

Page 432: ...es indeterminate so be sure to reset it in the software RADE A D converter IDMA request D2 Serial I F Ch 1 A D port input 4 7 IDMA request register 0x40293 Specifies whether to invoke IDMA when an interrupt factor occurs When using the set only method default Write 1 IDMA request Write 0 Not changed Read Valid When using the read write method Write 1 IDMA request Write 0 Interrupt request Read Val...

Page 433: ...SS and power is consumed even when A D operations are not performed Therefore when the A D converter is not used it must be set to the disabled state default 0 setting of ADE D2 in the A D enable register 0x40244 7 Once A D conversion ends further A D conversion will not be performed correctly if restarted within an interval shorter than one cycle of the A D converter operating clock set by the pr...

Page 434: ...IV ANALOG BLOCK A D CONVERTER B IV 2 16 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK ...

Page 435: ...S1C33L03 FUNCTION PART V DMA BLOCK ...

Page 436: ......

Page 437: ... information CORE_PAD Pads C33_SBUS C33 Core Block C33 LCD Controller Block Pads PERI_PAD Pads C33_PERI Prescaler 8 bit timer 16 bit timer Clock timer Serial interface Ports C33 Peripheral Block C33 Analog Block C33_CORE CPU BCU ITC CLG DBG C33_ADC A D converter C33 Internal Memory Block Internal RAM Area 0 Internal ROM Area 10 C33 DMA Block C33_DMA IDMA HSDMA C33_SDRAMC SDRAM interface C33_LCDC L...

Page 438: ...V DMA BLOCK INTRODUCTION B V 1 2 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK ...

Page 439: ...n High speed DMA DMA request End of DMA DMAREQx DMAENDx Figure 2 1 Dual Address Transfer Method Single address transfer In this method data transfers that are normally accomplished by executing data read and write operations back to back are executed on the external bus collectively at one time thus further speeding up the transfer operation The DMAACKx and DMAENDx signals are used to control data...

Page 440: ...he signal can be selected The DMAREQ0 to DMAREQ3 pins correspond to channel 0 to channel 3 respectively In addition to this external input software trigger or an interrupt factor can be selected for the HSDMA trigger factor using the register in the interrupt controller DMAACKx DMA acknowledge signal output pin for single address mode This signal is output to indicate that a DMA request has been a...

Page 441: ...MOD 1 0 Ch 3 transfer mode D F E HSDMA Ch 3 high order destination address set up register 0x4825A The following three transfer modes are available Single transfer mode DxMOD 00 default In this mode a transfer operation invoked by one trigger is completed after transferring one unit of data of the size set by DATSIZEx If data transfer need to be performed a number of times as set by the transfer c...

Page 442: ... 7 0 Ch 1 transfer counter 7 0 D 7 0 HSDMA Ch 1 transfer counter register 0x48230 BLKLEN2 7 0 Ch 2 transfer counter 7 0 D 7 0 HSDMA Ch 2 transfer counter register 0x48240 BLKLEN3 7 0 Ch 3 transfer counter 7 0 D 7 0 HSDMA Ch 3 transfer counter register 0x48250 TC0_L 7 0 Ch 0 transfer counter 15 8 D F 8 HSDMA Ch 0 transfer counter register 0x48220 TC1_L 7 0 Ch 1 transfer counter 15 8 D F 8 HSDMA Ch ...

Page 443: ...rder source address set up register 0x48256 D0IN 1 0 Ch 0 destination address control D D C Ch 0 high order destination address set up register 0x4822A D1IN 1 0 Ch 1 destination address control D D C Ch 1 high order destination address set up register 0x4823A D2IN 1 0 Ch 2 destination address control D D C Ch 2 high order destination address set up register 0x4824A D3IN 1 0 Ch 3 destination addres...

Page 444: ...ize 8 bits is assumed if this bit is 0 default Block length When using block transfer mode DxMOD 10 the data block length in units of DATSIZEx should be set using the BLKLENx 7 0 bits In single transfer and successive transfer modes BLKLENx 7 0 is used as the bits7 0 of the transfer counter Transfer counter Block transfer mode In block transfer mode up to 16 bits of transfer count can be specified...

Page 445: ...x48246 S3IN 1 0 Ch 3 memory address control D D C Ch 3 high order source address set up register 0x48256 SxIN 00 address fixed default SxIN 01 address decremented without initialization SxIN 10 address incremented with initialization SxIN 11 address incremented without initialization Refer to the explanation in Setting the Registers in Dual Address Mode DxIN 1 0 is not used in single address mode ...

Page 446: ...empty Serial I F Ch 1 Tx buffer empty 1100 A D conversion completion A D conversion completion A D conversion completion A D conversion completion By selecting an interrupt factor with the HSDMA trigger set up register the HSDMA channel is invoked when the selected interrupt factor occurs The interrupt control bits interrupt factor flag interrupt enable register IDMA request register interrupt pri...

Page 447: ...Ex If a data transfer needs to be performed a number of times as set by the transfer counter an equal number of triggers are required The operation of HSDMA in single transfer mode is shown by the flow chart in Figure 2 3 START END Data read from source 1 byte or 1 half word Clear trigger flag HSx_TF to accept next trigger Clear HSDMA enable bit HSx_EN Data write to destination 1 byte or 1 half wo...

Page 448: ...read from source 1 byte or 1 half word Data write to destination 1 byte or 1 half word Clear trigger flag HSx_TF to accept next trigger Clear HSDMA enable bit HSx_EN Set interrupt factor flag FHDMx Figure 2 4 Operation Flow in Successive Transfer Mode 1 When a trigger is accepted the trigger flag HSx_TF is cleared and then data of the size set in the control information is read from the source add...

Page 449: ...ng to SxIN DxIN settings Data read from source 1 byte or 1 half word Data write to destination 1 byte or 1 half word Increments decrements address according to SxIN DxIN settings Clear trigger flag HSx_TF to accept next trigger Clear HSDMA enable bit HSx_EN Set interrupt factor flag FHDMx Figure 2 5 Operation Flow in Block Transfer Mode 1 When a trigger is accepted the trigger flag HSx_TF is clear...

Page 450: ...ransfer belongs The data bus is left floating The external I O device outputs the transfer data onto the data bus using the DMAACKx signal as the read signal The memory takes in this data using the write signal Data transfer from memory to an I O device The address that has been set in the memory address register is output to the address bus A read operation is performed under the interface condit...

Page 451: ... inserted BCLK A 23 0 CE src CE dst RD WRH WRL DMAEND source address destination address Read cycle Write cycle Figure 2 6 DMAEND Signal Output Timing SRAM 2 DRAM Example Page mode RAS 1 cycle CAS 2 cycles Precharge 1 cycle BCLK A 11 0 RASx HCAS LCAS RD WR DMAEND ROW COL 1 COL 2 ROW COL 1 COL 2 Read cycle Write cycle Figure 2 7 DMAEND Signal Output Timing DRAM ...

Page 452: ...n 4 consecutive burst and 2 wait cycles are set during the first access BCLK A 23 2 A 1 0 CE10 9 D 15 0 RD DMAACK DMAEND addr 23 2 11 10 01 00 Figure 2 9 DMAACK DMAEND Signal Output Timing Burst ROM 3 DRAM Example Page mode RAS 1 cycle CAS 2 cycles Precharge 1 cycle BCLK A 11 0 RASx HCAS LCAS RD WR DMAACK DMAEND ROW COL 1 COL 2 Figure 2 10 DMAACK DMAEND Signal Output Timing DRAM Note The single ad...

Page 453: ...HSDMA interrupt factor flag to 1 when the transfer counter reaches 0 after completing a series of HSDMA transfers If the corresponding bit of the interrupt enable register is set to 1 at this time an interrupt request is generated Interrupts can be disabled by leaving the interrupt enable register bit set to 0 The HSDMA interrupt factor flag is always set to 1 when the data transfer in each channe...

Page 454: ... 0x40290 DEHDM1 D5 0x40294 If the IDMA request and enable bits are set to 1 IDMA is invoked through generation of an interrupt factor No interrupt request is generated at that point An interrupt request is generated after the DMA transfer is completed The registers can also be set so as not to generate an interrupt with only a DMA transfer performed For details on IDMA transfers and interrupt cont...

Page 455: ...MA Ch 0 0 0 0 0 0 R W R W R W R W R W 0 when being read 0040271 B 1 Enabled 0 Disabled DMA interrupt enable register FIDMA FHDM3 FHDM2 FHDM1 FHDM0 D7 5 D4 D3 D2 D1 D0 reserved IDMA High speed DMA Ch 3 High speed DMA Ch 2 High speed DMA Ch 1 High speed DMA Ch 0 X X X X X R W R W R W R W R W 0 when being read 0040281 B DMA interrupt factor flag register 1 Factor is generated 0 No factor is generated...

Page 456: ...h 2 trigger set up 0 0 0 0 0 0 0 0 R W R W 0040299 B 0 1 2 3 4 5 6 7 8 9 A B C Software trigger K54 input falling edge K54 input rising edge Port 3 input Port 7 input 8 bit timer Ch 3 underflow 16 bit timer Ch 3 compare B 16 bit timer Ch 3 compare A 16 bit timer Ch 5 compare B 16 bit timer Ch 5 compare A SI F Ch 1 Rx buffer full SI F Ch 1 Tx buffer empty A D conversion completion 0 1 2 3 4 5 6 7 8...

Page 457: ...n selection P33 function selection P32 function selection P31 function selection P30 function selection 0 0 0 0 0 0 R W R W R W R W R W R W 0 when being read Ext func 0x402DF 00402DC B P3 function select register 1 BUSACK 0 P35 1 BUSREQ CE6 0 P34 1 DMAACK0 0 P32 1 BUSGET 0 P31 1 WAIT CE4 CE5 0 P30 1 DMAACK1 0 P33 CFEX7 CFEX6 CFEX5 CFEX4 CFEX3 CFEX2 CFEX1 CFEX0 D7 D6 D5 D4 D3 D2 D1 D0 P07 port exte...

Page 458: ... X X X X R W 0048224 HW High speed DMA Ch 0 low order source address set up register Note D Dual address mode S Single address mode DATSIZE0 S0IN1 S0IN0 S0ADRH11 S0ADRH10 S0ADRH9 S0ADRH8 S0ADRH7 S0ADRH6 S0ADRH5 S0ADRH4 S0ADRH3 S0ADRH2 S0ADRH1 S0ADRH0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 reserved Ch 0 transfer data size D Ch 0 source address control S Ch 0 memory address control D Ch 0 s...

Page 459: ...ing Ch 0 trigger flag status reading 1 Clear 0 No operation 1 Set 0 Cleared 0 R W Undefined in read 004822E HW High speed DMA Ch 0 trigger flag register TC1_L7 TC1_L6 TC1_L5 TC1_L4 TC1_L3 TC1_L2 TC1_L1 TC1_L0 BLKLEN17 BLKLEN16 BLKLEN15 BLKLEN14 BLKLEN13 BLKLEN12 BLKLEN11 BLKLEN10 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch 1 transfer counter 7 0 block transfer mode Ch 1 transfer counter 15 ...

Page 460: ...1ADRH0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 reserved Ch 1 transfer data size D Ch 1 source address control S Ch 1 memory address control D Ch 1 source address 27 16 S Ch 1 memory address 27 16 0 0 0 X X X X X X X X X X X X R W R W R W 0048236 HW 1 Half word 0 Byte High speed DMA Ch 1 high order source address set up register Note D Dual address mode S Single address mode 1 1 0 0 1 0 1 0...

Page 461: ...ing Ch 1 trigger flag status reading 1 Clear 0 No operation 1 Set 0 Cleared 0 R W Undefined in read 004823E HW High speed DMA Ch 1 trigger flag register TC2_L7 TC2_L6 TC2_L5 TC2_L4 TC2_L3 TC2_L2 TC2_L1 TC2_L0 BLKLEN27 BLKLEN26 BLKLEN25 BLKLEN24 BLKLEN23 BLKLEN22 BLKLEN21 BLKLEN20 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch 2 transfer counter 7 0 block transfer mode Ch 2 transfer counter 15 ...

Page 462: ...2ADRH0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 reserved Ch 2 transfer data size D Ch 2 source address control S Ch 2 memory address control D Ch 2 source address 27 16 S Ch 2 memory address 27 16 0 0 0 X X X X X X X X X X X X R W R W R W 0048246 HW 1 Half word 0 Byte High speed DMA Ch 2 high order source address set up register Note D Dual address mode S Single address mode 1 1 0 0 1 0 1 0...

Page 463: ...ing Ch 2 trigger flag status reading 1 Clear 0 No operation 1 Set 0 Cleared 0 R W Undefined in read 004824E HW High speed DMA Ch 2 trigger flag register TC3_L7 TC3_L6 TC3_L5 TC3_L4 TC3_L3 TC3_L2 TC3_L1 TC3_L0 BLKLEN37 BLKLEN36 BLKLEN35 BLKLEN34 BLKLEN33 BLKLEN32 BLKLEN31 BLKLEN30 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch 3 transfer counter 7 0 block transfer mode Ch 3 transfer counter 15 ...

Page 464: ...3ADRH0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 reserved Ch 3 transfer data size D Ch 3 source address control S Ch 3 memory address control D Ch 3 source address 27 16 S Ch 3 memory address 27 16 0 0 0 X X X X X X X X X X X X R W R W R W 0048256 HW 1 Half word 0 Byte High speed DMA Ch 3 high order source address set up register Note D Dual address mode S Single address mode 1 1 0 0 1 0 1 0...

Page 465: ...r CFK51 CFK50 K5 1 0 pin function selection D 1 0 K5 function select register 0x402C0 CFK54 CFK53 K5 4 3 pin function selection D 4 3 K5 function select register 0x402C0 Set the DMAREQx pin of HSDMA Write 1 DMAREQx input Write 0 Input port Read Valid CFK50 CFK51 CFK53 and CFK54 are the function select bits for K50 DMAREQ0 K51 DMAREQ1 K53 DMAREQ2 and K54 DMAREQ3 respectively When using the DMAREQx ...

Page 466: ...o 0 input mode At hot start the bit retains its state from prior to the initial reset CFP33 CFP32 P3 3 2 pin function selection D 3 2 P3 function select register 0x402DC Set the DMAACKx pin of HSDMA Write 1 DMAACKx output Write 0 I O port Read Valid When using the DMAACK0 signal set the P32 pin for the DMAACK0 output pin by writing 1 to CFP32 Similarly when using the DMAACK1 signal set the P33 pin...

Page 467: ...ial I F Ch 1 Rx buffer full Serial I F Ch 0 Rx buffer full Serial I F Ch 1 Rx buffer full 1011 Serial I F Ch 0 Tx buffer empty Serial I F Ch 1 Tx buffer empty Serial I F Ch 0 Tx buffer empty Serial I F Ch 1 Tx buffer empty 1100 A D conversion completion A D conversion completion A D conversion completion A D conversion completion At initial reset HSDxS is set to 0000 software trigger HST0 Ch 0 sof...

Page 468: ...UALM3 Ch 3 address mode selection DF HSDMA Ch 3 control register 0x48252 Select an address mode Write 1 Dual address mode Write 0 Single address mode Read Valid When 1 is written to DUALMx the HSDMA channel enters dual address mode that allows specification of source and destination addresses When 0 is written the HSDMA channel enters single address mode for high speed data transfer between the ex...

Page 469: ... Read Valid The transfer data size is set to 16 bits by writing 1 to DATSIZEx and set to 8 bits by writing 0 At initial reset DATSIZEx is set to 0 8 bits S0IN1 S0IN0 Ch 0 source address control D D C Ch 0 high order source address set up register 0x48226 S1IN1 S1IN0 Ch 1 source address control D D C Ch 1 high order source address set up register 0x48236 S2IN1 S2IN0 Ch 2 source address control D D ...

Page 470: ...x48230 BLKLEN27 BLKLEN20 Ch 2 block length transfer counter 7 0 D 7 0 Ch 2 transfer counter register 0x48240 BLKLEN37 BLKLEN30 Ch 3 block length transfer counter 7 0 D 7 0 Ch 3 transfer counter register 0x48250 In block transfer mode these bits are used to specify a transfer block size A transfer operation invoked by one trigger is completed after transferring one block of data of the size set by ...

Page 471: ...stination address set up register 0x48228 D0ADRH11 D0ADRH0 Ch 0 destination address 27 16 D B 0 Ch 0 high order destination address set up register 0x4822A D1ADRL15 D1ADRL0 Ch 1 destination address 15 0 D F 0 Ch 1 low order destination address set up register 0x48238 D1ADRH11 D1ADRH0 Ch 1 destination address 27 16 D B 0 Ch 1 high order destination address set up register 0x4823A D2ADRL15 D2ADRL0 C...

Page 472: ...wing conditions are met at this time 1 The corresponding interrupt enable register is set to 1 2 No other interrupt request of higher priority is generated 3 The IE bit of the PSR is set to 1 interrupt enable 4 The corresponding interrupt priority register is set to a level higher than the CPU s interrupt level IL When using an interrupt factor to request IDMA note that even when the above conditi...

Page 473: ...rogrammed data transfer If the register is set to 0 regular interrupt processing is performed without ever invoking IDMA For details on IDMA refer to IDMA Intelligent DMA At initial reset RHDMx is set to 0 interrupt request DEHDM0 Ch 0 IDMA enable D4 Port input 0 3 HSDMA 16 bit timer 0 IDMA enable register 0x40294 DEHDM1 Ch 1 IDMA enable D5 Port input 0 3 HSDMA 16 bit timer 0 IDMA enable register ...

Page 474: ...DMA share the same circuit HSDMA cannot gain the bus ownership while an IDMA transfer is under way Requests for HSDMA invocation that have occurred during an IDMA transfer are kept pending until the IDMA transfer is completed A request for IDMA invocation or an interrupt request that has occurred during a HSDMA transfer are accepted after completion of the HSDMA transfer 5 In HALT mode since the D...

Page 475: ...tarting address of channel 0 Consequently an area of 384 words 1 536 bytes in RAM is required in order for all of 128 channels to be used The following explains how to set the base address and the contents of control information Before using IDMA make each the settings described below Setting the base address Set the starting address of control information starting address of channel 0 in the IDMA...

Page 476: ...0 0 Single transfer mode D29 28 DSINC 1 0 Destination address control DSINC1 DSINC0 Setting contents 1 1 Address incremented In block transfer mode the transfer address is updated without reset using the initial value 1 0 Address incremented In block transfer mode the transfer address is updated with the initial value 0 1 Address decremented In block transfer mode the transfer address is updated w...

Page 477: ... for address increment 11 or 10 in single and successive transfer modes the source address is incremented by an amount equal to the data size set by DATSIZ when one data transfer is completed If the format is set for address decrement 01 the source address is decremented in the same way In block transfer mode too the source address is incremented or decremented when one data unit is transferred Ho...

Page 478: ...f the format is set for address decrement 01 the destination address is decremented in the same way In block transfer mode as well the destination address is incremented or decremented when one data unit is transferred However if the set format is 10 the destination address that has been incremented during a block transfer recycles back to the initial value when the block transfer is completed DSA...

Page 479: ... 0x40290 DEHDM0 D4 0x40294 Ch 1 end of transfer 6 RHDM1 D5 0x40290 DEHDM1 D5 0x40294 16 bit programmable Timer 0 comparison B 7 R16TU0 D6 0x40290 DE16TU0 D6 0x40294 timer Timer 0 comparison A 8 R16TC0 D7 0x40290 DE16TC0 D7 0x40294 Timer 1 comparison B 9 R16TU1 D0 0x40291 DE16TU1 D0 0x40295 Timer 1 comparison A 10 R16TC1 D1 0x40291 DE16TC1 D1 0x40295 Timer 2 comparison B 11 R16TU2 D2 0x40291 DE16TU...

Page 480: ... to 0 the relevant interrupt factor generates an interrupt request and not a IDMA request The control registers interrupt enable register and interrupt priority register corresponding to the interrupt factor do not affect IDMA invocation IDMA can be invoked even if the interrupt enable bit in ITC is set to 0 interrupt disabled However these register must be set to enable the interrupt when generat...

Page 481: ... factor is used Therefore an interval longer than the DMA transfer period is required when invoking the same channel IDMA invocation request when DMA transfer is disabled An IDMA invocation request generated when IDMAEN is 0 DMA transfer disabled is kept pending until IDMAEN is set to 1 Since an invocation request is not cleared it is accepted when DMA transfer is enabled Simultaneous generation o...

Page 482: ... Transfer counter 1 Saves channel control information IDMA interrupt processing if interrupt is enabled Transfer counter 0 A Base address Channel number 12 B 3 words C Data read from source of transfer D Data write to destination of transfer E F 3 words N Trigger Y A B1 B2 B3 C D E F1 F2 F3 Figure 3 1 Operation Flow in Single Transfer Mode 1 When a trigger is accepted the address for control infor...

Page 483: ...ransfer E F 3 words N Trigger Y A B1 B2 B3 C1 D1 E1 Cn Dn En F1 F2 F3 Figure 3 2 Operation Flow in Successive Transfer Mode 1 When a trigger is accepted the address for control information is calculated from the base address and channel number 2 Control information is read from the calculated address into the internal temporary register 3 Data of the size set in the control information is read fro...

Page 484: ...F G H1 H2 H3 Transfer counter 1 Saves channel control information Transfer counter 0 H 3 words N Y according to SRINC DSINC settings Figure 3 3 Operation Flow in Block Transfer Mode 1 When a trigger is accepted the address for control information is calculated from the base address and channel number 2 Control information is read from the calculated address into the internal temporary register 3 D...

Page 485: ... but the IDMA enable bit is cleared 2 1 0 Trigger by interrupt factor Data transfer Transfer counter DINTEN IDMA request bit IDMA enable bit Interrupt factor flag Interrupt request 1 0 Figure 3 4 Operation when Invoked by Interrupt Factor When IDMA is invoked by the software trigger the IDMA interrupt factor flag FIDMA D4 DMA interrupt factor flag register 0x40281 will not be set When invoked by a...

Page 486: ... interrupt at the end of an IDMA transfer the DINTEN end of transfer interrupt enable bits in the IDMA control information for the first IDMA channel to be invoked and all the channels to be linked must be set to 1 For trigger in the software application 1 The IDMA channel 3 is invoked by a trigger in the software application and the DMA transfer that is set is performed Since the IDMA is operatin...

Page 487: ...interrupt factor occurring during an IDMA transfer has higher priority than the interrupt factor that invoked the IDMA transfer an interrupt request for it or a new IDMA invocation request is not accepted until after the current IDMA transfer is completed Software triggered interrupts If the transfer counter is decremented to 0 and DINTEN 1 interrupt enabled when one DMA transfer operation is comp...

Page 488: ...0 reserved IDMA High speed DMA Ch 3 High speed DMA Ch 2 High speed DMA Ch 1 High speed DMA Ch 0 X X X X X R W R W R W R W R W 0 when being read 0040281 B DMA interrupt factor flag register 1 Factor is generated 0 No factor is generated DBASEL15 DBASEL14 DBASEL13 DBASEL12 DBASEL11 DBASEL10 DBASEL9 DBASEL8 DBASEL7 DBASEL6 DBASEL5 DBASEL4 DBASEL3 DBASEL2 DBASEL1 DBASEL0 DF DE DD DC DB DA D9 D8 D7 D6 ...

Page 489: ...intelligent DMA is enabled by writing 1 to IDMAEN IDMA transfer is disabled by writing 0 to IDMAEN At initial reset IDMAEN is set to 0 disabled DCHN 6 0 IDMA channel number D 6 0 IDMA start register 0x48204 Set the channel numbers 0 to 127 to be invoked by a trigger in the software application At initial reset DCHN is set to 0 DSTART IDMA start D7 IDMA start register 0x48204 Use this register for ...

Page 490: ...register bit is set to 1 2 No interrupt request of higher priority is generated 3 The IE bit of the PSR is set to 1 interrupt enable 4 The corresponding interrupt priority register is set to a level higher than the CPU s interrupt level IL In order for the next interrupt to be accepted after interrupt generation the interrupt factor flag must be reset and the PSR must be set up again by setting th...

Page 491: ...ng conditions are met the transfer counter value becomes invalid during IDMA transfer so data cannot be transferred properly 1 The IDMA control information source destination addresses transfer counter etc is placed in the external EDO DRAM 2 The DRAM access timing condition is set to EDO mode by the BCU register 3 The bus clock is set to x2 speed mode X2SPD pin 0 When placing the control informat...

Page 492: ...V DMA BLOCK IDMA Intelligent DMA B V 3 18 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK ...

Page 493: ...S1C33L03 FUNCTION PART VI SDRAM CONTROLLER BLOCK ...

Page 494: ......

Page 495: ...LCD Controller Block Pads PERI_PAD Pads C33_PERI Prescaler 8 bit timer 16 bit timer Clock timer Serial interface Ports C33 Peripheral Block C33 Analog Block C33_CORE CPU BCU ITC CLG DBG C33_ADC A D converter C33 Internal Memory Block Internal RAM Area 0 Internal ROM Area 10 C33 DMA Block C33_DMA IDMA HSDMA C33_SDRAMC SDRAM interface C33_LCDC LCD panel interface C33 SDRAM Controller Block Figure 1 ...

Page 496: ...VI SDRAM CONTROLLER BLOCK INTRODUCTION B VI 1 2 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK ...

Page 497: ...k SDRAM BA1 and BA0 outputs Row address range 2K A10 A0 4K A11 A0 or 8K A12 A0 Column address range 256 A7 A0 512 A8 A0 or 1K A9 A0 Incorporates a programmable 12 bit auto refresh counter The SDRAM can be refreshed as necessary irrespective of the clock frequency used Intelligent self refresh mode for low power operation Two power up options Precharge Refresh Mode Register Set Precharge Mode Regis...

Page 498: ...write Low byte Area address strobe output for GA SDRAM write P33 DMAACK1 SIN3 SDA10 I O I O port HSDMA Ch 1 acknowledge output Serial I F Ch 3 data input SDRAM address bus 10 P32 DMAACK0 SRDY3 HDQM I O I O port HSDMA Ch 0 acknowledge output Serial I F Ch 3 ready signal output SDRAM data High byte input output mask signal output P15 EXCL4 DMAEND0 SCLK3 LDQM I O I O port 16 bit timer 4 event counter...

Page 499: ...AM 2M x 16 bits x 4 banks Figure 2 3 Connecting two 16 bit SDRAMs 32MB SDA 12 11 A 13 12 SDA10 P33 SDA 9 0 A 10 1 SDBA 1 0 A 15 14 D 7 0 BCLK SDCKE P20 SDCE0 1 CE7 8 SDCAS HCAS SDRAS LCAS SDWE P21 LDQM P15 S1C33 A 12 11 A10 A 9 0 BA 1 0 DQ 7 0 CLK CKE CS CAS RAS WE DQM 128M SDRAM 4M x 8 bits x 4 banks For little endian SDA 12 11 A 13 12 SDA10 P33 SDA 9 0 A 10 1 SDBA 1 0 A 15 14 D 15 8 BCLK SDCKE P...

Page 500: ...SDRAM To prevent a malfunction take measures against noise when designing the board patterns for the SDRAM Table 2 2 lists several examples of SDRAM chip configurations All of these examples use only one area of the S1C33 If your design uses two areas the same type of memory needs to be used in each area because SDRAM related settings are common to both areas Table 2 2 Chip Configuration Example w...

Page 501: ...en to the control registers normally 4 SWAITE D0 Bus control register 0x4812E 1 This enables the WAIT signal The IC s internal WAIT signal is used when powering up the SDRAM 5 A6EC D1 Access control register 0x48132 LCDCEC D0 LCDC system control register 0x39FFFD Use these registers to match endian types when reading out area 6 and SDRAMC LCDC Both bits select little endian when 0 or big endian wh...

Page 502: ...r each area Table 2 4 SDRAM Interface Parameters Parameter Selectable condition Initial setting Control bits Area 7 13 configuration SDRAM or Another Another device SDRAR0 D7 SDRAM area configuration register 0x39FFC0 Area 8 14 configuration SDRAM or Another Another device SDRAR1 D6 SDRAM area configuration register 0x39FFC0 CE7 13 pin configuration SDCE0 or CE7 13 CE7 13 SDRPC0 D3 SDRAM area conf...

Page 503: ...E7 and CE8 pins respectively they are not necessarily fixed to either area For example even when using area 7 or 13 for SDRAMs the chip enable used for the SDRAM can be SDCE1 CE8 14 Table 2 5 lists the chip enable address ranges and the SDRAM sizes that can be connected when the area s and chip enable are selected according to the above Table 2 5 Chip Enable Configuration CEFUNC SDRAR0 SDRAR1 SDRP...

Page 504: ...g Range Page Size SDRCA1 SDRCA0 Column size Column address pin used 0 0 256 SDA0 SDA7 default 0 1 512 SDA0 SDA8 1 0 1 024 SDA0 SDA9 1 1 Table 2 8 Setting Row Addressing Range SDRRA1 SDRRA0 Row size Row address pin used 0 0 2K SDA0 SDA10 default 0 1 4K SDA0 SDA11 1 0 8K SDA0 SDA12 1 1 The SDRAM controller uses only the lower 24 bits of the 28 bit address bus The relationship between the CPU address...

Page 505: ...ransfers are effective only when reading data from SDRAM When writing to SDRAM data are always written in a single operation not in bursts no matter what burst length is selected The SDRAM controller is designed in such a way that when one cycle of burst read is finished it automatically issues the READ command to continue with transfers Therefore unless SDRBL 1 0 00 the speed at which SDRAM is ac...

Page 506: ...M DQ 15 0 Bank 1 Bank 2 ACTV H NOP NOP NOP ACTV READ READ READ BA1 BA1 ROW2 D n tRRD tRP Bank 1 cannot be accessed CAS latency 2 CAS latency 2 tRCD 2 ROW2 ROW1 ROW1 Active Read Precharge Active Read COLn BA2 COLm BA1 COLl BA2 PRE NOP NOP BA1 D m D l ACTV BA1 ROW3 ROW3 BCLK Command SDCKE SDCEx SDRAS SDCAS SDWE SDBA 1 0 SDA 10 SDA 12 11 9 0 LDQM HDQM DQ 15 0 Bank 1 Bank 2 H NOP NOP ACTV READ PRE NOP...

Page 507: ...DRAM timing set up register 1 0x39FFC4 tRRD ACTIVE bank a to ACTIVE bank b period 1 to 4 SDRTRRD 1 0 D 4 3 SDRAM timing set up register 2 0x39FFC5 tRSC MODE REGISTER SET cycle time 1 or 2 SDRTRSC D5 SDRAM timing set up register 2 0x39FFC5 BCLK Command SDBA 1 0 SDA 12 11 9 0 SDA10 DQ 15 0 ACTV NOP NOP NOP NOP NOP PRE READ BA BA ROW COL ROW BA ROW ROW DATA DATA DATA DATA tRCD tRAS tRC tRP CAS latenc...

Page 508: ...e BCU operating clock BCU_CLK X2SPD 1 CPU SDRAM clock ratio is set to 1 1 The SDRAM clock and the CPU system clock will be the same X2SPD 0 CPU SDRAM clock ratio is set to 2 1 The SDRAM clock frequency becomes half of the CPU system clock While the SDRAM is self refreshed the SDRAM clock output can be turned off in order to reduce the chip s current consumption To set this feature use the SDRCLK D...

Page 509: ...or 100 µs or more after turning on the power to the SDRAM After the power to the SDRAM is turned on the SDRAM must be held in an NOP state SDCEx high for at least 100 µs Because the duration of this period varies with each SDRAM consult the specifications for your SDRAM 4 SDRINI D6 SDRAM control register 0x39FFC1 1 This causes the SDRAM controller to output the commands in the order specified by t...

Page 510: ...DRAM Commands Command Pins Function Symbol SDCKE DQM H LDQM Bank A 15 14 SDA10 SDA A 13 12 A 10 1 SDCEx SDRAS SDCAS SDWE Bank Active ACTV H X V V V L L H H Bank Precharge PRE H X V L X L L H L Precharge All PALL H X X H X L L H L Write WRIT H X V L V L H L L Read READ H X V L V L H L H Mode Register Set MRS H X V V V L L L L Deselect NOP NOP H X X X X H X X X Auto Refresh REF H X X X X L L L H Sel...

Page 511: ...mmand SDCKE SDCEx SDRAS SDCAS SDWE SDBA 1 0 SDA 10 SDA 12 11 9 0 LDQM HDQM DQ 15 0 ACTV NOP H NOP NOP PRE NOP READ BA BA ROW D 1 D 2 D 3 D 4 D 5 D 6 tRCD tRP CAS latency 2 ROW COL BA 2 Burst length 4 BCLK Command SDCKE SDCEx SDRAS SDCAS SDWE SDBA 1 0 SDA 10 SDA 12 11 9 0 LDQM HDQM DQ 15 0 ACTV NOP H NOP NOP PRE NOP READ BA BA ROW D 1 D 2 D 3 D 4 tRCD tRP CAS latency 2 ROW COL BA 3 Burst length 2 B...

Page 512: ... set to 1 SDRBL 1 0 00 the SDRAM controller reads data from the SDRAM in a single operation When writing to the SDRAM data are always written in a single operation no matter what burst length is selected BCLK Command SDCKE SDCEx SDRAS SDCAS SDWE SDBA 1 0 SDA 10 SDA 12 11 9 0 LDQM HDQM DQ 15 0 ACTV NOP H NOP NOP PRE NOP READ BA1 BA1 ROW1 D 1 tRCD tRP tRCD tRP CAS latency 2 ROW1 COL1 BA1 ACTV NOP PR...

Page 513: ... 11 0 D B 0 Auto refresh count register 0x39FFC6 For SDRARFC set the appropriate value meeting the specifications of your SDRAM The count value is obtained by the equation below RFP SDRARFC fOSC3 BL CL 2 tRP tRCD 3 ROWS RFP Maximum refresh period s ROWS Row address size fOSC3 OSC3 clock frequency Hz BL Burst length word CL CAS latency Number of SD_CLK cycles tRP PRECHARGE command period Number of ...

Page 514: ...d is issued the counter is reset and starts counting again The designated value for the counter can be specified in a range of 2 to 15 by using the SDRSRFC 3 0 D 3 0 SDRAM self refresh count register 0x39FFC8 Always set the SDRAM self refresh count register to 2 or more If it is set to less than 2 the SDRAM cannot exit self refresh mode When an SDRAM access occurs during self refresh mode SDCKE is...

Page 515: ... before switching the CPU clock to OSC1 or turning the OSC3 clock off Note Because the SDRAM is taken out of self refresh mode when accessed steps 2 and 3 of the above procedure must be executed on other memory than SDRAMs Bus Release Procedure When the CPU releases the external bus all of the SDRAM signal input output pins except for BCLK output when SDRCLK 1 are placed in the high impedance stat...

Page 516: ...RAM will not be taken out of self refresh mode when the bus is released 5 In response to the bus request the S1C33 releases the external bus The external bus including the SDRAM interface pins goes to a high impedance state 6 The external bus master takes over control of the SDRAM If SDRCLK D3 0x39FFC1 1 a clock for the SDRAM is output from the BCLK pin Therefore the external bus master must contr...

Page 517: ...ed 0 Disabled 1 Kept 0 Stopped SDRAM control register SDRCA1 SDRCA0 SDRRA1 SDRRA0 SDRBA D7 D6 5 D4 D3 2 D1 D0 reserved SDRAM page size column range reserved SDRAM row addressing range Number of SDRAM banks reserved 0 0 0 0 0 R W R W R W 0 when being read 0 when being read 0 when being read 039FFC2 B 1 4 banks 0 2 banks SDRAM address configuration register 1 1 0 0 1 0 1 0 SDRRA 1 0 Addressing range...

Page 518: ... 1 1 1 1 1 1 1 1 1 1 1 1 R W 0 when being read 039FFC6 HW SDRAM auto refresh count register 0 to 4096 SDRSRFC3 SDRSRFC2 SDRSRFC1 SDRSRFC0 D7 4 D3 D2 D1 D0 reserved SDRAM self refresh count 3 0 1 1 1 1 R W 0 when being read This register must not be set less than 0x02 039FFC8 B SDRAM self refresh count register 2 to 15 SDRSZ SDRBI D7 D6 D5 D4 0 reserved SDRAM data path bit width SDRAM bank interlea...

Page 519: ...isable delay time reserved Areas 8 7 wait control 1 Used 0 Not used 1 Used 0 Not used 1 8 bits 0 16 bits 0 0 0 1 1 1 1 1 R W R W R W R W R W 0 when being read 0 when being read 0048128 HW Areas 8 7 set up register 1 1 0 0 1 0 1 0 A8DF 1 0 Number of cycles 3 5 2 5 1 5 0 5 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 A8WT 2 0 Wait cycles 7 6 5 4 3 2 1 0 A6DF1 A6DF0 A6WT2 A6WT1 A6WT0 A5SZ A5DF1 A5...

Page 520: ...d Area 3 emulation CE pin function selection Successive RAS mode setup DRAM RAS precharge cycles selection reserved DRAM CAS cycles selection reserved DRAM RAS cycles selection 1 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W 0 when being read 0 when being read 0 when being read 0048130 HW 1 0 0 x 1 0 CEFUNC 1 0 CE output CE7 8 CE17 18 CE6 CE17 CE4 CE10 1 1 0 0 1 0 1 0 RPRC 1 0 Number of cycles 4 3 2 1...

Page 521: ...RAM control registers The number of wait cycles in areas used for SDRAMs should be set to 0 A8WT A14WT 000 At cold start these bits are set to 111 7 cycles At hot start the bits retain their status before being initialized A14DF1 A14DF0 Areas 14 13 output disable delay time D 5 4 Areas 14 13 set up register 0x48122 A8DF1 A8DF0 Areas 8 7 output disable delay time D 5 4 Areas 8 7 set up register 0x4...

Page 522: ... 1 to use areas 7 8 for SDRAMs or set A14IO to 1 to use areas 13 14 for SDRAMs At cold start these bits are set to 0 external access At hot start these bits retain their status before being initialized A6EC Area 6 little big endian method selection D1 Access control register 0x48132 Select either little endian or big endian method for accessing each area Write 1 Big endian Write 0 Little endian Re...

Page 523: ...Disabled Read Valid Writing 1 to SDRENA sets the pins shared with other functions to be used for the SDRAM with the SDRAM clock output from the BCLK pin If SDRENA 0 the shared pins serve other functions The SDRAM clock output from the BCLK pin is stopped in the HALT2 and the SLEEP modes At cold start SDRENA is set to 0 disabled At hot start SDRENA retains its status before being initialized SDRINI...

Page 524: ...igh impedance state If SDRCLK 1 the SDRAM clock is always output from the BCLK pin even while the SDRAM is self refreshed or the bus is released At cold start SDRCLK is set to 1 kept outputting At hot start SDRCLK retains its status before being initialized SDRCA1 SDRCA0 SDRAM page size D 6 5 SDRAM address configuration register 0x39FFC2 Set the SDRAM page size column addressing range Table 2 15 S...

Page 525: ...d SDRTRAS2 SDRTRAS0 SDRAM tRAS spec D 7 5 SDRAM timing set up register 1 0x39FFC4 Set the tRAS SDRAM parameter ACTIVE to PRECHARGE command period In accordance with the specifications of the SDRAM specify this parameter in terms of the number of SDRAM clock cycles Specifying 1 7 sets the period to 1 7 clock cycles Specifying 0 sets the period to 8 clock cycles At cold start SDRTRAS is set to 000 8...

Page 526: ...t D B 0 SDRAM auto refresh count register 0x39FFC6 Set the auto refresh counter value The auto refresh counter counts up on the OSC3 clock edges beginning with 0 and when the count specified here is reached the SDRAM controller sends an auto refresh command The counter is reset at that point and starts counting the next refresh period The counter is also reset by self refresh The value calculated ...

Page 527: ...command Read 1 Not finished Read 0 Finished Write Invalid SDRMRS is automatically set to 1 at power on and is reset to 0 by executing the MRS command in the SDRAM initialization sequence As the MRS command uses an external address bus no other external devices can be accessed until the command execution is finished To access any external device other than the SDRAM immediately after executing the ...

Page 528: ... refreshed while in those modes In that case confirm that SDRSRM D6 0x39FFCA 0 i e that the SDRAM is in self refresh mode before executing the HALT or SLP instruction If an access to the SDRAM occurs while being self refreshed the SDRAM is taken out of self refresh mode thus always make sure the SDRAM check and the HALT SLP instruction execution are performed from devices other than the SDRAM 4 Do...

Page 529: ...1 0x30 ld h r0 r1 SDRAM Controller REG setting part area13 0x2000000 0x2FFFFFF 16MB area14 0x3000000 0x3FFFFFF 16MB SDRAM area configuration register note 1 xld w r0 0x39FFC0 xld w r1 0x88 set area13 to SDRAM area SDCE0 CE13 available ld b r0 r1 16MB area available SDRAM control register xld w r0 0x39FFC1 xld w r1 0xff SDRAM self refresh disable initial sequence PRE REF MRS ld b r0 r1 Little endia...

Page 530: ...N add r2 0x1 SDRAM signal enable waiting loop cmp r2 r3 jrne SDRAM_SIGNAL_EN SDRAM power up bset r0 0x6 set SDRINI D6 0x39FFC1 POWER_UP btst r1 0x7 SDRAM power up waiting loop jrne POWER_UP end of SDRAM access configuration ret The SDRAM can be accessed after executing the above program Example of initialization routine for 4M words 16 bits 4 banks 32MB of SDRAM When using a 32MB SDRAM modify two ...

Page 531: ...S1C33L03 FUNCTION PART VII LCD CONTROLLER BLOCK ...

Page 532: ......

Page 533: ...oller Block Pads PERI_PAD Pads C33_PERI Prescaler 8 bit timer 16 bit timer Clock timer Serial interface Ports C33 Peripheral Block C33 Analog Block C33_CORE CPU BCU ITC CLG DBG C33_ADC A D converter C33 Internal Memory Block Internal RAM Area 0 Internal ROM Area 10 C33 DMA Block C33_DMA IDMA HSDMA C33_SDRAMC SDRAM interface C33_LCDC LCD panel interface C33 SDRAM Controller Block Figure 1 1 LCD Con...

Page 534: ...VII LCD CONTROLLER BLOCK INTRODUCTION B VII 1 2 EPSON S1C33L03 FUNCTION PART THIS PAGE IS BLANK ...

Page 535: ...possible in up to 16 shades of gray when a monochrome passive LCD panel is used 1 bpp mode Two shade display using a 2 4 bit look up table 2 bpp mode Four shade display using a 4 4 bit look up table 4 bpp mode 16 shade display using a 16 4 bit look up table Of 4 096 colors a maximum of 256 colors can be simultaneously displayed on a color passive LCD panel 1 bpp mode Two color display using three ...

Page 536: ...wer save DOZE mode suitable for Epson s self refresh type LCD panels The status of the LCD controller can be checked using the power save status bit Other Inverse display under software control Software power save mode LCD panel power down sequence supported LCD power supply control ...

Page 537: ... in from the display frame buffer by means of a DMA transfer Address generator This generates the memory addresses for the display data to be taken in by means of a DMA transfer FIFO This is a 16 16 bit FIFO used to write data into the display frame buffer and look up table Look up table This consists of three 16 4 bit palettes red green and blue During grayscale display mode the grayscale data to...

Page 538: ...us release request input Area 6 chip enable GPIO1 P35 BUSACK I O GPIO1 See Control of GPIO pins I O port Acknowledge output for bus release request GPIO2 P31 BUSGET GARD I O GPIO2 See Control of GPIO pins I O port Bus status monitor signal output for bus release request GA area read signal output Table 2 2 Pin Configurations by Type of LCD Panel Monochrome passive panel Color passive panel Pin nam...

Page 539: ...oller are described below Selecting the area Use the VRAMAR D7 LCDC system control register 0x39FFFD to select the area to be used as the display memory VRAMAR 1 Area 8 CEFUNC 00 or area 14 CEFUNC 01 VRAMAR 0 Area 7 CEFUNC 00 or area 13 CEFUNC 01 default SRAM settings When using SRAM as the display memory set the interface method for access from the LCD controller A0 BSL and the number of wait cyc...

Page 540: ...12E 1 This enables an external bus master 2 LCDEN D5 LCDC mode register 2 0x39FFE3 1 This enables the LCD controller 3 CFP3 5 4 D 5 4 P3 function select register 0x402DC 11 This sets the P35 pin as the BUSACK output and the P34 pin as the BUSREQ input 4 Initializing the LCDC registers Setup the LCDC register as necessary except for the look up table registers 0x39FFF5 0x39FFF7 as necessary 5 LPSAV...

Page 541: ...r is 25 MHz The BCU clock divide ratios can be set using the LCLKSEL 2 0 D 2 0 FIFO control register 0x39FFF4 as shown in Table 2 3 below LCLKSEL 2 0 X2SPD pin To CPU CPU_CLK BCU_CLK Bus clock LCDC clock PCLK MCLK BCU CLG 1 1 or 1 2 1 1 1 2 1 3 1 4 Figure 2 3 LCDC Clocks Table 2 3 Selection of LCDC Clocks LCLKSEL2 LCLKSEL1 LCLKSEL0 LCDC clock 0 0 0 Turned off 0 0 1 Turned off 0 1 0 Turned off 0 1 ...

Page 542: ...Selection of the LCD Panel LDCOLOR LDDW1 LDDW0 LCD panel 0 Mono Single 4 bit passive LCD 0 1 Mono Single 8 bit passive LCD 0 Reserved 0 1 1 Reserved 0 Color Single 4 bit passive LCD 0 1 Color Single 8 bit passive LCD format 1 0 Reserved 1 1 1 Color Single 8 bit passive LCD format 2 Resolution Set the resolution of the LCD panel in accordance with the procedure specified below Horizontal resolution...

Page 543: ... later one each for bits 0 and 1 For color LCD panels two colors from among the 4 096 colors available can be set in advance using two entries for pixel data 0 and 1 in each of the red green and blue look up tables Data for eight consecutive pixels is stored as one byte in the display memory A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 P0 P1 P2 P3 P4 P5 P6 P7 P8 Display memory Pn An LCD p...

Page 544: ...he display memory A0 B0 C0 D0 A1 B1 C1 D1 A2 B2 C2 D2 A3 B3 C3 D3 A4 B4 C4 D4 A5 B5 C5 D5 P0 P1 P2 P3 P4 P5 P6 P7 Pn An Bn Cn Dn Byte 0 Byte 1 Byte 2 Display memory LCD panel bit 7 bit 0 Figure 2 6 Data Format in 4 bpp Mode 4 8 bpp 256 color mode One pixel is represented by 8 bits displayed in 256 colors This mode is not available for grayscale display In this mode 256 discrete combinations are co...

Page 545: ...15 4 bit luminance data Pixel data 4 bit display data G or Gray Green look up table 0 1 2 3 14 15 4 bit luminance data Pixel data 4 bit display data B Blue look up table 0 1 2 3 14 15 Figure 2 8 Configuration of the Look up Tables The pixel data in the display memory is used as an index to the look up tables so that luminance data is generated based on the values in the entries indicated by the pi...

Page 546: ...le data for pixel data 0 4 bit grayscale data for pixel data 1 Figure 2 9 Look up Table in 1 bpp 2 Gray Level Mode Table 2 6 shows an example of the basic data setting Table 2 6 Example of Look up Table Settings in 1 bpp 2 Gray Level Mode Index R look up table G look up table B look up table 0 0 0 0 1 0 0xF 0 2 15 0 0 0 2 2 bpp 4 gray level mode Use the first four entries of the green look up tabl...

Page 547: ...data for pixel data 0x2 4 bit grayscale data for pixel data 0xF 4 bit grayscale data for pixel data 0xE 4 bit grayscale data for pixel data 0x3 4 bit pixel data 0x0 0x1 0x2 0x3 0xE 0xF 4 bit display data Green look up table Index 0 1 2 3 14 15 Figure 2 11 Look up Table in 4 bpp 16 Gray Level Mode Table 2 8 shows an example of the basic data setting Table 2 8 Example of Look up Table Settings in 4 ...

Page 548: ... to the look up tables The differences in configurations between display modes are shown below 1 1 bpp 2 color mode Use the first two entries of each look up table Select 2 color data from among the 4 096 colors and write it to the respective entries The RGB data in entry 0 is output for pixel data 0 and the RGB data in entry 1 is output for pixel data 1 For monochrome display write 0x0 to entry 0...

Page 549: ...t R display data Red look up table Index Unused 0 1 2 3 4 15 4 bit G data for pixel data 00 4 bit G data for pixel data 01 4 bit G data for pixel data 10 4 bit G data for pixel data 11 4 bit G display data Green look up table Index Unused 0 1 2 3 4 15 4 bit B data for pixel data 00 4 bit B data for pixel data 01 4 bit B data for pixel data 10 4 bit B data for pixel data 11 4 bit B display data Blu...

Page 550: ... data 0x1 4 bit G data for pixel data 0x2 4 bit G data for pixel data 0xF 4 bit G data for pixel data 0xE 4 bit G data for pixel data 0x3 4 bit G display data Green look up table Index 0 1 2 3 14 15 4 bit B data for pixel data 0x0 4 bit B data for pixel data 0x1 4 bit B data for pixel data 0x2 4 bit B data for pixel data 0xF 4 bit B data for pixel data 0xE 4 bit B data for pixel data 0x3 4 bit B d...

Page 551: ...data for G pixel data 100 4 7 4 bit G data for G pixel data 110 4 bit G data for G pixel data 101 4 bit G data for G pixel data 011 3 bit G pixel data 000 001 010 011 100 101 110 111 4 bit G display data Green look up table Index 0 1 2 3 5 6 4 bit B data for B pixel data 00 4 bit B data for B pixel data 01 4 bit B data for B pixel data 10 4 bit B data for B pixel data 11 2 bit B pixel data 00 01 1...

Page 552: ...ok up table data register 0x39FFF7 The data corresponds to the 4 high order bits of the register Write 0 to the 4 low order bits of the register For grayscale mode write 0x0 to this register Writing any value to this register moves the internal pointer to the next entry G 0 The pointer moves in the following order each time data is written R 0 G 0 B 0 R 1 G 1 B 1 When the index address changes the...

Page 553: ...e after it has finished displaying all pixels in one line Set a value in 8 pixel units in the HNDP 4 0 D 4 0 horizontal non display period register 0x39FFE7 Horizontal non display period HNDP 4 0 4 8 Ts The value HDP described above plus HNDP comprises the number of PCLK clock cycles per one line period FPLINE pulse period VDP Vertical display period This is the LCD panel s vertical resolution num...

Page 554: ... FPSMASK has no effect MOD rate The period during which the MOD signal is switched can be set using the MODRATE 5 0 D 5 0 MOD rate register 0x39FFEB MODRATE 0x0 MOD signal switched at a period of the FPFRAME signal default MODRATE other than 0x0 Switched at a period of MODRATE 1 FPLINE pulses Repeating of the FRM pattern This setup item is provided for EL panels Whether the frame rate modulation p...

Page 555: ... and start displaying data The LCD panel is placed in power save mode with all LCD signal output pins fixed low The LCDPWR signal is also fixed low and the power to the LCD panel does not turn on To change the LCD controller from power save mode back into normal mode set LPSAVE 1 0 D 1 0 LCDC mode register 2 0x39FFE3 to 0b11 The LCD controller starts a power up sequence from that point and outputs...

Page 556: ...wer to the LCD panel turns off 2 Allow for a wait time until LCD signals are deasserted To set the wait time in terms of the number of frames count the occurrences of VNDPF 1 vertical non display period 3 Set power save mode a specified length of time later LPSAVE 0b00 4 LCD signals are deasserted a one frame period after step 3 Reading Writing Display Data The LCD controller contains an exclusive...

Page 557: ...119 and screen 2 consisting of lines 120 239 In the initial state S1VSIZE 9 0 is set to 0 As a result screen 1 is nonexistent and screen 2 is displayed over the entire panel To display only screen 1 set the same value in S1VSIZE 9 0 as that set in the LDVSIZE 9 0 D 9 0 vertical panel size register 0x39FFE6 0x39FFE5 The entire screen can be changed instantaneously to different images by switching b...

Page 558: ...allows the view port to be moved horizontally panned by an amount equal to the offset by changing the screen 1 start address register The values set in the screen 1 start address register are halfword addresses Therefore the view port is moved in 16 pixel units in 1 bpp mode in 8 pixel units in 2 bpp mode in 4 pixel units in 4 bpp mode and in 2 pixel units in 8 bpp mode Movement of the virtual scr...

Page 559: ...rmance two types of portrait modes default and alternate portrait modes are available Default portrait mode Although inferior to alternate portrait mode in terms of display performance default portrait mode is superior in terms of current consumption as it enables the use of a slower clock In this mode the horizontal size of images must be increased by the power of 2 To display a horizontal 240 pi...

Page 560: ...rait display on a small LCD panel If the pixel clock frequency is changed here the frame rate must be reviewed including resetting of the non display period parameters Table 2 14 Clock Settings for Default Portrait Mode PMODCLK1 PMODCLK0 Pixel clock PCLK Memory clock MCLK 0 0 CLK CLK 0 1 CLK 2 CLK 2 1 0 CLK 4 CLK 4 1 1 CLK 8 CLK 8 CLK denotes the LCDC clock selected using the LCLKSEL 2 0 D 2 0 FIF...

Page 561: ...e If switched over without clearing the display memory the display may be distorted for a certain period 3 If the LCD panel was split into two screens in landscape mode reset the S1VSIZE 9 0 D 9 0 screen 1 vertical size register 0x39FFF2 by setting a new value above the vertical resolution of the LCD panel in it In portrait mode the LCD panel cannot be split for display on screen 2 4 Write a portr...

Page 562: ...ress register In alternate portrait mode the screen can be scrolled in the vertical direction one line at a time Comparison of portrait modes The differences between default portrait mode and alternate portrait mode are summarized in Table 2 16 Table 2 16 Differences between Portrait Modes Parameter Default portrait mode Alternate portrait mode Display memory Sufficient display memory must be avai...

Page 563: ...out of power save mode by setting LPSAVE to 11 thereby executing a power up sequence The LCD signal output is enabled and the LCDPWR signal goes high a one frame period after power save mode is released The above power up power down sequences can be controlled with a user s desired timing by using LPWREN D4 LCDC mode register 2 0x39FFE3 For details on the control procedure refer to Controlling LCD...

Page 564: ...D is set to 0 default bus release requests from outside will no longer be accepted while LCDCEN 1 As a result the pins listed below will not be used for bus release purposes and can therefore be used as general purpose input output GPIO pins Because these pins are usable only while the LCD controller remains enabled the control registers in the LCD controller block must be used to control their di...

Page 565: ...0 when being read 0 when being read 039FFE2 B 1 Repeated 0 Not repeated 1 Inverted 0 Normal 1 Blank 0 Normal LCDC mode register 1 1 1 0 0 1 0 1 0 BPP 1 0 Mode 8 bpp 4 bpp 2 bpp 1 bpp LCDCEN LPWREN LPSAVE1 LPSAVE0 D7 6 D5 D4 D3 2 D1 D0 reserved LCD controller enable LCDPWR enable reserved Power save mode 0 0 0 0 R W R W R W 0 when being read 0 when being read 039FFE3 B 1 Enabled 0 Disabled 1 Enable...

Page 566: ...3 D2 D1 D0 Screen 1 start address high order 8 bits 0 0 0 0 0 0 0 0 R W 039FFED B Screen 1 start address register 1 S2ADDR7 S2ADDR6 S2ADDR5 S2ADDR4 S2ADDR3 S2ADDR2 S2ADDR1 S2ADDR0 D7 D6 D5 D4 D3 D2 D1 D0 Screen 2 start address low order 8 bits 0 0 0 0 0 0 0 0 R W 039FFEE B Screen 2 start address register 0 S2ADDR15 S2ADDR14 S2ADDR13 S2ADDR12 S2ADDR11 S2ADDR10 S2ADDR9 S2ADDR8 D7 D6 D5 D4 D3 D2 D1 D...

Page 567: ...039FFF8 B GPIO configuration register 1 Output 0 Input 1 Output 0 Input 1 Output 0 Input GPO6D GPO5D GPO4D GPO3D GPIO2D GPIO1D GPIO0D D7 D6 D5 D4 D3 D2 D1 D0 reserved GPO6 data GPO5 data GPO4 data GPO3 data GPIO2 data GPIO1 data GPIO0 data 0 0 0 0 0 0 0 R W R W R W R W R W R W R W 0 when being read 039FFF9 B GPIO status control register 1 High 0 Low 1 High 0 Low 1 High 0 Low 1 High 0 Low 1 High 0 ...

Page 568: ...e select D5 LCDC mode register 0 0x39FFE1 Selects the type of connected LCD panel color or monochrome Write 1 Color panel Write 0 Monochrome panel Read Valid Setting LDCOLOR to 1 selects a color panel drive method and setting it to 0 selects a monochrome panel drive method At initial reset LDCOLOR is set to 0 monochrome panel FPSMASK Mask FPSHIFT signal D2 LCDC mode register 0 0x39FFE1 Selects the...

Page 569: ... modulation pattern effective only for EL panels Write 1 Repeated Write 0 Not repeated Read Valid When FRMRPT is set to 1 the internal 19 bit frame counter is enabled and starts counting the number of frames Each time this counter overflows 0x40000 0 the frame rate modulation pattern is repeated When FRMRPT is set to 0 the counter is disabled and the frame rate modulation pattern is not repeated A...

Page 570: ... panel size register 0x39FFE4 Sets the horizontal resolution of the LCD panel in 16 pixel units Set the value obtained using the equation below Horizontal resolution in pixels LDHSIZE 5 0 1 16 For an LCD panel with a horizontal resolution of 320 dots for example set 19 0x13 in LDHSIZE Do not set any value less than 1 in this register At initial reset LDHSIZE is set to 0x0 LDVSIZE 9 0 Vertical pane...

Page 571: ... any number of lines less than the LCD panel s vertical resolution LDVSIZE 9 0 is set in this register the LCD panel is divided into an upper half from line 1 to line S1VSIZE 1 as screen 1 and a lower half from that line down as screen 2 When the screen is not to be divided set any value equal to or greater than LDVSIZE in this register so that only screen 1 will be displayed At initial reset S1VS...

Page 572: ... must always be accessed bytewise for both reading and writing At initial reset LUTADDR is set to 0x0 entry 0 in the red look up table LUTDT 3 0 LUT data D 7 4 Look up table data register 0x39FFF7 Use this register to read or write to the look up tables Each time this register is accessed the look up table pointer changes in the order shown below provided that the look up table address register is...

Page 573: ...data D3 GPIO status control register 0x39FFF9 Sets the data to be output from the GPO 6 3 pins Write 1 High level Write 0 Low level Read Valid Writing 1 to GPOxD drives the GPOx pin high and writing 0 drives the GPOx pin low The GPO 6 3 pins are shared with the LCD signal output pins listed below These pins can only be used for general purpose output when a 4 bit LCD panel is selected GPO6 FPDAT3 ...

Page 574: ... MCLK which is selected by LCLKSEL 2 0 D 2 0 0x39FFF4 At initial reset PMODCLK is set to 0b00 PMODLBC 7 0 Line byte count D 7 0 Line byte count register 0x39FFFC Sets the number of bytes equivalent to one line in portrait mode For this line byte count write the number of horizontal pixels converted into the number of bytes available in bpp mode These horizontal pixels include the number of pixels ...

Page 575: ...ces even while the LCD controller is in use While the bus is being used by one of these external devices the LCD controller cannot access the display memory and therefore cannot update the display Setting BREQEN to 0 disables bus release requests from external devices only while the LCD controller is in use LCDCEN 1 At initial reset BREQEN is set to 0 disabled LCDCST A0 BSL select D1 LCDC system c...

Page 576: ...controller and the LCD panel to which the LCD controller is connected Therefore make sure data is never written to that location Precautions on Using ICD33 Follow the precautions described below when using the ICD33 S5U1C33000H for debugging an application which uses this LCD controller 1 When WAIT is enabled do not dump including displays using the Memory window or set the contents from to the LC...

Page 577: ... area6 access control register xld w r1 0xff00 ld h r5 r1 xld w r5 0x4813a select bclk output xld w r1 0x01 ld b r5 r1 xld w r1 0x39ffe3 lcd enable xld w r2 0x20 ld b r1 r2 xld w r5 0x402dc set busack req wait xld w r1 0x30 ld b r5 r1 test color 4 8bit 1 2 4 8 bpp video invert segment common landscape mode virtual image display blank set landscape mode color 8bit 8bpp segment32 x 3 xld w r1 0x39ff...

Page 578: ...ffee set S2 start address 5555 xld w r2 0x0000 ld h r1 r2 xld w r1 0x39fff1 set Memory address offset 00 xld w r2 0x00 ld b r1 r2 xld w r1 0x39fff2 set S1 Vertical size 0x01df lsb xld w r2 0x0100 ld h r1 r2 xld w r1 0x39fff4 set clk osc3 fifo 0 xld w r2 0x04 ld b r1 r2 xld w r1 0x39ffe3 LCD power on xld w r2 0x23 ld b r1 r2 Initialize the LUT xld w r1 0x39fff5 set lut address xld w r2 0x39fff7 xld...

Page 579: ...S1C33L03 FUNCTION PART Appendix I O MAP ...

Page 580: ......

Page 581: ... 1 0 Divided clk 1 θ 1 0 Divided clk 1 θ 1 0 Divided clk 8 bit timer clock select register P16TON0 P16TS02 P16TS01 P16TS00 D7 4 D3 D2 D1 D0 reserved 16 bit timer 0 clock control 16 bit timer 0 clock division ratio selection 0 0 0 0 R W R W 0 when being read θ selected by Prescaler clock select register 0x40181 16 bit timer 0 can be used as a watchdog timer 0040147 B 1 On 0 Off 1 1 1 1 0 0 0 0 1 1 ...

Page 582: ... D3 D2 D1 D0 reserved 16 bit timer 5 clock control 16 bit timer 5 clock division ratio selection 0 0 0 0 R W R W 0 when being read θ selected by Prescaler clock select register 0x40181 004014C B 1 On 0 Off 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 P16TS5 2 0 Division ratio θ 4096 θ 1024 θ 256 θ 64 θ 16 θ 4 θ 2 θ 1 16 bit timer 5 clock control register 1 On 0 Off P8TON1 P8TS12 P8TS11 P8TS10 P...

Page 583: ...ion ratio θ 256 θ 128 θ 64 θ 32 θ 16 θ 8 θ 4 θ 2 TCRST TCRUN D7 2 D1 D0 reserved Clock timer reset Clock timer Run Stop control X X W R W 0 when being read 0 when being read 0040151 B 1 Reset 0 Invalid 1 Run 0 Stop Clock timer Run Stop register TCISE2 TCISE1 TCISE0 TCASE2 TCASE1 TCASE0 TCIF TCAF D7 D6 D5 D4 D3 D2 D1 D0 Clock timer interrupt factor selection Clock timer alarm factor selection Inter...

Page 584: ...ter 0 to 65535 days high order 8 bits X X X X X X X X R W TCND15 TCND14 TCND13 TCND12 TCND11 TCND10 TCND9 TCND8 D7 D6 D5 D4 D3 D2 D1 D0 Clock timer day counter data high order 8 bits TCND15 MSB 0040158 B Clock timer day high order register 0 to 59 minutes Note Can be set within 0 63 TCCH5 TCCH4 TCCH3 TCCH2 TCCH1 TCCH0 D7 6 D5 D4 D3 D2 D1 D0 reserved Clock timer minute comparison data TCCH5 MSB TCC...

Page 585: ... read 0 when being read 0040164 B 1 On 0 Off 1 Preset 0 Invalid 1 Run 0 Stop 8 bit timer 1 control register 0 to 255 RLD17 RLD16 RLD15 RLD14 RLD13 RLD12 RLD11 RLD10 D7 D6 D5 D4 D3 D2 D1 D0 8 bit timer 1 reload data RLD17 MSB RLD10 LSB X X X X X X X X R W 0040165 B 8 bit timer 1 reload data register 0 to 255 PTD17 PTD16 PTD15 PTD14 PTD13 PTD12 PTD11 PTD10 D7 D6 D5 D4 D3 D2 D1 D0 8 bit timer 1 count...

Page 586: ... 0 when being read 0040174 B 1 On 0 Off 1 Preset 0 Invalid 1 Run 0 Stop 8 bit timer 4 control register 0 to 255 RLD47 RLD46 RLD45 RLD44 RLD43 RLD42 RLD41 RLD40 D7 D6 D5 D4 D3 D2 D1 D0 8 bit timer 4 reload data RLD47 MSB RLD40 LSB X X X X X X X X R W 0040175 B 8 bit timer 4 reload data register 0 to 255 PTD47 PTD46 PTD45 PTD44 PTD43 PTD42 PTD41 PTD40 D7 D6 D5 D4 D3 D2 D1 D0 8 bit timer 4 counter da...

Page 587: ...etting Init R W Remarks WRWD D7 D6 0 EWD write protection 0 R W 0 when being read 0040170 B 1 Write enabled 0 Write protect Watchdog timer write protect register EWD D7 2 D1 D0 Watchdog timer enable 0 R W 0 when being read 0 when being read 0040171 B 1 NMI enabled 0 NMI disabled Watchdog timer enable register ...

Page 588: ...Power control register PSCDT0 D7 1 D0 reserved Prescaler clock selection 0 0 R W 0040181 B Prescaler clock select register 1 OSC1 0 OSC3 PLL HLT2OP 8T1ON PF1ON D7 4 D3 D2 D1 D0 HALT clock option OSC3 stabilize waiting function reserved OSC1 external output control 0 1 0 0 R W R W R W 0 when being read Do not write 1 0040190 B 1 On 0 Off 1 Off 0 On 1 On 0 Off Clock option register Writing 10010110 ...

Page 589: ...01E2 B 1 Error 0 Normal 1 Transmitting 0 End 1 Error 0 Normal 1 Error 0 Normal 1 Empty 0 Buffer full 1 Buffer full 0 Empty Serial I F Ch 0 status register TXEN0 RXEN0 EPR0 PMD0 STPB0 SSCK0 SMD01 SMD00 D7 D6 D5 D4 D3 D2 D1 D0 Ch 0 transmit enable Ch 0 receive enable Ch 0 parity enable Ch 0 parity mode selection Ch 0 stop bit selection Ch 0 input clock selection Ch 0 transfer mode selection 1 1 0 0 ...

Page 590: ...ynchronous Clock sync Slave Clock sync Master 0 0 X X X X X X R W R W R W R W R W R W R W Valid only in asynchronous mode 00401E8 B Serial I F Ch 1 control register 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 SCLK1 0 Internal clock DIVMD1 IRTL1 IRRL1 IRMD11 IRMD10 D7 5 D4 D3 D2 D1 D0 Ch 1 async clock division ratio Ch 1 IrDA I F output logic ...

Page 591: ...4 D3 D2 D1 D0 Serial I F Ch 3 receive data RXD37 36 MSB RXD30 LSB X X X X X X X X R 00401F6 B Serial I F Ch 3 receive data register TEND3 FER3 PER3 OER3 TDBE3 RDBF3 D7 6 D5 D4 D3 D2 D1 D0 reserved Ch 3 transmit completion flag Ch 3 flaming error flag Ch 3 parity error flag Ch 3 overrun error flag Ch 3 transmit data buffer empty Ch 3 receive data buffer full 0 0 0 0 1 0 R R W R W R W R R 0 when bei...

Page 592: ...D2 AD1 AD0 0 0 0 0 0 0 R W R W R 0 when being read 0040242 B 1 Continuous 0 Normal A D trigger register 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 CE 2 0 End channel AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 CS 2 0 Start channel AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 CE2 CE1 CE0 CS2 CS1 CS0 D7 6 D5 D4 D3 D2 D1 D0 A D converter end channel selection A D converter...

Page 593: ...0 when being read 0040263 B High speed DMA Ch 0 1 interrupt priority register 0 to 7 0 to 7 PHSD3L2 PHSD3L1 PHSD3L0 PHSD2L2 PHSD2L1 PHSD2L0 D7 D6 D5 D4 D3 D2 D1 D0 reserved High speed DMA Ch 3 interrupt level reserved High speed DMA Ch 2 interrupt level X X X X X X R W R W 0 when being read 0 when being read 0040264 B High speed DMA Ch 2 3 interrupt priority register 0 to 7 PDM2 PDM1 PDM0 D7 3 D2 ...

Page 594: ...X X R W R W 0 when being read 0 when being read 004026A B Serial I F Ch 1 A D interrupt priority register 0 to 7 PCTM2 PCTM1 PCTM0 D7 3 D2 D1 D0 reserved Clock timer interrupt level X X X R W Writing 1 not allowed 004026B B Clock timer interrupt priority register 0 to 7 0 to 7 PP5L2 PP5L1 PP5L0 PP4L2 PP4L1 PP4L0 D7 D6 D5 D4 D3 D2 D1 D0 reserved Port input 5 interrupt level reserved Port input 4 in...

Page 595: ... 0 R W R W R W R W 0 when being read 0 when being read 0040273 B 1 Enabled 0 Disabled 16 bit timer 2 3 interrupt enable register 1 Enabled 0 Disabled E16TC5 E16TU5 E16TC4 E16TU4 D7 D6 D5 4 D3 D2 D1 0 16 bit timer 5 comparison A 16 bit timer 5 comparison B reserved 16 bit timer 4 comparison A 16 bit timer 4 comparison B reserved 0 0 0 0 R W R W R W R W 0 when being read 0 when being read 0040274 B ...

Page 596: ... read 0040283 B 1 Factor is generated 0 No factor is generated 16 bit timer 2 3 interrupt factor flag register 1 Factor is generated 0 No factor is generated F16TC5 F16TU5 F16TC4 F16TU4 D7 D6 D5 4 D3 D2 D1 0 16 bit timer 5 comparison A 16 bit timer 5 comparison B reserved 16 bit timer 4 comparison A 16 bit timer 4 comparison B reserved X X X X R W R W R W R W 0 when being read 0 when being read 00...

Page 597: ...W R W R W 0 when being read 0040293 B 1 IDMA request 0 Interrupt request 1 IDMA request 0 Interrupt request Serial I F Ch 1 A D port input 4 7 IDMA request register DE16TC0 DE16TU0 DEHDM1 DEHDM0 DEP3 DEP2 DEP1 DEP0 D7 D6 D5 D4 D3 D2 D1 D0 16 bit timer 0 comparison A 16 bit timer 0 comparison B High speed DMA Ch 1 High speed DMA Ch 0 Port input 3 Port input 2 Port input 1 Port input 0 0 0 0 0 0 0 0...

Page 598: ... speed DMA Ch 2 trigger set up 0 0 0 0 0 0 0 0 R W R W 0040299 B 0 1 2 3 4 5 6 7 8 9 A B C Software trigger K54 input falling edge K54 input rising edge Port 3 input Port 7 input 8 bit timer Ch 3 underflow 16 bit timer Ch 3 compare B 16 bit timer Ch 3 compare A 16 bit timer Ch 5 compare B 16 bit timer Ch 5 compare A SI F Ch 1 Rx buffer full SI F Ch 1 Tx buffer empty A D conversion completion 0 1 2...

Page 599: ...port data R R R R R 0 when being read 00402C1 B 1 High 0 Low K5 input port data register CFK67 CFK66 CFK65 CFK64 CFK63 CFK62 CFK61 CFK60 D7 D6 D5 D4 D3 D2 D1 D0 K67 function selection K66 function selection K65 function selection K64 function selection K63 function selection K62 function selection K61 function selection K60 function selection 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W 00402C3...

Page 600: ...PPT6 SPPT5 SPPT4 SPPT3 SPPT2 SPPT1 SPPT0 D7 D6 D5 D4 D3 D2 D1 D0 FPT7 input polarity selection FPT6 input polarity selection FPT5 input polarity selection FPT4 input polarity selection FPT3 input polarity selection FPT2 input polarity selection FPT1 input polarity selection FPT0 input polarity selection 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W 00402C8 B Port input interrupt input polarity s...

Page 601: ...W R W R W R W R W R W R W R W Extended functions 0x402DF 00402D0 B 1 SRDY1 0 P07 1 SCLK1 0 P06 1 SOUT1 0 P05 1 SIN1 0 P04 1 SRDY0 0 P03 1 SCLK0 0 P02 1 SOUT0 0 P01 1 SIN0 0 P00 P0 function select register P07D P06D P05D P04D P03D P02D P01D P00D D7 D6 D5 D4 D3 D2 D1 D0 P07 I O port data P06 I O port data P05 I O port data P04 I O port data P03 I O port data P02 I O port data P01 I O port data P00 I...

Page 602: ... port data register IOC27 IOC26 IOC25 IOC24 IOC23 IOC22 IOC21 IOC20 D7 D6 D5 D4 D3 D2 D1 D0 P27 I O control P26 I O control P25 I O control P24 I O control P23 I O control P22 I O control P21 I O control P20 I O control 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W This register indicates the values of the I O control signals of the ports when it is read See detailed explanation 00402DA B 1 Outp...

Page 603: ...eserved Areas 16 15 device size selection Areas 16 15 output disable delay time reserved Areas 16 15 wait control 1 8 bits 0 16 bits 1 8 bits 0 16 bits 0 1 1 1 1 1 0 1 1 1 1 1 R W R W R W R W R W R W 0 when being read 0 when being read 0 when being read 0 when being read 0048120 HW Areas 18 15 set up register 1 1 0 0 1 0 1 0 A18DF 1 0 Number of cycles 3 5 2 5 1 5 0 5 1 1 0 0 1 0 1 0 A16DF 1 0 Numb...

Page 604: ...as 10 9 output disable delay time reserved Areas 10 9 wait control 1 Used 0 Not used 1 Used 0 Not used 1 8 bits 0 16 bits 1 1 1 0 0 0 0 0 1 1 1 1 1 R W R W R W R W R W R W R W 0 when being read 0 when being read 0 when being read 0048126 HW 1 1 0 0 1 0 1 0 A10BW 1 0 Wait cycles 3 2 1 0 1 1 0 0 1 0 1 0 A10DF 1 0 Number of cycles 3 5 2 5 1 5 0 5 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 A10IR ...

Page 605: ...D6 D5 D4 D3 D2 D1 D0 TTBR register write protect 0 0 0 0 0 0 0 0 W Undefined in read 004812D B Writing 01011001 0x59 removes the TTBR 0x48134 write protection Writing other data sets the write protection TTBR write protect register RBCLK RBST8 REDO RCA1 RCA0 RPC2 RPC1 RPC0 RRA1 RRA0 SBUSST SEMAS SEPD SWAITE DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BCLK output control reserved Burst ROM burs...

Page 606: ...external access Area 16 15 internal external access Area 14 13 internal external access Area 12 11 internal external access reserved Area 8 7 internal external access Area 6 internal external access Area 5 4 internal external access Area 18 17 endian control Area 16 15 endian control Area 14 13 endian control Area 12 11 endian control Area 10 9 endian control Area 8 7 endian control Area 6 endian ...

Page 607: ... Area 5 4 address strobe signal Area 18 17 read signal Area 16 15 read signal Area 14 13 read signal Area 12 11 read signal reserved Area 8 7 read signal Area 6 read signal Area 5 4 read signal 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 when being read 0 when being read 0048138 HW G A read signal control register 1 Enabled 0 Disabled 1 Enabled 0 Disab...

Page 608: ...182 HW 16 bit timer 0 comparison register B 0 to 65535 TC015 TC014 TC013 TC012 TC011 TC010 TC09 TC08 TC07 TC06 TC05 TC04 TC03 TC02 TC01 TC00 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 bit timer 0 counter data TC015 MSB TC00 LSB X X X X X X X X X X X X X X X X R 0048184 HW 16 bit timer 0 counter data register SELFM0 SELCRB0 OUTINV0 CKSL0 PTM0 PRESET0 PRUN0 D7 D6 D5 D4 D3 D2 D1 D0 reserved 1...

Page 609: ... 004818A HW 16 bit timer 1 comparison register B 0 to 65535 TC115 TC114 TC113 TC112 TC111 TC110 TC19 TC18 TC17 TC16 TC15 TC14 TC13 TC12 TC11 TC10 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 bit timer 1 counter data TC115 MSB TC10 LSB X X X X X X X X X X X X X X X X R 004818C HW 16 bit timer 1 counter data register SELFM1 SELCRB1 OUTINV1 CKSL1 PTM1 PRESET1 PRUN1 D7 D6 D5 D4 D3 D2 D1 D0 reser...

Page 610: ...192 HW 16 bit timer 2 comparison register B 0 to 65535 TC215 TC214 TC213 TC212 TC211 TC210 TC29 TC28 TC27 TC26 TC25 TC24 TC23 TC22 TC21 TC20 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 bit timer 2 counter data TC215 MSB TC20 LSB X X X X X X X X X X X X X X X X R 0048194 HW 16 bit timer 2 counter data register SELFM2 SELCRB2 OUTINV2 CKSL2 PTM2 PRESET2 PRUN2 D7 D6 D5 D4 D3 D2 D1 D0 reserved 1...

Page 611: ... 004819A HW 16 bit timer 3 comparison register B 0 to 65535 TC315 TC314 TC313 TC312 TC311 TC310 TC39 TC38 TC37 TC36 TC35 TC34 TC33 TC32 TC31 TC30 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 bit timer 3 counter data TC315 MSB TC30 LSB X X X X X X X X X X X X X X X X R 004819C HW 16 bit timer 3 counter data register SELFM3 SELCRB3 OUTINV3 CKSL3 PTM3 PRESET3 PRUN3 D7 D6 D5 D4 D3 D2 D1 D0 reser...

Page 612: ...1A2 HW 16 bit timer 4 comparison register B 0 to 65535 TC415 TC414 TC413 TC412 TC411 TC410 TC49 TC48 TC47 TC46 TC45 TC44 TC43 TC42 TC41 TC40 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 bit timer 4 counter data TC415 MSB TC40 LSB X X X X X X X X X X X X X X X X R 00481A4 HW 16 bit timer 4 counter data register SELFM4 SELCRB4 OUTINV4 CKSL4 PTM4 PRESET4 PRUN4 D7 D6 D5 D4 D3 D2 D1 D0 reserved 1...

Page 613: ... 00481AA HW 16 bit timer 5 comparison register B 0 to 65535 TC515 TC514 TC513 TC512 TC511 TC510 TC59 TC58 TC57 TC56 TC55 TC54 TC53 TC52 TC51 TC50 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 bit timer 5 counter data TC515 MSB TC50 LSB X X X X X X X X X X X X X X X X R 00481AC HW 16 bit timer 5 counter data register SELFM5 SELCRB5 OUTINV5 CKSL5 PTM5 PRESET5 PRUN5 D7 D6 D5 D4 D3 D2 D1 D0 reser...

Page 614: ... 0 1 0 0 0 0 0 R W 0048200 HW IDMA base address low order register DBASEH11 DBASEH10 DBASEH9 DBASEH8 DBASEH7 DBASEH6 DBASEH5 DBASEH4 DBASEH3 DBASEH2 DBASEH1 DBASEH0 DF C DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 reserved IDMA base address high order 12 bits Initial value 0x0C003A0 0 0 0 0 1 1 0 0 0 0 0 0 R W Undefined in read 0048202 HW IDMA base address high order register 0 to 127 DSTART DCHN D7 D6 0 ...

Page 615: ...1 Memory WR 0 Memory RD 0 0 X X X X X X X X R W R W R W Undefined in read 0048222 HW High speed DMA Ch 0 control register Note D Dual address mode S Single address mode S0ADRL15 S0ADRL14 S0ADRL13 S0ADRL12 S0ADRL11 S0ADRL10 S0ADRL9 S0ADRL8 S0ADRL7 S0ADRL6 S0ADRL5 S0ADRL4 S0ADRL3 S0ADRL2 S0ADRL1 S0ADRL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D Ch 0 source address 15 0 S Ch 0 memory address ...

Page 616: ...0ADRH2 D0ADRH1 D0ADRH0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch 0 transfer mode D Ch 0 destination address control S Invalid D Ch 0 destination address 27 16 S Invalid 0 0 0 0 X X X X X X X X X X X X R W R W R W 004822A HW High speed DMA Ch 0 high order destination address set up register Note D Dual address mode S Single address mode 1 1 0 0 1 0 1 0 D0MOD 1 0 Mode Invalid Block Successi...

Page 617: ...1 Memory WR 0 Memory RD 0 0 X X X X X X X X R W R W R W Undefined in read 0048232 HW High speed DMA Ch 1 control register Note D Dual address mode S Single address mode S1ADRL15 S1ADRL14 S1ADRL13 S1ADRL12 S1ADRL11 S1ADRL10 S1ADRL9 S1ADRL8 S1ADRL7 S1ADRL6 S1ADRL5 S1ADRL4 S1ADRL3 S1ADRL2 S1ADRL1 S1ADRL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D Ch 1 source address 15 0 S Ch 1 memory address ...

Page 618: ...1ADRH2 D1ADRH1 D1ADRH0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch 1 transfer mode D Ch 1 destination address control S Invalid D Ch 1 destination address 27 16 S Invalid 0 0 0 0 X X X X X X X X X X X X R W R W R W 004823A HW High speed DMA Ch 1 high order destination address set up register Note D Dual address mode S Single address mode 1 1 0 0 1 0 1 0 D1MOD 1 0 Mode Invalid Block Successi...

Page 619: ...1 Memory WR 0 Memory RD 0 0 X X X X X X X X R W R W R W Undefined in read 0048242 HW High speed DMA Ch 2 control register Note D Dual address mode S Single address mode S2ADRL15 S2ADRL14 S2ADRL13 S2ADRL12 S2ADRL11 S2ADRL10 S2ADRL9 S2ADRL8 S2ADRL7 S2ADRL6 S2ADRL5 S2ADRL4 S2ADRL3 S2ADRL2 S2ADRL1 S2ADRL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D Ch 2 source address 15 0 S Ch 2 memory address ...

Page 620: ...2ADRH2 D2ADRH1 D2ADRH0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch 2 transfer mode D Ch 2 destination address control S Invalid D Ch 2 destination address 27 16 S Invalid 0 0 0 0 X X X X X X X X X X X X R W R W R W 004824A HW High speed DMA Ch 2 high order destination address set up register Note D Dual address mode S Single address mode 1 1 0 0 1 0 1 0 D2MOD 1 0 Mode Invalid Block Successi...

Page 621: ...1 Memory WR 0 Memory RD 0 0 X X X X X X X X R W R W R W Undefined in read 0048252 HW High speed DMA Ch 3 control register Note D Dual address mode S Single address mode S3ADRL15 S3ADRL14 S3ADRL13 S3ADRL12 S3ADRL11 S3ADRL10 S3ADRL9 S3ADRL8 S3ADRL7 S3ADRL6 S3ADRL5 S3ADRL4 S3ADRL3 S3ADRL2 S3ADRL1 S3ADRL0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D Ch 3 source address 15 0 S Ch 3 memory address ...

Page 622: ...3ADRH2 D3ADRH1 D3ADRH0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ch 3 transfer mode D Ch 3 destination address control S Invalid D Ch 3 destination address 27 16 S Invalid 0 0 0 0 X X X X X X X X X X X X R W R W R W 004825A HW High speed DMA Ch 3 high order destination address set up register Note D Dual address mode S Single address mode 1 1 0 0 1 0 1 0 D3MOD 1 0 Mode Invalid Block Successi...

Page 623: ... reserved SDRAM page size column range reserved SDRAM row addressing range Number of SDRAM banks reserved 0 0 0 0 0 R W R W R W 0 when being read 0 when being read 0 when being read 039FFC2 B 1 4 banks 0 2 banks SDRAM address configuration register 1 1 0 0 1 0 1 0 SDRRA 1 0 Addressing range reserved 8K SDA 12 0 4K SDA 11 0 2K SDA 10 0 1 1 0 0 1 0 1 0 SDRCA 1 0 Page size reserved 1K SDA 9 0 512 SDA...

Page 624: ... D1 D0 reserved SDRAM auto refresh count 11 0 1 1 1 1 1 1 1 1 1 1 1 1 R W 0 when being read 039FFC6 HW SDRAM auto refresh count register 0 to 4096 SDRSRFC3 SDRSRFC2 SDRSRFC1 SDRSRFC0 D7 4 D3 D2 D1 D0 reserved SDRAM self refresh count 3 0 1 1 1 1 R W 0 when being read This register must not be set less than 0x02 039FFC8 B SDRAM self refresh count register 2 to 15 SDRSZ SDRBI D7 D6 D5 D4 0 reserved ...

Page 625: ...l LCDC mode register 1 1 1 0 0 1 0 1 0 BPP 1 0 Mode 8 bpp 4 bpp 2 bpp 1 bpp LCDCEN LPWREN LPSAVE1 LPSAVE0 D7 6 D5 D4 D3 2 D1 D0 reserved LCD controller enable LCDPWR enable reserved Power save mode 0 0 0 0 R W R W R W 0 when being read 0 when being read 039FFE3 B 1 Enabled 0 Disabled 1 Enabled 0 Disabled LCDC mode register 2 1 1 0 0 1 0 1 0 LPSAVE 1 0 Mode Normal operation Doze reserved Power save...

Page 626: ... Screen 1 start address high order 8 bits 0 0 0 0 0 0 0 0 R W 039FFED B Screen 1 start address register 1 S2ADDR7 S2ADDR6 S2ADDR5 S2ADDR4 S2ADDR3 S2ADDR2 S2ADDR1 S2ADDR0 D7 D6 D5 D4 D3 D2 D1 D0 Screen 2 start address low order 8 bits 0 0 0 0 0 0 0 0 R W 039FFEE B Screen 2 start address register 0 S2ADDR15 S2ADDR14 S2ADDR13 S2ADDR12 S2ADDR11 S2ADDR10 S2ADDR9 S2ADDR8 D7 D6 D5 D4 D3 D2 D1 D0 Screen 2...

Page 627: ...O configuration register 1 Output 0 Input 1 Output 0 Input 1 Output 0 Input GPO6D GPO5D GPO4D GPO3D GPIO2D GPIO1D GPIO0D D7 D6 D5 D4 D3 D2 D1 D0 reserved GPO6 data GPO5 data GPO4 data GPO3 data GPIO2 data GPIO1 data GPIO0 data 0 0 0 0 0 0 0 R W R W R W R W R W R W R W 0 when being read 039FFF9 B GPIO status control register 1 High 0 Low 1 High 0 Low 1 High 0 Low 1 High 0 Low 1 High 0 Low 1 High 0 ...

Page 628: ...CDCST LCDCEC D7 D6 D5 D4 D3 D2 D1 D0 VRAM area select VRAM wait control number of wait cycles for SRAM External DMA enable External bus request enable A0 BSL select Big little endian select 0 0 0 0 0 0 0 0 R W R W R W R W R W R W 039FFFD B 1 Area 8 0 Area 7 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 BSL 0 A0 1 Big endian 0 Little endian LCDC system control register 0 7 ...

Page 629: ...ax 34 93 544 2491 Scotland Design Center Integration House The Alba Campus Livingston West Lothian EH54 7EG SCOTLAND Phone 44 1506 605040 Fax 44 1506 605041 ASIA EPSON CHINA CO LTD 23F Beijing Silver Tower 2 North RD DongSanHuan ChaoYang District Beijing CHINA Phone 64106655 Fax 64107319 SHANGHAI BRANCH 7F High Tech Bldg 900 Yishan Road Shanghai 200233 CHINA Phone 86 21 5423 5577 Fax 86 21 5423 46...

Page 630: ...In pursuit of Saving Technology Epson electronic devices Our lineup of semiconductors displays and quartz devices assists in creating the products of our customers dreams Epson IS energy savings ...

Page 631: ...http www epsondevice com EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION Issue April 2003 Printed in Japan B L Technical Manual S1C33L03 ...

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