Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03, Technical Manual

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VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
B-VI-2-12
EPSON
S1C33L03 FUNCTION PART
SDRAM Operation
Synchronous Clock
The SDRAM controller uses the BCLK pin as it outputs the SDRAM clock.
High-speed (OSC3)
oscillation circuit
CLKCHG CLKDT[1:0]
PLLS[1:0] pins #X2SPD pin
To CPU
OSC3_CLK
PLL_CLK
A
CPU_CLK BCU_CLK
CPU_CLK
OSC3_CLK
PLL_CLK
Bus clock
PLL
Low-speed (OSC1)
oscillation circuit
CLG
BCU
1/1 or 1/2
1/1–1/8
BCLKSEL[1:0]
SDRENA
SD_CLK
SDRAMC
1/1 or 1/2
Refresh
counter
BCLK pin
Figure 2.8 SDRAM Clock System
Normally output from the BCLK pin is a clock selected with the BCU’s BCLKSEL[1:0] (D[1:0])/BCLK select
register (0x4813A) (which is, by default, the CPU clock). Before SDRAM can be used, the SDRAM clock can be
enabled for output by writing "1" to the SDRENA (D7)/SDRAM control register (0x39FFC1).
The SDRAM clock has its frequency determined by how the #X2SPD pin is set, as does the BCU operating clock
(BCU_CLK).
#X2SPD = "1": CPU–SDRAM clock ratio is set to 1 : 1. The SDRAM clock and the CPU system clock will be
the same.
#X2SPD = "0": CPU–SDRAM clock ratio is set to 2 : 1. The SDRAM clock frequency becomes half of the CPU
system clock.
While the SDRAM is self-refreshed, the SDRAM clock output can be turned off in order to reduce the chip’s
current consumption. To set this feature, use the SDRCLK (D3)/SDRAM control register (0x39FFC1).
SDRCLK = "1": The BCLK pin always outputs SDRAM clock (default).
SDRCLK = "0": The BCLK pin is fixed low while the SDRAM is self-refreshed. It is placed in the high-
impedance state while control of the bus is released.
#SDCEx
OSC3 (CPU_CLK)
BCLK (BCU_CLK)
BCLK (SD_CLK when SDRCLK = "1")
BCLK (SD_CLK when SDRCLK = "0")
SDCKE
Access to
the SDRAM
Access to other
external memory
Access to the
internal memory
When #X2SPD = "1"
Self
refresh
#SDCEx
OSC3 (CPU_CLK)
BCLK (BCU_CLK)
BCLK (SD_CLK when SDRCLK = "1")
BCLK (SD_CLK when SDRCLK = "0")
SDCKE
Access to
the SDRAM
Access to other
external memory
Access to the
internal memory
When #X2SPD = "0"
Self
refresh
Figure 2.9 SDRAM Clock Operation