EDR-3000
IM02602003E
Name
Description
SNTP.SNTP active
Signal: If there is no valid SNTP signal for 120 sec, SNTP is regarded as inactive.
Statistics.ResFc all
Signal: Resetting of all Statistic values (Current Demand, Power Demand, Min, Max)
Statistics.ResFc I Demand
Signal: Resetting of Statistics - Current Demand (avg, peak avg)
Statistics.ResFc Max
Signal: Resetting of all Maximum values
Statistics.ResFc Min
Signal: Resetting of all Minimum values
Statistics.StartFc I Demand-I
State of the module input: Start of Statistics of the Current Demand (Update the displayed Demand )
Logic.LE1.Gate Out
Signal: Output of the logic gate
Logic.LE1.Timer Out
Signal: Timer Output
Logic.LE1.Out
Signal: Latched Output (Q)
Logic.LE1.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE1.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE1.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE1.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE1.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE1.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE2.Gate Out
Signal: Output of the logic gate
Logic.LE2.Timer Out
Signal: Timer Output
Logic.LE2.Out
Signal: Latched Output (Q)
Logic.LE2.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE2.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE2.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE2.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE2.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE2.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE3.Gate Out
Signal: Output of the logic gate
Logic.LE3.Timer Out
Signal: Timer Output
Logic.LE3.Out
Signal: Latched Output (Q)
Logic.LE3.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE3.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE3.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE3.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE3.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE3.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE4.Gate Out
Signal: Output of the logic gate
Logic.LE4.Timer Out
Signal: Timer Output
Logic.LE4.Out
Signal: Latched Output (Q)
Logic.LE4.Out inverted
Signal: Negated Latched Output (Q NOT)
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Summary of Contents for EDR 3000
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