EDR-3000
IM02602003E
Name
Description
Logic.LE49.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE49.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE49.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE50.Gate Out
Signal: Output of the logic gate
Logic.LE50.Timer Out
Signal: Timer Output
Logic.LE50.Out
Signal: Latched Output (Q)
Logic.LE50.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE50.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE50.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE50.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE50.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE50.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE51.Gate Out
Signal: Output of the logic gate
Logic.LE51.Timer Out
Signal: Timer Output
Logic.LE51.Out
Signal: Latched Output (Q)
Logic.LE51.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE51.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE51.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE51.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE51.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE51.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE52.Gate Out
Signal: Output of the logic gate
Logic.LE52.Timer Out
Signal: Timer Output
Logic.LE52.Out
Signal: Latched Output (Q)
Logic.LE52.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE52.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE52.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE52.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE52.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE52.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE53.Gate Out
Signal: Output of the logic gate
Logic.LE53.Timer Out
Signal: Timer Output
Logic.LE53.Out
Signal: Latched Output (Q)
Logic.LE53.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE53.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE53.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE53.Gate In3-I
State of the module input: Assignment of the Input Signal
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Summary of Contents for EDR 3000
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Page 7: ...Medium Voltage Switchgear Assembly...
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