CXR Larus 80-100-400
Issue 1, July 2006
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5.1129 Controls and Indicators
The following controls and indicators appear on the front panel of the card:
a. The red FAIL LED lights if the on-card fuse blows or the processor or
power supply fails.
b. The green PORT 1 LED lights when Port 1 is active.
c. The green/red PORT 2 LED lights green when Port 2 is active and red
when there are Ethernet collisions.
d. The yellow OVERRIDE LED lights when manual override for clock
selection is active.
e. The red ALARM LED lights when an alarm condition exists.
f. The RESET PROC pushbutton resets the processor.
g. The RESET O/R pushbutton allows for manual override of clock selection.
h. The A/B CLOCK SELECT pushbutton allows for selection of Clock A,
Clock B, Input A, or Input B.
5.1130 One-wire
Interface
The one-wire interface provides input ports and serial communication to the
cards without UARTs in the system. It uses the queued serial peripheral
interface (QSPI) of the queued serial module to communicate with the input,
alarm, and output cards.
5.1131
Local Area Network Controller for Ethernet (10 Base T)
The 54550 Information Management Card uses the AM79C90 Local Area
Network Controller for Ethernet (LANCE). The LANCE is a 68-pin VSLI
device designed to interface a microcontroller to an IEEE 802.3/Ethernet
local area network. In conjunction with the AM7992B Serial Interface
Adapter (SIA), AM79C98 Transceiver, and closely coupled local memory
and microprocessor, the LANCE is intended to provide the 54550 with a
complete interface module for an Ethernet network. The device uses a
scalable CMOS technology and is compatible with the MC68K
microprocessors. On-chip Direct Memory Access (DMA), advanced buffer
management, and extensive error reporting and diagnostics facilitate design
and improve system performance.
The parallel interface of the LANCE is designed for easy interface to the 68K
line of microprocessors. The LANCE has a 24-bit wide linear address space
when it is in the Bus Master mode. A programmable mode of operation
allows byte addressing using an Upper Data Strobe and Lower Data Strobe
signal compatible with the 68K microprocessors. A programmable polarity