CXR Larus 80-100-400
Issue 1, July 2006
______________________________________________________________
____________________________________________________________
5−
60
5.14 Model 54572 Composite Clock Output Driver Card
5.1401
This card provides twenty separate composite clock outputs. The outputs
drive SF channel banks and other equipment that require composite clock
inputs. An alarm output signal alerts the 54560 Alarm Interface Card when
one or more outputs have failed.
5.141 Functions
5.1411
The Model 54572 Composite Clock Output Driver Card provides the
following:
a. Clock selection by a logic array based on HOLD indications from the A
and B track and hold cards. The current tracking clock or, if both are in
HOLD, the last track and hold card to go into the HOLD state is selected.
Switching is nonrevertive to minimize the number of phase
disturbances.
b. Override lines from the 54550 Information Management Card allowing
for manual clock selection and for automatic switching directly to a
reference input in the event that both track and hold cards fail (Major
alarm state).
c. The first output card from the left (any slot) acting as a master selector
and all other output cards slaved to it to ensure that all output cards
select the same clock reference.
d. A synchronization bus connecting all output cards to ensure that all
outputs from the shelf are frame and multiframe synchronized for DS1
SF (12 frame multiframe), DS1 ESF (24 frame multiframe), and E1 (16
frame multiframe) outputs. All composite clock outputs are byte
synchronized.
e. One-wire interface to the 54550 Information Management Card for
reporting personality, LEDs, and alarms.
5.142 Circuit
Description
The 54572 block diagram appears in Figure 5-13.
5.1421
Clock Select Switch
The clock select switch is a 1.544 MHz clock selector with phase buildout
circuit, byte synchronization system, LED indicators, and output alarms. The
selector output goes to a phase buildout circuit whose function is to smooth
out sudden phase changes (which might be as much as ±1/2 a unit interval)
occurring when the clock selection is changed. The rate of change of phase
is limited to under 20 nanoseconds (1/32 unit interval) in 14 milliseconds
(21,216 unit intervals).
