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5−
31
5.8221 DS1/E1
Receiver
The DS1/E1 receiver regenerates the selected incoming signal and recovers
both the clock and the data. The data go to the framing circuit. The 54591
measures the input DS1/E1 reference bit time phase as compared to the
ovenized crystal oscillator output by means of a digital phase detector.
Samples of phase information are collected and averaged, over about a one-
second time period, to provide input to the control algorithm. If, at any point in
the accumulation and calculation period, a condition is detected (excessive
errors, LOS, OOF, etc.) which causes the collected information to be suspect,
the unit enters the holdover state and does not update the correction to the
oscillator. If the data are qualified, then the update will proceed. After 128
acquire cycles (about 2 minutes) following initial qualification, the clock will be
in the tracking mode. After 5 to 7 minutes, the tracking mode will be at
minimum error if the input is within specifications. The 54591 will track timing
signals from any other Stratum 3/LNC or higher source (i.e., Stratum 2/TNC or
1/PRC) having a frequency offset of no more than ±7.1 Hz.
5.8222 Framer
The 54591 communicates with a CS2180 Transceiver Chip for the T1 inputs or
a CS2181 for the E1 inputs. The framing circuit detects the following framing
errors:
a. Yellow Alarm, LOS (175 ±75 consecutive zeros)
b. BPVs
c. Invalid CRC6 codes (ESF framing only) or CRC4 codes (CRC4 framing
only)
An impaired signal causes the microcontroller to cease tracking, go into the
HOLD mode, and show the type of impairment on the seven segment display.
5.8223 Ovenized Crystal Oscillator
A 10 MHz ovenized crystal oscillator provides the input to a 48-bit DDFS.
5.8224 Direct Digital Frequency Synthesizer
The oscillator is coupled to the DDFS and acts as a reference for it. The
DDFS operates on the presumption that oscillator frequency is kept within a
reasonable degree of precision, e.g. within one part in 10
-9
. The DDFS uses a
digital process to convert the oscillator signal into a signal having a second
related frequency. The DDFS accomplishes this conversion by utilizing a
stored algorithm and a numerical input from the microcontroller.
The DDFS accepts an integer, N, from the microcontroller. The DDFS then
generates a new output frequency 'F out' from 'F osc' according to the
following formula:
(N) (F osc)
