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Broadcom BCM1125, User Manual

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User Manual

BCM1250/BCM1125/BCM1125H

10/21/02

B r o a d c o m   C o r p o r a t i o n

Document

1250_1125-UM100CB-R

Section 3: System Overview

Page  

25

If an error is signalled during a data transfer the system takes care to maintain the error condition. If bad data
is sent to the L2 cache or memory controller an uncorrectable ECC pattern is written with the data, so that
subsequent reads will also see an error and bad data will not be used in processing. This can lead to a cascade
of errors during the period between the initial detection of an error and software recovery code running (the
SCD error log will record the first problem). 

The D_MOD signal is asserted if the data being transferred is dirty (i.e. differs from L2/memory). In this case
the L2 cache or memory controller will take a copy of the data, so that the new owner receives it clean. 

The memory controller and L2 cache work together to supply data for any of the memory regions of the address
space. 

Figure 7

 shows the decision process that is used on reads and writes to the memory region to

determine which agent supplies the data and which accepts write data. It also shows which of the memory or
L2 will write back data when dirty data is supplied by an exclusive owner.

100

Bus error. A CPU will take a bus error exception 
if it receives this error.

I/O bridge0: PCI parity error, master or target 
abort. HyperTransport NxA or error return.

I/O bridge1: Generic bus error (no chip select for 
the address, time-out during an access or I/O bus 
parity error). 

Memory Controller: No chip select decoded for 
the address.

SCD: The SCD will return this error with 
UNPREDICTABLE data if the bus watcher 
detects an illegal address.

101

Fatal bus error. The ownership of the block is 
unclear. This can be caused by a CPU tag parity 
error, or because software used a CACHEOP to 
invalidate an exclusive line and the CPU had 
committed to supply the line in the window while 
the operation executed. A CPU will take a bus 
error exception if it receives this error. 

Memory Controller: The memory controller 
returns UNPREDICTABLE data with this error 
code if an agent asserts both R_SHD and 
R_EXC.

I/O bridge1: This error code is returned with 
UNPREDICTABLE data and the io_coh_err bit 
will be set if some agent asserts both R_SHD and 
R_EXC during a coherent generic bus access.

110

Uncorrectable ECC error in the tag. A CPU will 
take a cache error exception if it receives this 
error.

CPU: Tag parity error.

L2 Cache: Tag ECC error.

111

Uncorrectable ECC error in the data (L2 cache 
or memory controller). A CPU will take a cache 
error exception if it receives this error.

CPU: Data cache had uncorrectable data ECC 
error.

Memory Controller: Data ECC error.

L2 Cache: Data ECC error

I/O bridge: Write of a Read-modify-write 
operation that received an uncorrectable data 
error during the read.

Table 6:  ZBbus Data Status Codes

 (Cont.)

D_CODE[2:0]

Status of Data on D_DA

Sources of Error

Summary of Contents for BCM1125

Page 1: ...ER MANUAL BCM1250 BCM1125 BCM1125H 1250_1125 UM100CB R 16215 Alton Parkway P O Box 57013 Irvine CA 92619 7013 Phone 949 450 8700 Fax 949 450 8710 10 21 02 User Manual for the BCM1250 BCM1125 and BCM1125H ...

Page 2: ...Revision 1 03 Specification on page 224 Section HyperTransport Differences from Revision 0 17 Specification on page 222 Section HyperTransport Target Done Counter on page 236 Section TCP Checksum Checking on page 283 Section Flow Control In Encoded Packet FIFO Modes on page 294 Section Restrictions When Resetting the Interface on page 301 Section Burst Mode on page 371 Section Early Chip Select on...

Page 3: ...tion 5 Updates for BCM1125 H New register Level 2 Cache Settings Register Section 6 Additional Clarifications and BCM1125 H descriptions New Section Memory Access Sequencing New Section Example CHannel and Chip Select Configurations Updated guidelines Timing Parameter Guidelines Section 7 Additional Clarifications and BCM1125 H descriptions New Section Unaligned Buffer Descriptor Format for Ethern...

Page 4: ...3 2002 by Broadcom Corporation All rights reserved Printed in the U S A Broadcom and the pulse logo are trademarks of Broadcom Corporation and or its subsidiaries in the United States and certain other countries All other trademarks are the property of their respective owners ...

Page 5: ... Signal Groups 7 BCM1125 H Signal Groups 8 Section 3 System Overview 9 Introduction 9 Internal Registers 11 Coherence 12 Ordering Rules and Device Drivers 14 CPU Speculative Execution 16 Error Conditions 17 Cache Error Exceptions 17 Bus Error Exceptions 18 CPU to CPU Communication BCM1250 Only 19 External Interrupts 19 Overview of the ZBbus Protocol 20 Arbitration 21 Address Phase 22 Response Phas...

Page 6: ...t 70 Trigger Events 70 Trigger Sequences 73 Using the Trace Buffer 76 Reading the Trace Buffer 79 Magic Decoder Ring For Using The Trace Buffer 81 Connections to the Trace Logic 83 Trace Example 1 All CPU0 Activity 84 Trace Example 2 Network Packet Headers 85 Section 5 L2 Cache 89 Introduction 89 Normal Operation 89 Using the L2 Cache as Memory 91 Standard RAM 92 Memory Locked in the L2 Cache 92 C...

Page 7: ...urations 109 Mapping 109 Channel Select 109 Chip Select 110 Example Channel and Chip Select Configurations 112 Row Column and Bank Configuration 117 Choosing Interleave Parameters 120 Page Policy 122 Supported DRAMs and DIMMs 123 DDR SDRAMS 123 DDR FCRAMs 123 DIMMs 124 Larger Memory Systems 124 ECC 125 SDRAM Timing 125 SDRAM Refresh 126 SDRAM Initialization and Commands 126 I O Control 128 Timing ...

Page 8: ...Operation 176 CRC and Checksum Generators 178 Checksum Generation 178 CRC Generation 179 Computation Sizes and Bandwidth 180 Examples 181 Data Mover Control Registers 184 Data Mover Descriptors 187 Section 8 PCI Bus and HyperTransport Fabric 190 Introduction 190 PCI and HyperTransport Address Range 192 Memory Mapped Devices 194 HyperTransport Expansion Space 194 Configuration Space 194 PCI I O Spa...

Page 9: ...Peer to Peer Accesses 219 PCI Bus To HyperTransport Fabric 219 HyperTransport Fabric to PCI Bus 221 PCI Arbiter 222 PCI Interrupts 222 HyperTransport Differences from Revision 0 17 Specification 222 HyperTransport Differences from Revision 1 03 Specification 224 Ordering Rules 231 Using the PCI in Device Mode 232 Configuration of PCI and HyperTransport 234 HyperTransport Target Done Counter 236 Sy...

Page 10: ...nfiguration 272 Transmit Path 274 Receiver Operation 275 Receiver Configuration 275 Receive Path 277 Destination Address Filtering 278 Receive DMA Channel Selection 281 Packet Type Identification 282 IPv4 Header Checksum 283 TCP Checksum Checking 283 Packets Dropped by the DMA Channel 283 Flow Control 284 Interrupts 286 Standard Interrupt Signaling 286 Split Interrupt Signaling 286 Management Inte...

Page 11: ...Loopback 326 DUART Registers 327 Synchronous Mode 337 Functional Overview 337 Input Line Interface 340 Input Using an External Enable 340 Input Using the Internal Sequencer 341 Output Line Interface 342 Output Using an External Enable 342 Output Using the Internal Sequencer 343 Synchronous Serial Protocol Engine 344 Operation in HDLC Mode 344 Framing Parameters 345 HDLC Transmitter 345 HDLC Receiv...

Page 12: ...Cacheable Access Blocking 364 Generic Bus Parity 364 Bus Width 365 Generic Bus Timing 365 Fixed Cycle Read Access 367 Fixed Cycle Write Access 368 Acknowledgement Read Access 369 Acknowledgement Write Access 370 Burst Mode 371 Early Chip Select 373 Boot ROM Support 373 Generic Bus Errors 374 Drive Strength Control 374 Generic Bus Registers 375 Section 12 PCMCIA Control Interface 384 Introduction 3...

Page 13: ...uction 404 SMBus Overview 404 Transport Protocol 404 Transport Protocol Reset 406 SMBus Protocol 406 Extended Protocol 408 Programming Model 410 Using SMBus Protocols 410 Using Extended Protocols 412 Direct Access 413 Booting Using an SMBus EEPROM 413 Switching from SMBus Mode 414 SMBus Registers 416 Section 15 JTAG and Debug 422 Introduction 422 TAP Controller 422 BYPASS Instruction 425 IDCODE In...

Page 14: ...CTRL and TRACECURCNT Instructions 431 PROCESSMON Instruction 432 Boundary Scan Register 432 BSRMODE Holding Boundary Scan Active 435 Processor and Probe Access 436 Processor Accesses to the JTAG Space 438 Probe Accesses to the ZBbus 438 Address Register 439 Data Register 439 EJTAG Control Register 440 Differences from EJTAG 2 5 Feb 22 2000 Specification 442 Section 16 Reference 446 Internal Regist...

Page 15: ...15 Chip Select Options 110 Figure 16 Example Single Channel 128MB 112 Figure 17 Example 1GB with two chip selects on one channel 113 Figure 18 Example 1GB with two chip selects interleaved on one channel 114 Figure 19 Example 1GB with two chip selects interleaved across both channels 115 Figure 20 Example 2GB with two chip selects interleaved on one channel 116 Figure 21 Timing Relationships Set b...

Page 16: ...erTransport 216 Figure 46 PCI Adaptive Retry Parameters 218 Figure 47 Buffers Used for PCI to HyperTransport Peer to Peer Accesses 220 Figure 48 Buffers Used for HyperTransport to PCI Peer to Peer Accesses 221 Figure 49 Configuration Space Address 234 Figure 50 HyperTransport Interface Clocks and FIFOs 256 Figure 51 Ethernet Interface Block Diagram 265 Figure 52 Ethernet Frame Format 268 Figure 53...

Page 17: ...s Matching 347 Figure 73 Synchronous Serial Loopback Connections 352 Figure 74 Fixed Cycle Read Access 367 Figure 75 Fixed Cycle Write Access 368 Figure 76 Acknowledge Read Access 369 Figure 77 Acknowledge Write Access 370 Figure 78 Generic Bus Burst Read 371 Figure 79 Generic Bus Burst Write 371 Figure 80 Example PCMCIA Slot Connection 385 Figure 81 Example Flash Card Timing Diagram 392 Figure 82...

Page 18: ...BCM1250 BCM1125 BCM1125H User Manual 10 21 02 Broadcom Corporation Page xviii Document 1250_1125 UM100CB R ...

Page 19: ...acturing Information Register 43 Table 15 System Configuration Register 43 Table 16 Scratch Register 45 Table 17 Mailbox Registers 46 Table 18 Interrupt Mappings 47 Table 19 Interrupt Message Format for Writes to interrupt_ldt_set Register 49 Table 20 Delivery of HyperTransport Interrupts 49 Table 21 Interrupt Registers 52 Table 22 Interrupt Sources 52 Table 23 Watchdog Timer Initial Count Registe...

Page 20: ...ss Control Bundle 77 Table 50 Trace Entry Format and Read Order 79 Table 51 Decode of some TIDs for system revision PERIPH_REV3 81 Table 52 Encoded Byte Enables for CPU Transactions 82 Table 53 Addresses for Memory Banks 92 Table 54 Management Address 95 Table 55 ECC Diagnostic Operations 98 Table 56 Level 2 Cache Tag Register 100 Table 57 Level 2 Cache Settings Register 100 Table 58 Clock Speed 1...

Page 21: ... Select Register 142 Table 83 Column Address Bits Select Register 142 Table 84 Bank Address Bits Select Register 143 Table 85 Chip Select Attribute Register 143 Table 86 ECC Test Data Register 144 Table 87 ECC Test ECC Register 144 Table 88 Data Buffer Parameters 148 Table 89 Data Parameters 148 Table 90 Address Used for ASIC Mode Transfers 160 Table 91 Ethernet and Serial DMA Configuration Regist...

Page 22: ...ptor Address 185 Table 118 Data Mover CRC Definition Registers Only if System Revision PERIPH_REV3 185 Table 119 Data Mover CRC Checksum Definition Registers Only if System Revision PERIPH_REV3 186 Table 120 Data Mover Channel Partial Result Registers Only if System Revision PERIPH_REV3 186 Table 121 Data Mover Descriptor First Doubleword 187 Table 122 Data Mover Descriptor Second Doubleword 188 T...

Page 23: ...52 Table 151 HyperTransport Isochronous Ignore Mask Offset 60Bits 31 0 253 Table 152 HyperTransport Error Control Register Offset 68 Bits 23 0 253 Table 153 HyperTransport Error Status Register Offset 68 Bits 31 24 254 Table 154 HyperTransport SRI Transmit Control Register Offset 6C Bits 23 16 254 Table 155 HyperTransport SRI Data Buffer Allocation Register Offset 6C Bits 15 0 254 Table 156 HyperT...

Page 24: ...ceive Address Filter Mask Registers Only if System Revision PERIPH_REV3 315 Table 189 MAC Receive Address Filter Hash Match Registers 315 Table 190 MAC Transmit Source Address Registers 315 Table 191 MAC Packet Type Configuration Registers 316 Table 192 MAC Receive Address Filter Control Registers 316 Table 193 MAC Receive Channel Select Map Registers 318 Table 194 MAC MII Management Interface Reg...

Page 25: ... 222 DUART Output Port RTS Register 335 Table 223 Synchronous Serial Interface Signal Names 339 Table 224 Synchronous Serial Interface GPIO Pins 339 Table 225 Sequencer Table Entries 341 Table 226 HDLC Frame Structure 344 Table 227 Option Flags for Synchronous Serial Transmit Channel 345 Table 228 Status Flags for Synchronous Serial Receive Channel 349 Table 229 Recommended Line Interface Settings...

Page 26: ...eneric Bus Error Data Register 0 378 Table 258 Generic Bus Error Data Register 1 378 Table 259 Generic Bus Error Data Register 2 378 Table 260 Generic Bus Error Data Register 3 378 Table 261 Generic Bus Error Address Register 0 379 Table 262 Generic Bus ErrorAddress Register 1 379 Table 263 Generic Bus Error Parity Register 379 Table 264 Output Drive Control Register 0 379 Table 265 Output Drive C...

Page 27: ...Table 292 SMBus Status Registers 417 Table 293 SMBus Data Registers 417 Table 294 SMBus Extra Data Registers 417 Table 295 SMBus Packet Error Check Registers 418 Table 296 SMBus Start and Command Registers SMBus Mode 418 Table 297 SMBus Start and Command Registers Extended Mode 419 Table 298 JTAG Signals 422 Table 299 JTAG Instructions 424 Table 300 JTAG Device ID Register 425 Table 301 JTAG Wafer...

Page 28: ...BCM1250 BCM1125 BCM1125H User Manual 10 21 02 Broadcom Corporation Page xxviii Document 1250_1125 UM100CB R ...

Page 29: ...ering Protocol conversion VoIP Gateway Network appliances file servers web cache print servers VPN access firewalls gateways The different members of the family target different performance points and applications while retaining software compatibility This User Manual covers the dual processor BCM1250 and the uni processor BCM1125 and BCM1125H parts All the parts use the SB 1 CPU core This is a h...

Page 30: ...s that can run full duplex at OC 48 rates Two serial ports are provided for use as UARTs or for WAN connections at up to T3 OC 1 rates 55Mbit s High speed I O is provided using the HyperTransport formerly called Lightning Data Transport or LDT I O fabric and a 66 MHz PCI rev 2 2 local bus To enable low chip count systems the BCM1250 includes a configurable generic bus that allows glueless connecti...

Page 31: ...abric Both the BCM1125 and BCM1125H have a 66 MHz PCI rev 2 2 local bus To enable low chip count systems both parts include a configurable generic bus that allows glueless connection of a boot ROM or flash memory and simple I O peripherals On chip debug trace and performance monitoring functions assist both hardware and software designers in debugging and tuning the system The system can be run ei...

Page 32: ...rt I O Link Specification Revision 1 03 from the HyperTransport Technology Consortium PCI Specification Revision 2 2 MIPS64 Architecture for Programmers http www mips com publications index html Volume I Introduction to the MIPS64 Architecture MD00083 Volume II The MIPS64 Instruction Set MIPS MD00087 Volume III Privileged Resource Architecture MIPS MD00091 Volume IV b The MDMX ASE to MIPS64 MIPS M...

Page 33: ...the system to creating an environment in which the system no longer continues to operate Following an UNDEFINED operation assertion of the reset signal may be required to restore deterministic operation Register Definition Tables include the register name and physical address in their titles The table shows all bits that are implemented Registers are all allocated a 64 bit field any bits that are ...

Page 34: ...n be used by software to determine the available features Note that code written for the earlier parts will work on PERIPH_REV3 parts provided that it correctly observes Reserved fields An earlier version of the manual should be used for the prototype parts marked BCM12500 which lack some of the peripheral functionality Broadcom Use Only registers and operations are intended for use by Broadcom in...

Page 35: ...RST_L Generic IO_AD 23 0 IO_AD 31 24 IO_ADP 3 0 GPIO 5 2 IO_CS_L 7 0 IO_WR_L IO_OE_L IO_ALE IO_RDY Bus S0_DIN S0_DOUT S0_CIN_RCLKIN S0_COUT S0_CTS_TCLKIN S0_RTS_TSTROBE S0_TIN S0_RIN S1 same as S0 Serial Ports SDA0 SCL0 SDA1 SCL1 SMBus MAC E0_COL E0_CRS E0_TCLKO E0_TCLKI E0_TXD 7 0 E0_TXEN E0_TXER E0_RCLK E0_RXD 7 0 E0_RXDV E0_RXER E0_MDIO E0_MDC M0_CAS_L M0_WE_L P_PERR_L P_SERR_L P_STOP_L E1 same...

Page 36: ... 31 24 IO_ADP 3 0 GPIO 5 2 IO_CS_L 7 0 IO_WR_L IO_OE_L IO_ALE IO_RDY Bus S0_DIN S0_DOUT S0_CIN_RCLKIN S0_COUT S0_CTS_TCLKIN S0_RTS_TSTROBE S0_TIN S0_RIN S1 same as S0 Serial Ports SDA0 SCL0 SDA1 SCL1 SMBus MAC E0_COL E0_CRS E0_TCLKO E0_TCLKI E0_TXD 7 0 E0_TXEN E0_TXER E0_RCLK E0_RXD 7 0 E0_RXDV E0_RXER E0_MDIO E0_MDC M_CAS_L M_WE_L P_PERR_L P_SERR_L P_STOP_L E1 same as E0 REFCK0 REFCK1 TCK TMS TDI...

Page 37: ...nd the System Control and Debug unit SCD Figure 5 Logical Block Diagram of BCM1250 and BCM1125 H System Control Debug Performance Data L1 Inst L1 L2 DDR SDRAM Ch1 Data L1 Inst L1 Monitor Interrupt Mappers Timers Generic Data Mover Bus Trace Controller Bus Error Log Counters Address Trap Trace Buffer I O Bridge 0 I O Bridge 1 PCI Host Bridge HT Host Bridge PCI Bus HT Fabric DMA MAC0 DMA MAC1 DMA Se...

Page 38: ...rts the processor is CPU 0 and will report that it is a uniprocessor in the Processor Identification Register The Level 2 cache L2 is organized slightly differently than L2 caches in other systems It is shared by the processor s and any I O DMA masters It is best understood as a cache on the front of the memory as shown in Figure 5 rather than by using the traditional model where the L2 is associa...

Page 39: ...used for all access widths in a little endian system In a big endian system if the access to the registers is as a double word the base address should be used for a word access the address is the base address plus 4 for a half word access use the base address plus 6 and for a byte access use the base address plus 7 For example consider a register with 1 valid byte and base address 1234_0000 Its do...

Page 40: ...ves ownership of a block it is possible that it will lose ownership before it has received the data in this case it can perform one operation on the block before passing the data to the new owner this is required to avoid live lock when two agents are trying to write to the same block Coherent memory references check L1 and L2 tags and the partial line merge buffer in the I O bridges at bus speed ...

Page 41: ...the same time this instruction executes the snoop will hit on the line in the L1 but the line is invalidated before it can be evicted The CPU will respond by returning UNPREDICTABLE data marked with a fatal bus error There is no problem with using the Writeback Invalidate CACHE operation The generic bus section of memory may be mapped cacheable coherent The I O bridge will act as default owner in ...

Page 42: ... where a processor writes some data and then sets a flag to indicate it is done Another processor polling the flag will always see the new value of the data if it sees the new value of the flag Rule 2 allows the flag to be a peripheral register memory data such as DMA descriptors or data buffers in cacheable coherent space can be updated and then a control register in uncached space written for ex...

Page 43: ...tial SYNC operation No instructions will be issued from the time the store conditional is issued until it graduates In most cases no extra SYNC instructions are needed when acquiring a lock The load linked is used to check if the lock is free and the store conditional can be used to claim it If the load indicates that the lock is in use or the store conditional fails the code should spin waiting f...

Page 44: ...d normally be disabled for memories The only space where speculation can cause a problem is therefore the xkphys aliases for PCI and HyperTransport peripherals In the absence of program error i e the register just contains the wrong value there are two reasonable instruction sequences that could cause this behavior if at the start of the sequence the register happens to hold a kseg0 or xkphys cach...

Page 45: ...e state of external error reporting registers in addition to the ones in the CPU Note that when data is returned to the data cache marked with an error code it will be written to the cache with an uncorrectable ECC error after ECC is calculated the bottom two bits of each double word are inverted to force the error to ensure that it is not used on this processor and that the error is preserved if ...

Page 46: ...the generic bus chip select or memory controller address parameters may have been changed If any branches were executed while the address was valid the CPU will store the branch target information in its branch prediction structures At a later time it may predict that a branch destination is at the now invalid address and issue a speculative instruction fetch In this case the CPU will not take a b...

Page 47: ...uction if the pipeline is running there will immediately be an instruction to use so the shorter time will apply the longer time is taken when the pipeline is stalled and the instruction that will carry the exception has to be generated EXTERNAL INTERRUPTS External interrupts from the PCI inputs are synchronized into the internal clock and pass through the interrupt mapper see Section Interrupts o...

Page 48: ...fewer than 64 Table 2 lists the signals in each section of the bus Table 1 ZBbus Agent IDs Agent ID Description CPU0 0 SB 1 CPU 0 CPU1 1 SB 1 CPU 1 Only in BCM1250 IOB0 2 I O Bridge 0 connects PCI and HyperTransport interfaces to the ZBbus IOB1 3 I O Bridge 1 connects the MACs and slow speed peripheral interfaces to the ZBbus SCD 4 System Control and Debug Unit 5 Reserved L2C 6 L2 Cache MC 7 Memor...

Page 49: ...herency state for the transaction and thus determines which agent is responsible for providing the data Ownership transfers at the end of the R phase 4 The agent providing the data arbitrates for the data bus 5 The data phase D phase transfers the associated data and ends the transaction Normally an agent only arbitrates for the bus when it is prepared to make a transaction However occasionally ag...

Page 50: ...s exclusively owned by the acquiring agent All other copies of the block are invalidated Data will be supplied by the exclusive owner if one is identified in the response phase otherwise the default owner will supply it WRITE 010 Write The block is written back to L2 memory Data will be supplied by the requester WRITE_INV 011 Write Invalidate The requesting agent acquires ownership of the block an...

Page 51: ...l examine the status after doing a Read shared command if no other agent has a shared copy of the data then the requesting agent is permitted but not required to take exclusive ownership of the block as if it had issued a Read Exclusive command An agent can assert both R_EXC and R_SHD to indicate an error This is done if there is a parity or ECC error in the tags and the agent is unable to determi...

Page 52: ...when the endian mode changes Table 5 shows the mapping from byte address to data bits and byte enables The D_CODE indicates the status of the data being transferred as shown in Table 6 Table 5 ZBbus Byte Lane Assignments Data bits 2 2 5 4 5 8 2 2 4 4 7 0 2 2 3 3 9 2 2 2 3 2 1 4 2 2 2 1 3 6 2 2 1 0 5 8 2 2 0 0 7 0 1 1 9 9 9 2 1 1 9 8 1 4 1 1 8 7 3 6 1 1 7 6 5 8 1 1 6 6 7 0 1 1 5 5 9 2 1 1 5 4 1 4 1...

Page 53: ...rget abort HyperTransport NxA or error return I O bridge1 Generic bus error no chip select for the address time out during an access or I O bus parity error Memory Controller No chip select decoded for the address SCD The SCD will return this error with UNPREDICTABLE data if the bus watcher detects an illegal address 101 Fatal bus error The ownership of the block is unclear This can be caused by a...

Page 54: ...state the SCD will then release the system and CPU0 The device will source the reset signal for the board RESETOUT_L the PCI bus P_RST_L and the HyperTransport fabric LDT_RESET_L and LDT_PWROK if the link needs a cold reset These are all driven during the internal reset period and other than P_RST_L can be asserted separately under software control Reset can also be initiated by software or time o...

Page 55: ...nfiguration Options IO_AD Bit Name Pulled Up to 3 3V Pulled Down Section 0 Reserved Reserved Normal Operation N A 1 clk100_src The internal 100MHz clock and IO_CLK100 come directly from the CLK100_p reference The IO_CLK100 will have a duty cycle only a little worse than the reference clock The internal 100MHz clock and IO_CLK100 are generated by dividing down the output of the PLL that feeds the C...

Page 56: ...s used for the boot ROM is configured for multiplexed operation with 32 data bits and 32 address enable bits The SMBus EEPROM boot is configured for small 16 kbit EEPROMs using the read word protocol Section Configurin g a Chip Select Region on page 36 3 Section Booting Using an SMBus EEPROM on page 413 18 boot_mode 1 The boot address will access an EEPROM on the SMBus The boot address will access...

Page 57: ...t CPU 0 invalidates its cache tags and the L2 cache tags prior to releasing CPU 1 from reset CPU 1 should clear its tags and signal CPU 0 that coherent accesses may be used It is possible to independently reset the CPUs either from software or the watchdog timers This is a potentially hazardous operation since while in reset the CPU is removed from participation in the coherence protocol When the ...

Page 58: ... this sequence it is therefore safe to release it from reset in a system that is already running with coherent accesses The different actions of the resets may be used to identify which reset happened A sequence similar to the following could be used this assumes that the device uses a UART on port 0 for the console but the IO_AD 12 is set for synchronous port index wb invalidate over whole Dcache...

Page 59: ... an integer PLL ratio is used i e IO_AD 7 was sampled low ensures the duty cycle is no worse than 40 60 regardless of the reference clock However if a nonintegral PLL ratio is used only the rising edge of the internally generated IO_CLK100 is valid the time the output spends high can vary from cycle to cycle and be as short as 10 of the cycle The PCI bus and network interfaces have their own bus c...

Page 60: ...he full bandwidth is not needed I O Bridge 0 is designed for operation with the clock about 200 MHz it should be set in the range 166 266 MHz check the data sheet for the maximum frequency for a given speed grade I O Bridge 1 is designed for operation with the clock about 266 MHz it should be set in the range 233 333 MHz check the data sheet for the maximum frequency for a given speed grade The ma...

Page 61: ...ial Interface some modes PCI controller MAC 0 MAC 1 FIFO 0 MAC 2 FIFO 1 Interface clocks asynchronous to 100 MHz Reference Core Clock to CPU0 CPU1 L2 Cache HT Internal clock ZBbus Clock M0 Clock M1 Clock HT Clock GPIO Glitch Filter Generic Bus Timing Clock for Watchdog Timers Clock for Generic Timers Baud CLK0 Baud CLK1 SCL0 SCL1 BAUD Rate A BAUD Rate B SMBUS0 MEM Channel 1 MEM Channel 0 SSTL 2 SS...

Page 62: ...e Top Owner 00_0000_0000 00_0FFF_FFFF Memory controller 00_1000_0000 00_1005_FFFF System control and debug 00_1006_0000 00_3FFF_FFFF I O system 00_4000_0000 00_5FFF_FFFF HyperTransport PCI memory mapped I O 32 bit addressing range Match byte lane endian policy 00_6000_0000 00_7FFF_FFFF HyperTransport PCI memory mapped I O 32 bit addressing range Match bit lane endian policy 00_8000_0000 00_9FFF_FF...

Page 63: ...cesses to Reserved or Unused regions will result in UNPREDICTABLE behavior Writes will be discarded Figure 9 Memory Map System Control and Debug First SDRAM Region Boot ROM Internal Devices Reserved PCI HT Config 01_0000_0000 00_A000_0000 00_0000_0000 SDRAM Expansion Maps to 00_D800_0000 00_DFFF_FFFF With Match Bit Endian Policy PCI HT I O Space HT PCI Special L2 Direct Access Fourth SDRAM Region ...

Page 64: ... KB I O Duart status and control 00_1006_0400 00_1006_07FF 1 KB I O Sync serial dma and HDLC ch 0 00_1006_0800 00_1006_0BFF 1 KB I O Sync serial dma and HDLC ch 1 00_1006_0C00 00_1006_0FFF 1 KB I O Unused 00_1006_1000 00_1006_17FF 2 KB I O Generic Bus config 00_1006_1800 00_1006_1FFF 2 KB I O Generic Bus status and log PCMCIA config and status 00_1006_2000 00_1006_2FFF 4 KB I O Reserved 00_1006_30...

Page 65: ...stem Management Match bit lane endian policy Reserved on BCM1125 00_F920_0000 FD_F92F_FFFF 1 MB HT N A 00_F930_0000 00_FBFF_FFFF 45 MB HT Reserved 00_FC00_0000 00_FDFF_FFFF 32 MB PCI HT I O space only 25 bits Match bit lane endian policy 00_FE00_0000 00_FEFF_FFFF 16 MB PCI HT Configuration Space Match bit lane endian policy 00_FF00_0000 00_FFFF_FFFF 16 MB PCI HT Reserved 01_0000_0000 7F_FFFF_FFFF ...

Page 66: ...5 BCM1125H User Manual 10 21 02 Broadcom Corporation Page 38 Section 3 System Overview Document 1250_1125 UM100CB R FE_0000_0000 FF_FFFF_FFFF 8 GB HT Reserved Table 11 Address Map Details Cont Base Top Size Owner Use ...

Page 67: ...User Manual BCM1250 BCM1125 BCM1125H 10 21 02 Broadcom Corporation Document 1250_1125 UM100CB R Section 3 System Overview Page 39 This Page is left blank for notes ...

Page 68: ...BCM1250 BCM1125 BCM1125H User Manual 10 21 02 Broadcom Corporation Page 40 Section 3 System Overview Document 1250_1125 UM100CB R This Page is left blank for notes ...

Page 69: ... number The second is the system configuration register system_cfg which reports the states of the reset time configuration options and allows resetting of various sections of the system The system_cfg register is accessible both from the system and from the JTAG port A CPU can cause a system reset by setting the system_reset bit of the system_cfg register This will behave the same as the COLDRES_...

Page 70: ... the value is preserved over other resets The sw_flag bit in the system_cfg register may be used to indicate the validity of the scratch value since the flag is cleared on a cold reset and preserved over other resets The sw_flag may also be used by the system to distinguish between cold resets and others Software can check the bit after reset if the bit is zero then the reset was a cold reset and ...

Page 71: ...t CPU clock 2 for use with slow CPU clocks 11 7 pll_div ext Read Only reflects the strap resistors on generic IO_AD 11 7 that select the PLL Divide ratio 12 ser0_enable ext Read Write The default reflects the strap resistor on generic IO_AD 12 but this bit can be written by software to change the setting 0 Serial interface 0 is in asynchronous uart mode 1 Serial interface 0 is in synchronous mode ...

Page 72: ...ble via JTAG only Broadcom use only 42 pllbypass 1 b0 Writable via JTAG only Broadcom use only 44 43 pll_iref 2 b0 Writable via JTAG only Broadcom use only 46 45 pll_vco 2 b0 Writable via JTAG only Broadcom use only 48 47 pll_vreg 2 b0 Writable via JTAG only Broadcom use only 49 mem_reset 1 b0 Writable via JTAG only When set the memory controller is held in reset 50 l2c_reset 1 b0 Writable via JTA...

Page 73: ...m Use Only 63 sw_flag 1 bx This read write bit is cleared by a cold reset Its value is preserved on any other reset It may be used by software to detect the reset type or for any other use Table 15 System Configuration Register Cont system_cfg 00_1002_0008 Bits Name Default Description Table 16 Scratch Register system_scratch 00_1002_0C10 Bits Name Default Description 63 0 value 64 hx This registe...

Page 74: ...ded One or more of the four interrupts will be raised whenever there are outstanding events in the mailbox This is likely to be the best method to use if high speed I O interrupts will be feeding the mailbox At the other extreme each of the quarters of the mailbox could be considered a channel for passing 16 bit messages An example use is in inter processor procedure calls The source of the call w...

Page 75: ...r including system mailbox and HyperTransport sources and describes all the associated registers The interrupt mapper receives the level sensitive interrupts from all sections of the part Each source has an associated mask bit and a 3 bit map register If the source is interrupting and not masked out it is driven to one of the CPU interrupt lines according to the mapping Table 18 shows the mapping ...

Page 76: ...or number in the interrupt mapper The MIPS architecture does not directly support hardware interrupt vectoring so the vector number is used by the hardware to decide which input to the interrupt mapper will be triggered and software can do any required vectoring The interrupt packet also includes a destination This is either a physical processor number or a system specific logical mapping The BCM1...

Page 77: ...ation selected is either the lowest priority or the CPU that is currently servicing an interrupt from the same source Since MIPS architecture CPUs give no external indication of which interrupt they are currently servicing the mapper implements this by delivering the interrupt to the lowest numbered CPU to which it is directed All HyperTransport interrupts are thus presented to the interrupt mappe...

Page 78: ...evice bridged from the HyperTransport then the command packet will be routed to the intervening HyperTransport PCI bridge If the southbridge is on the PCI interface set by the southOnLDT configuration bit being clear the IACK access will be run as a PCI IACK cycle but in that case the interrupt would not have come in as a HyperTransport External Interrupt message THE FULL INTERRUPT MAPPER The full...

Page 79: ...its interrupt_ldt_clr_x 64 bits interrupt_diag_x 64 bits interrupt_mask_x 64 bits interrupt_ldt_x 64 bits ht interrupt decode logic expands to set one of the 128 bits in terrupt_source_status_x 64 bits system sources Map Registers In O0 4 interrupt_status_0_x 64 bits INT 0 int_trace_trigger_x interrupt_ldt_set 64 bits same location for all mappers 64 64 64 64 64 64 64 64 O1 interrupt_status_1_x 64...

Page 80: ...ill be set only if the corresponding source is interrupting is not masked and is mapped to this output interrupt_source_status _0 00_1002_0040 _1 00_1002_2040 Read Only A bit will be set if the corresponding source is interrupting regardless of the state of the interrupt mask interrupt_trace _0 00_1002_0038 _1 00_1002_2038 Setting a bit in this register allows the interrupt to trigger the trace un...

Page 81: ...rrupt from the PCMCIA controller they are cleared by reading the pcmcia_status register as described in Section Using The PCMCIA Card on page 390 13 addr_trap_int Address trap interrupt Raised by any of the address traps counting from 1 to 0 Cleared by reading the addr_trap_reg See Section Address Trapping on page 67 14 perf_cnt_int System performance counter interrupt Raised by any of the system ...

Page 82: ...rt interrupt controller sets any bit cleared when the CPU clears all the bits 27 mbox_int_1 Mailbox bits 47 32 non zero Interrupts when another CPU or the HyperTransport interrupt controller sets any bit cleared when the CPU clears all the bits 28 mbox_int_2 Mailbox bits 31 16 non zero Interrupts when another CPU or the HyperTransport interrupt controller sets any bit cleared when the CPU clears a...

Page 83: ...pts 43 gpio_int_11 GPIO pin 11 interrupt 44 gpio_int_12 GPIO pin 12 interrupt Interrupts when external source raises an interrupt If level sensitive the external source must clear the interrupt If edge triggered the gpio_clr_edge register must be written to clear the interrupt Generation of these two interrupts may be disabled in the gpio_int_type register to free these vectors for use by HyperTra...

Page 84: ...tInt interrupt packet directed to this CPU had been received from the HyperTransport bus This bit is cleared using the interrupt clear register HyperTransport interrupts are directed so the source for this bit differs for each interrupt controller 55 pci_error_int PCI error interrupt This bit is set when an error is seen on the PCI bus It can be caused by PCI parity errors target abort master abor...

Page 85: ...ed by any write to the configuration register If the timer times out for a second time i e before the interrupt has been cleared the default behavior of the watchdog is to signal the system controller to perform a full reset of the part and any external devices that take reset from the RESETOUT_L LDT_RESET_L HT_RESET_L or PCI P_RST_L signals Once the watchdog has signalled a reset it will be disab...

Page 86: ...ere is no detection of missed interrupts once the interrupt has asserted it will only be raised again after it has been cleared and then the counter reaches zero TIMER SPECIAL CASES If the initial count of any timer regardless of mode is set to zero and the timer is enabled then an interrupt will be signalled every clock tick It is UNPREDICTABLE if writing the configuration register will cause the...

Page 87: ...n Registers watchdog_timer_cfg_0 00_1002_0060 watchdog_timer_cfg_1 00_1002_0160 Write clears interrupt Bits Name Default Description 0 watchdog_timer_enable 1 b0 When this bit is written with a 0 the timer will be disabled When this bit is written with a 1 regardless of its previous state the timer will be loaded from the initial count and start decrementing 1 reserved 1 b0 Reserved 4 2 reset_type...

Page 88: ...general_timer_cnt_3 00_1002_0188 READ ONLY Bits Name Default Description 22 0 timer_cnt 23 bx Timer current count register When the timer is running the count decrements every microsecond 63 23 reserved 41 h0 Reserved Table 28 General Timer Configuration Registers general_timer_cfg_0 00_1002_0090 general_timer_cfg_1 00_1002_0098 general_timer_cfg_2 00_1002_0190 general_timer_cfg_3 00_1002_0198 Wri...

Page 89: ...erf_cnt_int interrupt will be raised The interrupt is removed and all the counters are cleared when the clear bit in the perf_cnt_cfg register is written with a 1 Since it takes a cycle to disable the counters there is one additional cycle sampled after one or more of the counts reaches FF_FFFF_FFFF during which the counter may overflow if its source is still active There is an additional bit in t...

Page 90: ...grant The counter is incremented every cycle some agent loses arbitration for the address bus i e there are two or more requesters in arbitration 04 Address bus cycles arbitrated but not used The counter is incremented every time the address bus is granted but the agent drives a NOP command 05 Address match 0 count counts each bus address cycle that matches the address trap comparator The occurren...

Page 91: ...the total sum of cycles between agent n requesting the bus and agent n receiving grant on the bus 30 Memory channel 0 read accesses Counts the number of reads to memory 31 Memory channel 0 write accesses Counts the number of writes to memory 32 Memory channel 0 turnarounds Counts the number of times the controller changes from read to write or write to read 33 Memory channel 0 page hits Counts the...

Page 92: ...51 on page 81 The responder id gives the number of the agent that reported the error The data that was returned with the error code is also captured but in many cases it will be of UNPREDICTABLE value Note that when a bus error or fatal error is returned to a CPU it will take a bus error exception and when an uncorrectable ECC error is returned it will take a cache error exception These exceptions...

Page 93: ...ror See Table 1 on page 20 24 22 dcode 3 b0 Data transfer error code See Table 6 on page 24 29 25 reserved 5 b0 Reserved 30 mult_errors 1 b0 Set to indicate multiple errors The first fatal one or the most recent non fatal one is logged all were counted 31 reserved 1 b1 Reserved Reads as 1 63 32 notimp 32 bx Not Implemented Table 36 Bus Watcher Error Status Debug Register bus_err_status_debug 00_10...

Page 94: ...f write the register with zero to clear the count 31 24 l2_bad_t_ecc 8 b0 Count of uncorrectable L2 tag errors saturates at 8 hff write the register with zero to clear the count 63 32 notimp 32 bx Not Implemented Table 39 Bus Watcher Memory and I O Error Counter Register bus_mem_io_errors 00_1002_08C8 Should only be written with 32 bit or 64 bit write Bits Name Default Description 7 0 mem_cor_d_ec...

Page 95: ...currence count Any access of the selected type with an address greater than or equal to the lower register and less than or equal to the upper register matches the range Thus to trap on a specific address the upper and lower addresses are set to be the same When an access matches and the occurrence counter is greater than zero the counter will decrement Provided the address trap interrupt is clear...

Page 96: ...ction System Performance Counters on page 61 Table 40 Address Trap Trigger Index Register addr_trap_index 00_1002_00B0 READ ONLY Bits Name Default Description 3 0 addr_trap_index 4 b0 Trap that triggered the interrupt 7 4 reserved 4 h0 Reserved Table 41 Address Trap Trigger Debug Register addr_trap_reg_debug 00_1002_0460 READ ONLY Bits Name Default Description 63 0 value 64 hx This register contai...

Page 97: ...the source agent of the transaction to be compared and inverting the sense of both address and source comparisons Useful values are x00 Trap for all sources if address is in the range x01 Trap for all sources if address is not in the range 010 Trap if top 4 bits of tid matches source and address is in the range 011 Trap if top 4 bits of tid matches source and address is outside the range 110 Trap ...

Page 98: ... in the flags that are set in the control register There are two components events and sequences A trigger event is signalled when the cycle on the ZBbus or some other system state matches a condition Up to four events are concatenated to make a sequence The sequence also includes an action which is one of the trace buffer commands start stop or freeze and an indication if the trace buffer should ...

Page 99: ...l not happen again until after the trace outputs from both mappers have cleared An external device can trigger an event by pulling the DEBUG_L pin low DEBUG_L is a bidirectional open collector signal and must have an external pull up to 3 3V The SCD can signal the completion of a trigger event sequence by pulling the signal low for 10 ZBbus cycles see Section Trigger Sequences on page 73 The state...

Page 100: ...he transaction matches the req_id field of this register 5 data_id_match 1 b0 When set the data portion of the event only occurs if the data ID of the transaction matches the data_id field of this register 6 resp_id_match 1 b0 When set the data portion of the event only occurs if the responder ID of the transaction matches the resp_id of this register 7 interrupt 1 b0 When set the event occurs whe...

Page 101: ...sed as 5FFF The functions that can be performed when a sequence is complete are 1 Start collecting samples This enables collection of samples into the trace buffer unless collection has been frozen The sample that triggers the start will be recorded if the sequence is marked with one of the filter bits described below 2 Stop collecting samples This suspends collection of samples into the trace buf...

Page 102: ...e state of trace collection Debug Pin causes the SCD to pull the DEBUG_L pin low for 10 ZBbus clock cycles Debug CPU causes the SCD to assert the debug interrupt to both CPUs The debug interrupt is cleared by a read of the trace_cfg register The outputs from all the sequencers are combined If multiple functions are signalled freeze has the highest priority then stop then start Note that when an ad...

Page 103: ...uld be performed when the sequence completes 00 Nop No function is performed 01 Start The trace collection is started 10 Stop Trace collection is stopped 11 Freeze The trace buffer is frozen 18 Asample 1 b0 If this bit is set then an address trace is taken when the sequence completes if Dsample is set this bit is ignored unless all the select fields are 4 hF If the select fields are all 4 hF and A...

Page 104: ...reset ready for collection to begin This bit always reads as zero 1 startread 1 b0 When this bit is written with a 1 the trace buffer read pointer and latch are prepared for reading This bit always reads as zero Note that the buffer can only be read once after a collection if this bit is written with a 1 for a second time the data read back will be UNPREDICTABLE 2 start 1 b0 When this bit is writt...

Page 105: ...rship unclear 110 Uncorrectable tag ECC error L2 111 Uncorrectable data ECC error CPU L2 Mem 3 D_MOD D phase indication that the data is dirty this has no relationship to the A and R phase signals 7 4 D_RSP 3 0 Data phase responder ID this has no relationship to the A and R phase signals 17 8 D_ID 9 0 Data phase transfer ID this has no relationship to the A and R phase signals 9 6 requester ID 5 0...

Page 106: ...Uncacheable 11 Uncacheable accelerated may have merged writes 68 66 A_CMD Address phase command bits 000 READ_SHD 001 READ_EXC 010 WRITE 011 WRITE and INVALIDATE 100 INVALIDATE 101 110 Reserved 111 No command valid NOP 103 69 A_AD 39 5 Line address of the transaction on the bus 113 104 A_ID 9 0 This is the value of the address ID bits on the bus A_ID 9 6 Requester ID A_ID 5 0 Unique number within ...

Page 107: ...lds of the sample are valid Software or the JTAG probe must perform six reads to collect the entire sample before decoding it Table 50 describes the entry formats and the order in which they are read When all the entries have been read from the buffer the ATRIG and DTRIG bits are forced to zeros in any subsequent reads This condition can be used to terminate reading the buffer or the trcFull and t...

Page 108: ...ding the bundle is The entries are returned with the newest one first and the earliest available read out last The postprocessing software must take care to reverse the order to show causality if b 127 1 if b 126 1 Have valid address and valid data sample Format 2 else Format 1 if b 255 0 Have 1 valid address sample else if b 383 0 Have 2 valid address samples else ...

Page 109: ...e Table 1 TID 5 0 Set by the agent Description CPU 000x 11nnnn Instruction Fetch 000x 000nnn Read for read queue entry nnn 000x 10nnnn Write or Evict Bridge 0 0010 00pnnn Read from port p 1 PCI 0 HyperTransport 0010 01pnnn Write from port p 1 PCI 0 HyperTransport 0010 10pnnn Read modify write i e partial line write from port p 1 PCI 0 HyperTransport Bridge 1 0011 00pnnn Read from DMA engine p 1 Se...

Page 110: ... One bit set 11000000 00110000 00001100 00000011 The half word can be identified from the encoded enables Uncacheable lw sw One bit set 11110000 00001111 The word can be identified from the encoded enables Uncacheable ld sd One bit set 11111111 The double word can be identified from the A_DW code Uncacheable lwl lwr swl swr One bit set 1 4 bits set The bytes can be identified from the encoded enab...

Page 111: ...C The trace logic connects to many other parts of the SCD Figure 11 shows these connections Figure 11 Connections to Trace Logic System Events ZBbus Address Traps Performance Counters Interrupt Mapper Debug Pin Trace Events Trace Sequences JTAG Trace Buffer JTAG CPU Interrupts Capture Full CPU Debug Freeze Match Trace Interrupt Interrupt Trace Overflow Match M atch Counted ...

Page 112: ...the A sample bit could be set on this sequence to record the dummy access if a separator was required When the trace buffer is full the trace_cfg setting causes it to freeze and raise an interrupt CPU0 would service this interrupt and with as little cache disturbance as possible read out the trace into a bigger in memory buffer At the end of the ISR the trace buffer is reset and started it must ha...

Page 113: ...e MAC to the buffer memory It does this by detecting a transfer on the data bus where the data source in the resp_id field and the initiator of the transaction in the data_id field are the same This is enough to detect that some write data is in flight from the I O bridge The seq2 sequence will first need trace1 to detect the write request to the buffer addresses before looking at trace2 to detect...

Page 114: ... This detects any write data from the CPU it is used in sequence with trace0 to detect this particular write If the transaction is a read then trace3 detects the data returning from the I O bridge in response to the CPU request the I O space read is uncacheable and the CPU only has one outstanding so in sequence with trace0 this always catches the correct data Master mode accesses from the PCI are...

Page 115: ...User Manual BCM1250 BCM1125 BCM1125H 10 21 02 Broadcom Corporation Document 1250_1125 UM100CB R Section 4 System Control and Debug Unit Page 87 This Page is left blank for notes ...

Page 116: ...BCM1250 BCM1125 BCM1125H User Manual 10 21 02 Broadcom Corporation Page 88 Section 4 System Control and Debug Unit Document 1250_1125 UM100CB R This Page is left blank for notes ...

Page 117: ...ncorrectable errors result in UNPREDICTABLE data being returned to the requestor with an uncorrectable tag error signalled Data with uncorrectable errors will be returned to the requestor with an uncorrectable data error signalled In either error case software recovery is required The bus watcher in the SCD will log the data associated with the error and raise an interrupt The L2 will record the t...

Page 118: ... the TLB with one of the cacheable coherent no L2 attributes codes 0 and 1 which will cause all blocks in the page to be accessed with the L2 allocate flag clear Alternatively the pages can be marked with the usual cacheable coherent attributes codes 4 and 5 and the PREFetch instruction with a streaming hint can be used to access individual lines around the L2 cache In the second case since the bl...

Page 119: ...ccur in one way of the cache On parts with system revision indicating PERIPH_REV3 and later the register can be read back from the l2_misc_value register Figure 12 Level 2 Cache Way Disable Access Address The memory removed from the cache must always be accessed as cacheable space Cacheable transfers are always done as full blocks and the L2 cache always operates on full cache lines Writes smaller...

Page 120: ...l MEMORY LOCKED IN THE L2 CACHE The second method for using the L2 cache as a controlled memory is to lock data into it The L2 is initialized with the data from main memory before the way is removed from the replacement algorithm then any accesses to those main memory addresses will always access the L2 cache This scheme is more complicated to set up and care must be taken that the addresses to be...

Page 121: ...me this is not a burden for I O devices doing DMA since the coherence protocol will ensure the most up to date copy of the data is returned for a DMA read and the latency is about the same regardless of whether the data comes from the L1 or L2 cache In cacheable space the CPU will only do full 32 byte block reads to fill the L1 cache line and full 32 byte block writes when a line is evicted from t...

Page 122: ... L2 cache there is a management mode This is used to invalidate the cache when the system is reset and is used during recovery from uncorrectable ECC errors It can also be used to force dirty lines to be flushed from the L2 cache however this should never be necessary in normal operation There are two memory mapped registers associated with the management mode Performing cache operations using the...

Page 123: ...are used as tag bits in 256 KB and 128 KB cache configurations 18 17 Way These bits select which of the four lines in a set are accessed During management writes these address bits are written to the tag 19 Dirty The dirty bit indicates that the line held in the L2 cache contains more recent data than the block in main memory If this bit is set the block must be written back to memory before the l...

Page 124: ...tim if one is needed on the next cache access note this is the next access not the next miss Therefore a line can be flushed from the cache by doing a management read of the line to be flushed followed by a regular cacheable read of a block that uses the same index and is not currently in the L2 The management access selects the way as the victim for the subsequent fill To avoid the line being flu...

Page 125: ...g add zero before reading the tag register There is no ordering problem if the management access is done using an uncacheable read because the CPU will maintain the order between the management access and the l2_read_tag register but uncached access is less efficient if all the data in the line needs to be examined Management writes will write the data to the addressed index and way The data is wr...

Page 126: ...r the test along with the data ECC bits to be used for the test The second write an ECC diagnostic write of type 2 b01 replaces only the actual data If the data of the second write differs by a single bit from the data in the first write a subsequent standard read will get the data from the first write flagged with a corrected ECC error If the second write had two bits difference the subsequent re...

Page 127: ...rk on the BCM1250 and BCM1125 H using 4096 sets It could be optimized for the BCM1125 H to only clear 2048 sets Save the old status register and set the KX bit This allows 64 bit addressing through xkphys mfc0 t2 C0_SR or t1 t2 M_SR_KX mtc0 t1 C0_SR Start the index at the base of the cache management area but leave the address bit for Valid zero Note that the management tags are at 00_D000_0000 wh...

Page 128: ...56KB or 512KB cache and is a tag bit in a 128KB cache 16 Tag bit 40 holds index bit 16 in a 512KB cache and is a tag bit in a 256KB or 128KB cache 38 17 Tag bits 39 0 45 40 Tag ECC raw 47 46 Way 48 Dirty 49 Valid 59 50 Data ECC raw 63 60 Reserved Table 57 Level 2 Cache Settings Register Bits l2_misc_value 00_1004_0058 READ ONLY Sytem Revision PERIPH_REV3 and later only 3 0 Cache quadrant informati...

Page 129: ...User Manual BCM1250 BCM1125 BCM1125H 10 21 02 Broadcom Corporation Document 1250_1125 UM100CB R Section 5 L2 Cache Page 101 This Page is left blank for notes ...

Page 130: ...BCM1250 BCM1125 BCM1125H User Manual 10 21 02 Broadcom Corporation Page 102 Section 5 L2 Cache Document 1250_1125 UM100CB R This Page is left blank for notes ...

Page 131: ...CRAM Fast Cycle RAM which is designed to be mounted on the main board These parts have smaller rows and a much simplified command set allowing them to have both faster cycle times and lower access latency than standard DDR Each channel can support up to 1 GByte of memory using 256 Mbit technology parts As larger DRAMs become available this will increase to 2 GByte with 512 Mbit parts and 4 GByte w...

Page 132: ... entries are allocated in both the RQQ and the DBF Entries are normally added to the RQQ in sequential order However checks are first done to detect any write to read or write to write address dependencies The RQQ holds the memory access information and initially the DBF is empty If the request is a write then the request is not ready for submission to the memory until the data has been received f...

Page 133: ...om I O bridge 1 are given priority and are issued in order If a read request conflicts with an existing write the write is also given priority If a channel is currently doing a read all reads to that channel will be issued ahead of any writes If a read has been bypassed enough times to reach its age_limit see below it will go ahead of other reads If a channel is currently doing a write all writes ...

Page 134: ...ass the read to the closed page To limit the length of time the read to the closed page is blocked the controller limits the number of reads that may pass it Every time a read is bypassed its age is incremented when it reaches the age_limit no new entries will be permitted to pass it and it and any entries ahead of it will drain from the queue The age_limit is set per channel in the mc_config regi...

Page 135: ...he CPU has no way of knowing when they complete If the CPU needs to both place a memory barrier and be informed of the completion then a read may be done to one of the controller configuration registers If the CPU performs a write of A to address 1 followed by a read of the mc_test_ecc register and finally a write of B to address 2 then A is always written to memory before B and when the CPU sees ...

Page 136: ...125 0 450 225 50 0 56 3 64 3 75 0 90 0 112 5 400 200 44 4 50 0 57 1 66 7 80 0 100 0 Table 58 Clock Speed Cont CPU Clock ZBbus Clock Memory Clock 4 5 1 Memory Clock 4 1 Memory Clock 3 5 1 Memory Clock 3 1 Memory Clock 2 5 1 Memory Clock 2 1 Table 59 Percent Deltas from Popular DIMM Frequencies CPU Clock ZBbus Clock 133 MHz DIMM Clock 143 MHz DIMM Clock 166 MHz DIMM Clock 183 MHz DIMM Clock 200 MHz ...

Page 137: ...ere is only one chip select this must be configured to have a single address range But the physical address map has one 256 MB memory block starting at zero which contains the CPU exception vectors and must be present and the next 256 MB block starts at 00_8000_0000 If the memory controller used physical addresses there would not be a way to configure the address range to use the whole DIMM Howeve...

Page 138: ... the lower row bits This increases the possibilities for having active banks In this configuration the channel must be assigned a contiguous memory address range and each chip select covers the same memory size mixed_CS allows interleaving between a pair of chip selects either CS 0 and CS 1 or CS 1 and CS 2 or CS 2 and CS 3 and allows the others to be set using their start and end registers This m...

Page 139: ...our chip select regions are interleaved interleaved_cs mode their start address registers must be set to the start of the common range and their end address registers are set to the end address of the common range plus 1 i e they are programmed identically to a range four times the size of one of them The address bits that selects between the two chip selects is configured by writing two ones in a...

Page 140: ... error or UNPREDICTABLE data being returned depending on the setting of the berr_disable bit in the mc_config register Figure 16 Example Single Channel 128MB Using the 512Mb memory technology and using 8 or 9 with ECC 64Mx8 allows each chip select to have 512MB of memory Two physical banks will therefore allow a 1GB memory system to be built There are three interesting configurations two on the BC...

Page 141: ...hip selects on one channel Channel 0 chip select 0 bank2_map bank1_map bank0_map Expansion space Physical Address used by CPU and DMA MC Address Space only used for MC configuration 00_0000_0000 00_1000_0000 00_8000_0000 00_9000_0000 00_A000_0000 00_C000_0000 00_D000_0000 01_0000_0000 80_0000_0000 FF_FFFF_FFFF First SDRAM Peripherals Second SDRAM Third SDRAM Reserved Fourth SDRAM Peripherals L2 mg...

Page 142: ...ch channel This doubles the number of data bits in use since the controller can run both channels in parallel allowing twice the peak bandwidth Channel 0 chip select 0 bank2_map bank1_map bank0_map Expansion space Physical Address used by CPU and DMA MC Address Space only used for MC configuration 00_0000_0000 00_1000_0000 00_8000_0000 00_9000_0000 00_A000_0000 00_C000_0000 00_D000_0000 01_0000_00...

Page 143: ... Big Memory mode see Section Larger Memory Systems on page 124 will also face this issue even when using lower density memory parts The 2GB problem can be solved with a little help from software The hardware is configured in a way that creates an alias of the low 1GB of memory which software should ensure is never used for example by the virtual physical address translation in the TLB Rather than ...

Page 144: ...only allows DMA access to the low 256MB from the PCI or from 32 bit addressing peripherals bridged from the HT interface since the DMA and CPU accesses must use the same physical range PCI accesses translated by the BAR0 map could be used Figure 20 Example 2GB with two chip selects interleaved on one channel Channel 0 chip select 0 bank2_map bank1_map bank0_map Expansion space Physical Address use...

Page 145: ...r bit wide devices are not supported The maximum size is therefore achieved using four physical banks of 8 or 9 with ECC eight bit wide devices Using 256Mb technology parts this limits the total size to 1GB per channel or 2GB total Using 512Mb parts this doubles and will double again when the 1Gb DDR parts come out reaching the theoretical maximum of 8GB The memory controller can use fast DDR part...

Page 146: ... by the device Example masks are shown in Table 62 The bank is selected from the lowest bits the column next and the row from the upper bits Note that the column masks need not have bits 4 3 set these address bits are always used as the low column bits One problem with this example is that the internal bank is switched every cache line so streaming data that transfers in 64 byte blocks for example...

Page 147: ...rleave between the physical banks This is shown in Table 66 Table 64 Example for 128 MByte CS Region with 4K Rows 1K Columns 128 Byte Interleave Row Address Bits 26 15 Column Address Bits 14 9 6 5 4 3 Bank Address Bits 8 7 Row 00000000_00000111_11111111_10000000_00000000 Column 00000000_00000000_00000000_01111110_01100000 Bank 00000000_00000000_00000000_00000001_10000000 Table 65 Example for 256 M...

Page 148: ...st important but maximum access latency may also be important Some things e g a faster memory clock will improve all of them but many of the options improve one at the expense of others In particular reductions in average memory latency are often at the expense of increasing the maximum latency In most cases the system will use more than one physical bank of memory These can be put on different ch...

Page 149: ...The system performance will be improved by interleaving the channels and thus removing the hot spot and allowing the bandwidth to be shared more evenly A good general starting point applies the principle from the previous examples keep a few cache lines contiguous to allow for page mode accesses then use low bits to interleave across the two channels the internal banks within a device and the phys...

Page 150: ...e there is a good chance the page will be open when required The Hint Based policy is the same as the CAS time check except that it accepts a hint with each memory request The hint is part of the command on the ZBbus and will be asserted by the DMA engines PCI and HyperTransport interfaces when doing block moves If the hint is set on a request then even if there are no more requests the page is le...

Page 151: ... the third bank address bit This is enabled if three bits are set in the bank address selection register For regular SDRAMS if the ram_with_A13 bit is set in the mc_drammode register the BA 2 is brought out on the A13 pin and A12 reverts to being a row address DDR FCRAMs Memory channels can be configured to use FCRAMs These require two extra row address bits and use a function FN flag to distingui...

Page 152: ...a board using the large memory extension The extension works by configuring the memory controller to only use two chip selects and driving two additional address bits on the other two chip select outputs Externally each of the chip selects is used to enable a 2 to 4 decoder to generate the actual chip selects for the physical memory banks the delay through the decoder must be taken in to account w...

Page 153: ...ta will be written back into the memory They will continue to occupy the RQQ entry until the data has been written Thus a memory location should not return multiple single bit ECC errors Double bit errors are left as such so repeated reads of the data will continue to give the error ECC checking can be disabled either to support non ECC DIMMs or during memory testing The memory controller can be s...

Page 154: ...ter holds the data to be encoded on address lines A 11 0 for standard DDR parts and A 14 0 for FCRAMs Table 69 Commands that can be Issued Through mc_dramcmd Register Name Command Description EMRS Write Extended Mode Register Write the value in the mc_drammode register to the Extended Mode Register in the selected parts MRS Write Mode Register Write the value in the mc_drammode register to the Mod...

Page 155: ...r for Normal Operation appropriate CAS latency Sequential burst and burst length of 4 MRS 8 Once 200 memory cycles have passed since the DLL was reset the SDRAM is ready for normal operation The reset initialization sequence is different for FCRAM from regular DDR parts The memory controller will not release the enable CKE when the PDN_clr command is used to start the clock but waits for a PRE com...

Page 156: ...ower loading and when non standard termination is used IMPORTANT The rest of this description explains the DLLs for the BCM1250 and BCM1125 H where the system_revision indicates PERIPH_REV2 or later The address DLL was organized differently on the early access prototype pass 1 parts marked BCM12500 please see an earlier revision of this User Manual for description of those parts An internal master...

Page 157: ...position the delayed DQS at the center of theoretical data window The DLL can be adjusted about 8 75 of the memory cycle or 35 of the quarter cycle either side of this point The second use of the DLL is to position the address and data signals relative to the memory clock This is done by driving the data address control from a fixed internal clock and using the DLL to move the external Mn_CLK with...

Page 158: ...is about 34 of the cycle time with dqo_skew set to 4 b1111 The second and third uses of the DLL interact to set the position of the DQS output relative to the clock The difference between the addr_skew and dqo_skew controls this delay if they are set to the same value the strobe will line up with the clock The early DQS shown by t2 results from the addr_skew being set to M 4 b1111 and dqo_skew to ...

Page 159: ... must start looking for the DQS before the earliest DQS returns 3 The data must not be read from the latch before the byte with the latest DQS has been written and allowed to settle Taken together these constraints fix the window in which the first DQS of each byte lane must be received at the controller The tCrD tCrDh and tFIFO parameters in the mc_timing1 register describe this window As a start...

Page 160: ...L arrangement in those parts increasing dqo_skew will move the window to the left Increasing the value of dqi_skew will move the windows to the left this is true on all parts The positions of the windows are also affected by the settings of the clock_class and clock_drive parameters in the memory clock configuration register The windows in the figure are shown for clock_class 1 and clock_drive 7 i...

Page 161: ...ed 1 1 2 window Most systems will likely want to use one of the following settings n 0 1 for whole cycle CAS latencies and relatively short board delays n 0 2 for whole cycle CAS latencies with moderately long board delays n 1 2 for half cycle CAS latencies Due to a performance bug systems with half cycle CAS latencies using BCM1250 pass 1 prototype parts should use n 0 2 if possible There are thr...

Page 162: ...f nominal no conflict time is reduced by the DQS delay between the two physical banks Therefore it is unlikely that a system will require a non zero value of the r2rIdle parameter To summarize most systems using half cycle CAS latency will set r2wIdle to a 1 w2rIdle to a 1 and r2rIdle to a 0 Systems using SDRAMs with a whole cycle CAS latency will set r2rIdle to 1 and the other parameters to 0 Sys...

Page 163: ...rs set a range to give hysteresis to the blocking mc_config_0 Queue size to start blocking agents other than IOB1 mc_config_1 Queue size to stop blocking agents other than IOB1 47 44 age_limit 4 h8 Maximum number of younger reads that can pass a read in the request queue before the read is serviced See Section Memory Controller Architecture on page 104 51 48 wr_limit 4 h5 Maximum number of writes ...

Page 164: ... h8 mc_config_1 Value of physical address bits 31 28 that should map to 1 2nd 256MB block mc_config_0 Reserved 27 24 bank2_map 4 h9 mc_config_1 Value of physical address bits 31 28 that should map to 2 3rd 256MB block mc_config_0 Reserved 31 28 bank3_map 4 hC mc_config_1 Value of physical address bits 31 28 that should map to 3 4th 256MB block mc_config_0 Reserved 39 32 probe_mode 8 b0 mc_config_1...

Page 165: ... Tthe interleaving occurs between CS2 and CS1 determined by one bit of the interleaved CS position register The values of the CS 2 1 start end 1 addresses are the same 0011 Mixed CS mode CS 3 and CS 2 are not interleaved and determined by the corresponding start end 1 addresses The interleaving occurs between CS1 and CS0 determined by one bit of the interleaved CS position register The values of t...

Page 166: ...ld be clear to have the clock drivers configured for SSTL_2 Class 1 operation and set for SSTL_2 class 2 22 20 data_drive 3 b0 This sets the drive strength and therefore slew rate of the output drivers for the data lines 0 gives the weakest drive slowest slew rate and 7 the hardest See Section I O Control on page 128 23 data_class 1 b0 This bit should be clear to have the data drivers configured f...

Page 167: ...erted when the command is issued 6 cs2 If this bit is set cs2 is asserted when the command is issued 7 cs3 If this bit is set cs3 is asserted when the command is issued 63 8 reserved Reserved Table 76 DRAM Mode Register mc_drammode_0 00_1005_1140 mc_drammode_1 00_1005_2140 Bits Name Default Description 12 0 emode 15 b0 This value is written to the Extended MODE register via the address lines when ...

Page 168: ...ge Default Description 3 0 tRCD 1 6 4 h3 RAS to CAS delay This should be set to 1 for FCRAMs 6 4 tCrD 1 6 3 h2 Cycles from CAS read to data the CAS latency 7 tCrDh 0 1 1 b0 If this bit is set the data capture is delayed by a half cycle from the integer part of the CAS latency set in tCrD See the discussion in Timing Parameter Guidelines on page 131 11 8 tCwD 1 2 or 1 4 4 h1 Delay from CAS to Write...

Page 169: ...05_1180 mc_timing2_1 00_1005_2180 Bits Name Description 63 0 reserved Reserved Table 79 Chip Select Start Address Register mc_cs_start_0 00_1005_11A0 mc_cs_start_1 00_1005_21A0 Bits Name Default Ch0 Default Ch1 Default Ch1 BCM1125 H Description 15 0 cs0_start 16 h0000 16 h0100 16 h0000 Chip select 0 1 2 3 region start address bits 39 24 These address are in the memory address space after the trans...

Page 170: ...000111_11111111_10000000_00000000 9 0 reserved Reserved 34 10 select Address bits are selected for use as the row address by setting the corresponding bits in this register The number of bits set should match the number of rows of the SDRAM The set bits must be contiguous 63 35 reserved Must be zero Table 83 Column Address Bits Select Register mc_cs0_col_0 00_1005_1220 mc_cs1_col_0 00_1005_1280 mc...

Page 171: ...SDRAM The set bits must be countiguous 63 37 reserved Must be zero Table 85 Chip Select Attribute Register mc_cs_attr_0 00_1005_1380 mc_cs_attr_1 00_1005_2380 Bits Name Default Description 1 0 cs0_page 2 b01 Page policy for Chip Select 0 See Section Page Policy on page 122 00 Closed Page AutoPrecharge every CAS 01 CAS time check AutoPrecharge unless there is another request in the queue 10 Hint Ba...

Page 172: ..._1 00_1005_2400 Bits Name Default Description 63 0 invert 64 h0 This value is XORed with the data written to memory Any bits set in this register will cause the corresponding data bit to be inverted compared to the data the ECC bits were calculated for If only one bit is set a correctable ECC error should result from a read If two bits are set an uncorrectable ECC error should result from a read T...

Page 173: ...User Manual BCM1250 BCM1125 BCM1125H 10 21 02 Broadcom Corporation Document 1250_1125 UM100CB R Section 6 DRAM Page 145 This Page is left blank for notes ...

Page 174: ...BCM1250 BCM1125 BCM1125H User Manual 10 21 02 Broadcom Corporation Page 146 Section 6 DRAM Document 1250_1125 UM100CB R This Page is left blank for notes ...

Page 175: ...ial interfaces are generated by appending _ser_N_rx and _ser_N_tx for serial interface N 0 1 There is an additional generic Data Mover for doing transfers between arbitrary addresses both memory and I O can be addressed This is similar in style to the other DMA controllers but has a slightly different programming interface since it needs to support both source and destination addresses The general...

Page 176: ...Mover does not use the size field the buffer length matches the length parameter described below Owner The data buffer is either owned by one of the DMA controllers or by the system software Ownership is not explicit each DMA controller has a count of the number of descriptors it owns and will use all buffers pointed to from those descriptors Software needs to keep track of the buffers and must up...

Page 177: ...the CPU Figure 24 DMA Descriptor The descriptor also has three control bits If the INT bit is set then the DMA channel will raise an interrupt when it has completed processing of the descriptor The second control bit indicates if the buffer B details are valid if this bit is clear the descriptor only has one associated buffer and the buffer B details are ignored they are preserved when the status ...

Page 178: ...dress Offset in bytes size in cache blocks L1 in bytes Aligned to 32 byte block Aligned to 32 byte block Packet Start Address Offset in bytes size in cache blocks L2 in bytes Aligned to 32 byte block Aligned to 32 byte block Unused Start Address Offset in bytes size in cache blocks L3 in bytes Aligned to 32 byte block Aligned to 32 byte block Length L1 L2 L3 in bytes Packet ...

Page 179: ...to 65536 descriptors The DMA controller keeps track of its current position in the ring initially the base Software passes ownership of descriptors and the associated pair of buffers to the controller by incrementing the count of the number of descriptors owned by the controller Writing to the count register adds the value written to the current count The software may write the register at any tim...

Page 180: ...s is that the SOP bit is cleared this can be used by software to detect the packet transmission has completed If software does not make use of this feature the bandwidth used for descriptor management through the I O bridge and thus the latency for other accesses can be reduced by disabling writing back the transmit status In the Ethernet DMA engine the SOP bit must always be set for the descripto...

Page 181: ...oftware will place the next descriptor when the count reaches zero the controller will remember the link value and fetch the new descriptor from that address when the count becomes non zero In both ring and chain modes reading the dma_cur_dscr_addr register gives address of the descriptor currently being processed and the current count of descriptors owned by the controller If the count field in t...

Page 182: ...s is in the standard format Note that the descriptor field must be set to the size of the data plus the low 5 bits of the start address so the maximum buffer size for arbitrary alignment is 16K 32 bytes The a_size field is not used and can therefore always be used for the optional extra status information No B Buffers are available Only Ring mode can be used The Packet Length Status Interrupt and ...

Page 183: ...ribute The channel configuration sets how many blocks from the start of a packet should be marked for allocation in the L2 cache this can be set larger than the maximum packet size to have complete packets sent to the cache The L2 is still being used as a cache the data still has a memory address and can be evicted from the cache to memory if the L2 replacement algorithm requires it The network an...

Page 184: ...head While the hardware does support buffers as small as 32 bytes and these may be ideal as header buffers the system becomes more efficient as the buffer size is increased In the transmit channel the tbx_en bit should be set in the dma_config0 register to allow the controller to prefetch buffer data whenever possible If this bit is set the controller will mostly fetch pairs of cache blocks back t...

Page 185: ...DMA channels are combined into the mac_status register for the interface see Table 182 on page 310 The serial interface transmit and receive channel status are combined into the ser_status register for each channel that can be read to determine the interrupt cause see Table 240 on page 357 Reading the status will clear all bits in the status register and clear the interrupt DESCRIPTOR COUNT WATERM...

Page 186: ...t count is set to one then an interrupt will be raised after every packet Since this can swamp the system with interrupts the count would typically be set higher and the receive interrupt service routine will be written to accept a batch of packets In order to avoid imposing a high delay before packets are serviced when they are arriving at a low rate the interrupt can also be raised by a timer Th...

Page 187: ...s are fetched for each packet Rather than sending the packet header to the first buffer in the descriptor the packet is directed to the address range set in the dma_asic_addr register The asicxfr_size is set to the number of cache lines of the packet that should be sent to the ASIC if there is an offset specified this is one less than the maximum number of cache lines that should be sent to the AS...

Page 188: ... address for a 1 MB region of memory The first cache block in a packet with the descriptor prepended if enabled will be sent to the Start Of Packet SOP address subsequent blocks are sent to the Middle Of Packet MOP address range and the last cache block in the packet will be set to either the End Of Packet EOP address or the EOP Error address The block sent to the EOP address may contain less than...

Page 189: ... next descriptor will be fetched for the next packet so the B buffer is never used The ASIC can process the packet and write data back to memory at the address given in the prepended dscr_a The ASIC needs a way to inform the CPU that its processing is complete The DMA controller will generate the end of packet or completion or watermark interrupt when it has sent the full packet to the ASIC and ha...

Page 190: ...nds the rest of the packet into memory in the normal way when it is done it will write the length and flags back into the descriptor The ASIC can perform its header processing and write results and the header back using the buffer A address If CPU intervention is required an ASIC on the HyperTransport fabric could opt to write the results and header back with HyperTransport Isochronous writes whic...

Page 191: ...t to enable interrupt at end of packet The interrupt will be generated when the number of packets specified in int_pktcnt have been received or if the receive interrupt timer has timed out See Section Completion Interrupts on page 158 4 hwm_int_en 1 b0 Set to enable an interrupt when the number of descriptors owned by the DMA controller falls below the high watermark 5 lwm_int_en 1 b0 Set to enabl...

Page 192: ...ent to the ASIC 3 flow_ctl_en 1 b0 Set to cause the controller to send a flow control request to the interface when the descriptor count falls below the low watermark and only remove the request when the count goes above the high watermark MAC receive channels only setting this bit in other channels causes UNDEFINED behavior 4 no_dscr_updt 1 b0 Set to prevent the descriptor being written with the ...

Page 193: ...et The number of cache lines sent to the ASIC will be Offset zero The number in this field If this field is zero then one cache line is transferred Offset nonzero One greater than the number in this field 47 46 reserved 2 b0 Reserved 63 48 int_timeout 16 b0 This field sets the timeout for interrupt generation See Section Completion Interrupts on page 158 If this field is zero then timing of the as...

Page 194: ...ma_asic_addr_mac_1 00_1006_5418 dma_asic_addr_mac_2 00_1006_6418 dma_asic_addr_ser_0 00_1006_0598 dma_asic_addr_ser_1 00_1006_0998 Bits Name Default Description 19 0 zero 20 b0 These bits must be zero 39 20 base 36 b0 This is the base of the ASIC address space 64 40 reserved 24 b0 Reserved Table 95 Descriptor Count Register dma_dscr_cnt_mac_0_rx_ch_0 00_1006_4818 dma_dscr_cnt_mac_0_tx_ch_0 00_1006...

Page 195: ...c_2_rx_ch_0 00_1006_6828 dma_cur_dscr_b_mac_2_tx_ch_0 00_1006_6C28 dma_cur_dscr_b_mac_2_rx_ch_1 00_1006_6928 dma_cur_dscr_b_mac_2_tx_ch_1 00_1006_6D28 dma_cur_dscr_b_ser_0_rx 00_1006_0428 dma_cur_dscr_b_ser_0_tx 00_1006_04A8 dma_cur_dscr_b_ser_1_rx 00_1006_0828 dma_cur_dscr_b_ser_1_tx 00_1006_08A8 READ ONLY Bits Name Default Description 63 0 cur_b 64 b0 The current descriptor second double word ca...

Page 196: ...c_1_tx_ch_1 00_1006_5D30 dma_cur_daddr_mac_2_rx_ch_0 00_1006_6830 dma_cur_daddr_mac_2_tx_ch_0 00_1006_6C30 dma_cur_daddr_mac_2_rx_ch_1 00_1006_6930 dma_cur_daddr_mac_2_tx_ch_1 00_1006_6D30 dma_cur_daddr_ser_0_rx 00_1006_0430 dma_cur_daddr_ser_0_tx 00_1006_04B0 dma_cur_daddr_ser_1_rx 00_1006_0830 dma_cur_daddr_ser_1_tx 00_1006_08B0 READ ONLY Bits Name Default Description Table 99 Ethernet Receive P...

Page 197: ...n The flags differ between the interfaces and are described in Section Option and Flag Bits for Ethernet MACs on page 171 and Section Control and Flag Bits for Synchronous Serial Interface on page 174 Table 101 DMA Descriptor Second Doubleword dscr_b Bits Name Description 3 0 options This field sets the per packet options that are sent to the interface The options depend on the channel and are out...

Page 198: ...e per packet options that are sent to the interface The options depend on the channel and are outlined below 7 4 reserved Reserved 21 8 size This field specifies the buffer size in bytes This field must be set to the number of bytes of data in the buffer plus bits 4 0 of the start address in the dscr_a addr field The DMA engine behavior is UNPREDICTABLE if this size is set to be less than the valu...

Page 199: ...for Ethernet and Packet Fifo modes 54 53 rx_ch Receive channel number always 2 b00 for DMA channel zero This field is valid for Ethernet and Packet Fifo modes 57 55 pkt_type Packet type Contains an encoded version of the Ethernet Type field See Section Packet Type Identification on page 282 This field is valid for Ethernet and Packet Fifo modes It depends on the packet format so it may not be usef...

Page 200: ... operation and the vlan_det_en bit is set in the mac_adfilter_cfg register This bit will be set when a packet with a VLAN tag is received and clear if there is no VLAN tag 2 crc_flag This bit is only valid if the system revision indicates PERIPH_REV3 or greater Ethernet mode only this flag is set in addition to the bad bit when a CRC error is detected 3 reserved This bit may be used for status inf...

Page 201: ... VLAN tag and replace CRC 0111 No Modifications 1000 Reserved 1001 Replace source address and append CRC 1010 Replace source address and replace CRC 1011 Replace source address append CRC and pad 1100 Replace source address append VLAN tag and replace CRC 1101 Replace source address remove VLAN tag and replace CRC 1110 Replace source address replace VLAN tag and replace CRC 1111 Reserved Descripto...

Page 202: ...his bit is set to indicate the start of the packet Software should ensure this bit is clear when it sets up the descriptor the DMA controller will only set it when packet reception has been completed Table 109 Option Flags for Synchronous Serial Receive Channel Receive Options Bits Name Description None Table 110 Status Flags for Synchronous Serial Transmit Channel Transmit Status Flags Bits Name ...

Page 203: ...User Manual BCM1250 BCM1125 BCM1125H 10 21 02 Broadcom Corporation Document 1250_1125 UM100CB R Section 7 DMA Page 175 This Page is left blank for notes ...

Page 204: ...ource and destination addresses can be incremented decremented or held constant for each 32 byte block This allows movement of overlapping regions if the source address is less than the destination the data should be moved from the top end of the buffer with both addresses decrementing if the source address is greater then the data should be moved starting at the bottom of the region and increment...

Page 205: ... sharing of the data mover software should break down large transfers into a series of smaller transfers to enable finer granularity on the round robin The data mover descriptors include an interrupt bit If this is set then when the transfer specified in the descriptor is complete the interrupt bit will be set in the dm_dscr_base register and the channel interrupt will be raised If an error is fla...

Page 206: ...s control of the DMA channel and in many cases can be avoided since a different computation can be performed in other channels The data in the partial result register is only valid when the channel is not currently computing a checksum or CRC and the register should only be written when the channel is not computing If the data mover channel is disabled then the CRC and checksum partial result regi...

Page 207: ...he crc_partial register For an 8 bit CRC the width is set to 8 the polynomial must be placed in the upper byte 63 48 of the crc_poly field the initial value will come from the upper byte 31 24 of the crc_init field and the partial result will be in the upper byte 31 24 of the crc_partial register For other CRC widths the next larger output field width should be used and the CRC result will be in t...

Page 208: ...iSCSI where the CRC is internal to the TCP payload The number of bytes appended will be 1 2 or 4 to match the field width of the CRC If required a read modify write is done Note that when a checksum is appended it is not included in the CRC When the prefetch flag is set no data will be moved and the destination address is used just to write the CRC if the append flag is set If the Prefetch flag is...

Page 209: ...bytes in the TCP header The pseudo header sum is included this takes advantage of the fact that the order of the adds does not matter The second descriptor adds the first data block and the third descriptor the second data block Because the Prefetch flag is set the buffers are only read and no copy is made The third descriptor has the Append CS flag set so the destination address is used to write ...

Page 210: ...al data move could do a single doubleword copy of the value 1 to the MAC DMA descriptor count register using an uncached destination to ensure only one doubleword is written This is a somewhat inefficient use of the data mover but has offloaded the CPU from fielding the datamover interrupt and writing the MAC register Example 3 illustrated in Figure 35 on page 183 shows preparing a large iSCSI blo...

Page 211: ...tware before the data mover were started then rather than having the TCP checksums written to an array the Append CS would be removed from the second and third descriptors and additional descriptors inserted after the second and third and to replace the final one These descriptors would have the CRC disabled and would add and append the TCP sum in the same way as the third descriptor in example 2 ...

Page 212: ...a read from the dm_dscr_base register 61 error R O reset W O 1 b0 On a read this bit is set when the channel is interrupting because of a data transfer error uncorrectable ECC Bus Error or Fatal bus error signalled on the D_CODE If such an error occurs the channel will abort This bit is cleared by a read from the dm_dscr_base register If this bit is written with a 1 the current descriptor pointer ...

Page 213: ...2_0B50 dm_cur_dscr_addr_3 00_1002_0B70 READ ONLY Bits Name Default Description 39 0 dscr_addr 40 bx The current descriptor address can be read from this field 47 40 reserved 8 b0 Reserved 63 48 cur_count 16 b0 The current count of descriptors owned by the DMA engine can be read from this field Table 118 Data Mover CRC Definition Registers Only if System Revision PERIPH_REV3 crc_def_0 00_1002_0B80 ...

Page 214: ...ved 13 bx Reserved Table 120 Data Mover Channel Partial Result Registers Only if System Revision PERIPH_REV3 dm_partial_0 00_1002_0BA0 dm_partial_1 00_1002_0BA8 dm_partial_2 00_1002_0BB0 dm_partial_3 00_1002_0BB8 Bits Name Default Description 31 0 crc_partial 32 bx Current partial CRC result After a transfer with the crc_ap append bit set this register will contain the final CRC result after XOR a...

Page 215: ...c address is 32 byte aligned 50 l2c_dest If this bit is set writes to the destination buffer are marked L2_cacheable and will therefore be allocated in the L2 on an L2 miss For cacheable transfers the L2 is always checked and will always be updated if hit 51 l2c_src If this bit is set reads from the source buffer are marked L2_cacheable and will therefore be allocated in the L2 on an L2 miss For c...

Page 216: ...ta Mover Descriptor Second Doubleword dm_dscr_b Bits Name Description 39 0 src_addr The source address of the transfer may be any alignment 59 40 length The length of the transfer in bytes If this field is zero then 2 20 bytes will be transferred 63 60 reserved Reserved Table 121 Data Mover Descriptor First Doubleword Cont dm_dscr_a Bits Name Description ...

Page 217: ...User Manual BCM1250 BCM1125 BCM1125H 10 21 02 Broadcom Corporation Document 1250_1125 UM100CB R Section 7 DMA Page 189 This Page is left blank for notes ...

Page 218: ...3 3V signal levels the interface is not 5V tolerant PCI special cycles dual address cycles and the LOCK protocol are not supported The interface can act as either the host bridge or as a device configured and controlled by another host These are referred to as Host Mode and Device Mode When operating in Host Mode an internal arbiter can be used providing support for four external PCI devices alter...

Page 219: ...che line writes The PCI and HyperTransport interface units implement their respective bus protocols and include additional data and command buffering The bandwidths of the connections between the I O bridge and interface units are sized appropriately for the interfaces so the HyperTransport is not constrained by the PCI bandwidths However the interfaces are presented logically to the system as if ...

Page 220: ...and HyperTransport are little endian A full discussion of the endian issues is in Section Endian Policies on page 201 the two endian options match bit lanes and match byte lanes are defined there All the areas for mapping PCI and HyperTransport devices except a HyperTransport only expansion area are put in the low 4 GBytes of the address space so they can be addressed using 32 bits of address in s...

Page 221: ...pt or EOI cycle Direct Mapped to 00_4000_0000 00_5FFF_FFFF with match bit lane endian policy PCI Memory Space Devices match byte lane HT Memory Space Devices with match byte lane endian policy PCI Memory Space Devices with match byte lane endian policy N M L K J I H HT Special Functions match byte lane has FD_2000_0000 added to address IACK Read Space match byte lane Run IACK cycle to Southbridge ...

Page 222: ...e policy HYPERTRANSPORT EXPANSION SPACE There is a large region of the address space allocated to HyperTransport expansion This is marked as region N in the address map above Figure 37 on page 193 This space is Reserved on the BCM1125 Use of this area requires the use of full 40 bit physical addresses Configuration software will also need modification to use this area by default it will attempt to...

Page 223: ...TIVE DECODE In most x86 systems there is a device called the Southbridge that connects to the PCI bus and provides the interface to a number of slow speed I O devices serial ports parallel ports keyboard mouse more recently USB and legacy buses normally the ISA bus it also contains the legacy interrupt controller often known as the PIC after the original Peripheral Interrupt Controller chip The in...

Page 224: ...ctive decode is only used for legacy devices it will only be used for I O addresses in the bottom of the range In this interface locations in the first 32 KB of the I O address space can only be used for the legacy subtractive decode devices This area is shown as region H in Figure 37 on page 193 Any access to this range will be directed according to the southOnLDT bit if it is set they will be se...

Page 225: ...baddr DFFF_FFFF endian zbaddr 29 match bit lanes match byte lanes if pcildtaddr 00_4100_0000 Note after a 29 removal if pcildtaddr 23 17 7 b0000101 0A_xxxx 0B_xxxx if Bridge Control VgaEn send pcildtaddr 00FF_FFFF to HT with COMPAT bit clear else send pciaddr 00FF_FFFF to PCI else if Southbridge is on LDT send pcildtaddr 00FF_FFFF to HT with COMPAT bit set else send pciaddr 00FF_FFFF to PCI else i...

Page 226: ...me is discussed in detail in Section HyperTransport Interrupts on page 48 which describes all the interrupts on the part The HyperTransport level sensitive interrupt messages require an End Of Interrupt EOI acknowledgement to clear them when the interrupt processing is complete This is sent as a broadcast message in the HyperTransport address range reserved for interrupt messages The interface all...

Page 227: ...CK cycle This is a byte read that returns the interrupt vector information The address map defines the region F in Figure 37 on page 193 for the CPU to read from to perform an IACK access the address is ignored and any access in this range has the same effect If the southOnLDT bit is set this gets run as a cycle on the HyperTransport to the special address range FD_F900_0000 FD_F90F_FFFF with the ...

Page 228: ...hould translate into a single HyperTransport request accesses that are 1 4 bytes translate directly to a Read sized Byte request and accesses that are an aligned number of 32 bit words translate to the Read sized Doubleword request The interface is able to split ZBbus reads into two HyperTransport requests allowing the 5 7 byte reads that the load doubleword left LDL and load doubleword right LDR ...

Page 229: ... will be used The address bit used to select the endian mode is zeroed as the request passes through the interfaces so that the target always see the match bytes address LITTLE ENDIAN SYSTEM NO SWAPS When the part is run as a little endian system there is no need to do any swapping between the system and PCI or HyperTransport If the system configuration register is set for little endian then no sw...

Page 230: ...ture of the PCI is exposed to the processor If a value is stored from a CPU register into a peripheral device register its bytes will be reversed Figure 39 Match Byte Lane Endian Policy If a sequence of bytes is moved through the interface the address of each byte is maintained so the order of the sequence is maintained between the PCI or HyperTransport device and memory Therefore this is the corr...

Page 231: ... these are forbidden by the HyperTransport specification for configuration accesses to the HyperTransport space and forbidden by the bridge for accesses to the PCI configuration registers If a byte access is performed the programmer will get the expected result for a big endian context i e the most significant bits of the register will be at the lowest CPU byte address Similarly a 16 bit access wi...

Page 232: ...an policy selection is as a way to optimize code This section considers the software viewpoint assuming a portable operating system is being used To summarize the issue The PCI HyperTransport bus and peripherals are little endian thus when storing a 32 bit value in a register the least significant byte i e bits 7 0 are assigned to the lowest memory address When an access is done from a big endian ...

Page 233: ...e in the internal or HyperTransport space The PCI controller has a type 0 device configuration header This allows for up to 6 BARs 5 are used when the interface is in Host Mode and 3 are used when the interface is in Device Mode In addition a PCI expansion ROM may be accessed through its special BAR Table 123 shows the BARs and the internal addresses that they map to In Host Mode they default to t...

Page 234: ...rnally this bit overrides the destination implied by the address so software must take care to set it correctly If the bit is set to send the request internally and the address is in the HyperTransport range the result is UNPREDICTABLE but in most cases a target abort error will be returned If the bit is set to send the access to the HyperTransport and the address is in the internal range then the...

Page 235: ...ess an expansion ROM with no setup required by the CPU preventing reset ordering problems The bottom bit of the BAR must be set to enable the region as required by the PCI specification Reads on the PCI do not explicitly indicate a length To optimize performance the PCI bridge will always prefetch a cache line i e do a read on the ZBbus with all byte enables set when a read to the part comes in fr...

Page 236: ... 2 An error is returned from a read request that has been sent to the ZBbus this will be logged by the Bus Watcher or to the HyperTransport interface this will be logged in the interface CSRs 3 The request hit in a BAR and targets the HyperTransport interface but the ptp_en bit in the Feature Control register is clear disabling peer to peer transfers from PCI to HT 4 The request hit in a BAR in pa...

Page 237: ... Mailbox CPU1 BAR 2 Mailbox CPU0 Unused BAR 0 Maps anywhere through Table Host Bridge Ignores Low Memory Match bit endian policy BAR 4 Low Memory Match byte endian policy 2000_0000 6100_0000 7000_0000 7100_0000 7200_0000 7300_0000 DRAM Maps to 00_D800_0000 00_DFFF_FFFF With match bit endian policy PCI HT I O Space HT PCI Special L2 Direct Access Fourth DRAM Region Third DRAM Region Second DRAM Reg...

Page 238: ... FF_FFFF_FFFF 80_0000_0000 00_0000_0000 FD_FE00_0000 Reserved NxA Configuration Registers Device 0 Function 0 FD_F900_0000 Reserved NxA Accept and forward to SCD FD_F800_0000 F1_0000_0000 Reserved NxA Send on PCI using lower 32 address bits E0_8000_0000 E0_0000_0000 MAP to 00_xxxx_xxxx and send on ZBbus Match Bytes send to PCI or HT southOnLdt bit Peer to Peer HT transfer If srcid nonzero send bac...

Page 239: ...ear The data is passed directly between the two interfaces regardless of system endian settings Only a single HyperTransport PCI read will be issued at a time The PCI interface will not respond to requests that it generates any access forwarded from the HyperTransport fabric that match a PCI address with destination inside the part will result in an error Requests that match the ZBbus space will b...

Page 240: ...ould be used to allow packet headers to be cached and bodies to be written to memory Note that bits 39 36 are always ignored in the comparison so that the Ex_xxxx_xxxx address will have the same L2CA behaviour as the 0x_xxxx_xxxx address that it maps to ACCESSING THE SIBYTE FROM A SIBYTE ON A DOUBLE HOSTED CHAIN The interface provides limited support for double hosted HyperTransport chains This is...

Page 241: ...o it Anything that matches a memory address will be accepted by the master The slave has an identical memory map so direct transactions will never reach it The Bounce space provides a way for the peripheral to bounce transactions to the slave via the master Any address received in the range F1_0000_0000 FB_FFFF_FFFF will be sent back out on the HyperTransport fabric with the address mapped to 01_0...

Page 242: ...eable reads outstanding The internal connections will maintain the order of reads and the SB 1 CPU supports multiple outstanding uncached reads to allow streaming There is one case where this can cause problems in the HyperTransport fabric due to the ordering of the chain or PCI with bridges using delayed reads reads to different devices may reach their destinations in a different order than they ...

Page 243: ...s will limit the performance Therefore in interface with RevId 3 or greater a prefetch mechanism is added If prefetching is enabled in the PCI Adaptive Extend Register then a full cache block ZBbus read will cause 2 or 4 cache blocks to be prefetched from the PCI This is particularly useful when the Data Mover is transferring a large block from the PCI If a read request from the ZBbus is for a ful...

Page 244: ...nsport interface and is inserted in the I O bridge queue Since it has become a posted write it may now pass reads An error response will never be generated Reads from the HyperTransport fabric pass through the queues and are sent onto the ZBbus The I O bridge interface can have 8 reads outstanding on the ZBbus including those from both PCI and HyperTransport When all 8 entries in the RDR buffer ar...

Page 245: ...bus unless the dis_memrd_be bit is set in the PCI Adaptive Extend register If this bit is set all memory space reads will have all four byte enables asserted the additional bytes received from the PCI will be ignored If the dis_memrd_be bit is clear then any access to the PCI greater than 4 bytes should be an aligned multiple of four bytes If the dis_memrd_be bit is set then any access may be safe...

Page 246: ...the adaptive policy will increase the retry delay to the maximum value This prevents the PCI throughput falling catastrophically when the system experiences a load slightly higher than was expected However if the memory latency becomes larger than the maximum the very high load box then the retry delay is set to its minimum value causing requests to be rapidly disconnected Once the overload has be...

Page 247: ...rt bridge header will be accepted from the PCI and forwarded to the HyperTransport fabric This forwarding is disabled by default and must be enabled in the Feature Control register offset h40 in the PCI configuration header In addition requests that match BAR0 and have an enabled mapping with the send_ldt bit set are forwarded to the HyperTransport the send_ldt bit overrides any destination implie...

Page 248: ...o HyperTransport Peer to Peer Accesses Peer to peer reads always assume the destination address is prefetchable this is required for performance since the PCI bus does not give a good indication of the transfer size at the start of the transaction Caution should be used when accessing registers using peer to peer operations The same algorithm is used as for reads to the ZBbus the PCI read is assum...

Page 249: ...s be posted to the PCI bus Non posted write requests will be acknowledged when they leave the HyperTransport interface Writes flow in their own channel from the HyperTransport interface to the PCI interface and may pass non posted reads Figure 48 Buffers Used for HyperTransport to PCI Peer to Peer Accesses The HyperTransport interface can have two reads outstanding to the PCI interface If a HyperT...

Page 250: ...es 56 59 see Table 22 Interrupt Sources on page 52 Any of the inputs that are not used by PCI devices can therefore be used as general active low interrupt inputs The P_INTA_L signal can also be driven as an open collector output by the interface note that when it is driven low the input logic will detect that it is low and raise system interrupt 56 This is intended for use in device mode to allow...

Page 251: ...n all entries of the interface transmit FIFOs The outgoing entry counters will get incremented on each transaction issued When an entry s counter overflows its priority is elevated 12 The correct ordering of interrupts with respect to writes from the HyperTransport into the BCM1250 is maintained An interrupt that follows a HyperTransport write will not be raised inside the BCM1250 until the write ...

Page 252: ...s of the coherence bit in the command 4 1 Topology The part is always a host If the interface revision is 3 or greater the ActAsSlave mode is supported for double hosted chains 4 1 1 Double Hosted Chains The interface supports double hosted chains Designation of the master and slave end must be done by software The Host Hide function is not implemented The ActAsSlave is implemented in interface Re...

Page 253: ...iByte on a Double Hosted Chain on page 212 Responses from the part always have the Bridge bit set rather than the specified clear and a UnitID of zero 2 Broadcasts are dropped 3 Directed requests are accepted as described in the Section Accessing the SiByte from HyperTransport Devices on page 210 4 This rule is not completely enforced Responses with the Bridge bit set and a UnitID of zero are trea...

Page 254: ...of read responses But this is not the case internally and care must be taken because the ZBbus always allows read responses to pass posted writes See the Section Ordering Rules and Device Drivers on page 14 7 1 Configuration Cycle Types Configuration Cycles are generated as described in Section Configuration of PCI and HyperTransport on page 234 7 3 1 1 I O Space Enable 7 3 1 2 Memory Space Enable...

Page 255: ...standard then bit 4 is used for frequency selection 7 5 9 Link Frequency Capability The link frequency capability register is only supported on revision 3 and greater of the interface On revision 2 BCM1250 pass 2 it would have the value 16 h801F indicating that frequencies up to 600MHz are supported and there are vendor specific frequencies On revision 1 BCM1250 pass 1 it would have the value 16 h...

Page 256: ...e CRC Expected Table 158 on page 255 and Received Table 159 on page 255 registers 10 1 3 Protocol Errors 10 1 4 Receive Buffer Overflow Errors Protocol and Overflow errors are reported in the HyperTransport Error Status Register Table 153 on page 254 rather than the new Link Error Register and controlled in the HyperTransport Error Control Register Table 152 on page 253 rather than the new Error H...

Page 257: ... summarised in the Table 125 on page 229 below which follows the format of the Table 50 in the HyperTransport Specification 11 1 Clocking Mode Definition The interface supports synchronous and asynchronous mode Software must configure the interface before setting the SipReady bit as described in the System Reset Initialization of the HyperTransport Interface on page 256 12 Reset and Initialization...

Page 258: ...perform the link frequency change on a link reset and revert to 200MHz on a cold reset However to support other devices that use the HyperTransport specification from before revision 1 0 this behaviour can be prevented by setting the sriLdtPLLCompat bit in the SRI Command Register Table 149 on page 252 A Address Remapping The interface supports the host address map as outlined throughout this chap...

Page 259: ...ional doubleword flow control ORDERING RULES The HyperTransport fabric and the PCI bus have a set of ordering rules described in Appendix E of the PCI specification revision 2 2 These differ from the more relaxed ordering rules used on the ZBbus The PCI HyperTransport rules are imposed in the I O bridge which will allow posted writes to pass reads and will not allow read responses to pass posted w...

Page 260: ...SysSet register can only be written from the ZBbus side of the bridge It is used to provide a value in the SubSystem Device and Vendor Id registers seen by external configuration reads In Device Mode software on the part should write the SubSysSet register with a value that identifies the manufacturer of the option card and its part number This write must be done early in initialization before the...

Page 261: ... bit is set any read requests from the PCI bus will be issued retries read access will probably only be needed for debugging Table 131 summarizes access to the PCI configuration registers Table 126 PCI CSR Access Rules Register ZBbus Read ZBbus Write PCI Read PCI Write Host Mode Device Vendor ID 0 Class Revision 8 Valid data Ignored Unpredictable Unpredictable Map Entries 44 80 SubSysSet 8C Signal...

Page 262: ...ree a bus number for its secondary interface the other bus it directly connects to and a subordinate bus number which is the highest numbered bus that is behind the bridge all buses in the range secondary subordinate are accessible through the bridge Once all the buses are enumerated the configuration code will assign base addresses to all the devices There are three separate address ranges for me...

Page 263: ...a master abort and set the status flags to indicate this happened the data returned will be marked valid and will contain 32 hFFFF_FFFF for normal accesses a master abort will result in a bus error return When a PCI configuration read is aborted in this way all other reads that are in flight in the PCI bridge will be terminated with a bus error Software should therefore ensure that there are no re...

Page 264: ...show bits 15 12 as zero For configuration accesses to buses other than bus 0 to work the HyperTransport secondary and subordinate bus numbers should be written with zero Until these registers are programmed accesses to the PCI memory or I O space will have UNDEFINED results CONFIGURATION HEADER DESCRIPTIONS The following sections describe the configuration headers used by the PCI and HyperTranspor...

Page 265: ...mory Host R O 8000_0008 Dev R O 0000_0008 Reserved Hits to this BAR are passed through as accesses to the upper 2GB of the low 4GB of the address space 28 Cardbus CIS R O 00000000 This register is not used 2C SubSystem Id R O 0000 SubSys Vendor R O FFFF These registers are not used internally since this is a host bridge If the Configuration registers are read by an external PCI master with the bri...

Page 266: ...NPREDICTABLE results 94 ReadHost W O 00000001 This register controls register accesses in device mode See Table 137 on page 243 and Using the PCI in Device Mode on page 232 98 Adaptive Extend R W xxxxxx00 This register controls performance features See Table 138 on page 243 9C VendorIdSet R W 0001166D This register is only available if the interface Rev Id is 3 or greater This register is only acc...

Page 267: ...PalSnpEn R O 1 b0 This bit is always zero The bridge does not snoop VGA palette accesses 6 ParErrResp R W 1 b0 This bit controls the response to PCI parity errors If it is set then the MstrDParErr bit is set in the status register and the PCI error interrupt is raised when a parity error is detected If it is clear then no interrupt is raised In both cases the DetParErr bit is set in the status reg...

Page 268: ...ursts on the PCI Bits 1 0 are R O and are always zero Table 131 PCI Cache Line Size Offset 0C Bits 7 0 Bits Name Default Description 7 0 ClineSz R W 8 h0 This register sets the cache line size in DWORDS 32 bit words used by the bridge for PCI transactions As a master the bridge bases the PCI command used on how the size of the transfer matches the value in this register word_count one cacheline us...

Page 269: ...ry Offset 44 80 Bits Name Default Description 0 enable 1 b0 This bit must be set to enable the mapping If it is clear the PCI interface will not assert DEVSEL to accept the request 1 send_ldt 1 b0 If this bit is set then the request will be forwarded to the HyperTransport fabric regardless of what the address is If this bit is clear the request is sent into the BCM1250 2 l2ca 1 b0 If this bit is s...

Page 270: ...hat the input from P_INTA_L is still active so setting the bit will raise a PCI INTA interrupt to the interrupt mapper This register should only be accessed from the ZBbus side of the PCI interface Writing to this register from the PCI interface will have UNPREDICTABLE results 31 1 reserved R 0 31 b0 Reserved Table 137 PCI Read Host Register Offset 94 Bits 31 0 Bits Name Default Description 0 rd_h...

Page 271: ...rnal configuration reads In Device Mode software on the device should write the SubSysSet register with a value that identifies the manufacturer of the option card and its part number This write must be done early in initialization before the host needs to read the value On interface revision 3 and later the Device Vendor Id and the Class code that will be read by the external host can also be cha...

Page 272: ...cLatTimer R O 00 Subord Bus R W 00 Sec bus R W 00 Pri Bus R O 00 Primary bus is fixed in hardware as 0 Secondary and subordinate buses must be set by the PCI HyperTransport bus enumeration code 1C Sec Status See Table 143 on page 248 R C 0000 I O Limit R W x1 I O Base R W x1 The low 4 bits of the base and limit registers indicate 32 bit I O addressing and register 30 is used The upper four bits ar...

Page 273: ...erved R O Unpredictable R O 0000 Reserved R O Unpredictable RevId 3 Features R O 0004 Reserved on RevId 1 and 2 On revision 3 and later this is the feature register indicating support for CRC test and not other features 50 SriCmd See Table 149 on page 252 R W 0000 SriRxDen R W 10 SriTxDen R W 10 System Reset Initialization registers These registers must be configured by the CPU before the HyperTra...

Page 274: ...h the bridge memory range Peer to Peer transfers from the PCI bus will always be accepted by the HyperTransport bridge but they can be disabled in the PCI bridge by clearing the ptp_en bit in the PCI Feature Control Register see Table 133 on page 242 2 MasterEn R W 1 b0 Primary Bus i e ZBbus Master Enable This bit controls acceptance of requests from the HyperTransport fabric If a request has unit...

Page 275: ...rface it will not be forwarded but it will be reported in the DetSerr bit in the Secondary Status register 15 DetParErr R O 1 b0 Always clear Errors from the ZBbus are logged by the Bus Watcher in the SCD Table 143 HyperTransport Bridge Secondary HT Status Register Offset 1C Bits 31 16 Bit Name Default Description 4 0 reserved R O 5 b0 These bits apply to PCI bridges only For a HyperTransport brid...

Page 276: ...r Any HyperTransport error with the NXA bit set causes a ZBbus response with valid data that is all ones Any HyperTransport error with the NXA bit clear causes a ZBbus Bus Error response 6 SecBusReset R W 1 b0 If this bit is set the LDT_RESET_L signal is asserted If the WarmReset bit in the HyperTransport host interface command register is clear the LDT_PWROK signal is deasserted to cause a cold r...

Page 277: ...ter Offset 40 Bits 31 16 Cont Bits Name Default Description Table 146 HyperTransport Link Control Register Offset 44 Bits 15 0 Bits Name Default Description 0 reserved R O 1 b0 Reserved 1 CrcSyncFloodEn R W 1 b0 If set CRC errors will cause a sync flood and set the Link Failure bit and will therefore jam the link If clear a sync flood is not generated and the bit not set CRC checking is always ena...

Page 278: ...InEn R O 1 b0 The bridge is not capable of Doubleword Flow Control 14 12 WidthOut R O 3 b000 This field is fixed for an 8 bit link 15 DwFcOutEn R O 1 b0 The bridge is not capable of Doubleword Flow Control Table 148 HyperTransport Link Frequency Register Offset 48 Bits 15 8 Bits Name Default Description 3 0 LinkFreq R W 4 b0000 This register sets the maximum transmitter clock frequency for the lin...

Page 279: ...copy used to control the PLL Older fixed frequency devices need this bit set so a link cold reset does not alter the link frequency HyperTransport Rev 1 0 devices reset their link frequency to 200 MHz on a link cold reset sriLdtPLLCompat set to 1 compatible with API AP1011 SiPackets SP1011 sriLdtPLLCompat set to 0 comply with 1 0 spec This table summarizes the behavior on reset LdtLinkFreq LdtPLLF...

Page 280: ...atalEn R W 1 b0 If this bit is set a nonfatal interrupt will be raised when a posted request to a nonexistent address or response that does not match a request is detected Non posted requests will receive an NXA error in this case 8 EocNxaSyncFloodEn R W 1 b0 If this bit is set a posted request needing an NXA or a response that does not match a request will cause SYNC flooding of the HyperTranspor...

Page 281: ...on the link This bit is also set but no error packet sent if a response is received that has source id of zero and did not come from this host Software may clear this bit by writing a 1 to it 7 5 Reserved R O 3 b0 Reserved Table 154 HyperTransport SRI Transmit Control Register Offset 6C Bits 23 16 Bits Name Default Description 3 0 BufRelSpace R W 4 b0100 This field sets the minimum number of packe...

Page 282: ...nse Data match the buffers in the receiver and fields in the NOP flow control packet NOP packets received from the other end of the link will increment the number of buffers that the transmitter believes the receiver has available If the count reaches the limit set in this register the extra credits will be discarded This allows a general way to throttle traffic in a particular virtual channel on ...

Page 283: ...port receive and transmit FIFO clocks A high level view of this is shown in Figure 50 Data from the fabric is loaded into the receive FIFO using the clock that was received with the data It is unloaded using the internal HyperTransport interface clock and passed to the receive logic Data from the transmit logic is loaded into the transmit FIFO using the internal HyperTransport interface clock and ...

Page 284: ...e HyperTransport transmit clock fTX Note that the receive and transmit clocks used in this discussion are the actual clocks on the link and therefore are half of the data rate The transmit clock frequency is set in the LinkFreq register in the HyperTransport Capability block The 100 MHz reference clock is multiplied up by the HyperTransport PLL to give the requested frequency The internal HyperTra...

Page 285: ... to be stable This is negative because it is measured from the load pointer to the unload pointer which must always be behind Since the pointers cycle around the FIFO the offset must be taken mod 8 to get the actual value programmed In asynchronous mode the load and unload pointers are stationary during initialization so the correct value can be obtained directly from this computation In synchrono...

Page 286: ...1 The recommended data settle margin is 2 This gives TxInitialOffset minInternalSyncClocks minPointerAdvance Margin 1 2 2 3 MOD 8 5 Error Control Register The Error Control Register sets the error handling behavior of the HyperTransport interface for both the standard HyperTransport errors and the additional ones reported on the BCM1250 or BCM1125H The possible responses to errors are to raise the...

Page 287: ...sb_softres bit and results in the assertion of link reset 3 HyperTransport link power ok LDT_PWROK This open drain output is driven and received by the interface The HyperTransport link is inactive if this signal is not asserted 4 HyperTransport link reset LDT_RESET_L This open drain output is driven and received by the interface The HyperTransport link is reset when this signal is asserted a cold...

Page 288: ...n the HyperTransport Link Control Register are reset to zero on a system cold reset and are persistent through a system warm reset 5 The HyperTransport Link Frequency Register is cleared by system cold reset and is persistent across system warm reset Beyond that it s behavior is determined by the sriLdtPLLCompat bit in the HyperTransport SRI Command Register If the sriLdtPLLCompat bit is set the L...

Page 289: ...User Manual BCM1250 BCM1125 BCM1125H 10 21 02 Broadcom Corporation Document 1250_1125 UM100CB R Section 8 PCI Bus and HyperTransport Fabric Page 261 This Page is left blank for notes ...

Page 290: ...BCM1250 BCM1125 BCM1125H User Manual 10 21 02 Broadcom Corporation Page 262 Section 8 PCI Bus and HyperTransport Fabric Document 1250_1125 UM100CB R This Page is left blank for notes ...

Page 291: ...thernet mode each interface can be put into a bypass mode where the Ethernet protocol processing is disabled and the interface acts as a Packet FIFO In this the GMII pins are used to provide an 8 bit data path in each direction that can carry packet or unframed data Selection of Ethernet or 8 bit Packet FIFO is done by software The interfaces are identical and independent The registers and interru...

Page 292: ...registers the RMON statistical counters and the DMA control interface It also provides the connection from the DMA engines into the part Figure 51 Ethernet Interface Block Diagram I O Bridge 1 Receive DMA Transmit DMA Receive Transmit FIFO FIFO Packet FIFO Ethernet or Packet FIFO Select GMII Interface Interface Control Data Data Packer Unpacker Ethernet or Packet FIFO Select and Synchronizer Contr...

Page 293: ...he external physical layer interface over the GMII pins It will also respond to flow control requests and block packet transmission as required The Packet FIFO protocol engine generates simple framing signals for the external interface but otherwise acts as a bypass path for data to the GMII pins The receive packet flow starts with a byte stream being delivered from the physical layer device over ...

Page 294: ...frame size Overwrite the source address field in the packet with the MAC s own source address Append a CRC to the end of the packet During reception the protocol engine can Automatically drop packets that have errors during their first few bytes Filter incoming packets and automatically discard any with a destination address that does not match Both exact and hash based matching are available Flag...

Page 295: ... Figure 52 Figure 52 Ethernet Frame Format Preamble SFD Destination Address Source Address Type Length Data CRC IFG IFG VLAN Frame ss ss ifg_tx ifg_thrsh Min Packet Size Max Packet Size 7 1 6 6 2 46 1500 4 Preamble SFD Destination Address Source Address Type Length Data IFG IFG ss ss 7 1 6 6 4 46 1500 4 CRC 2 VLAN TAG Standard Frame Previous Frame Previous Frame 4 Defer to CRS Ignore CRS ...

Page 296: ...If the value of the field is less than or equal to 1500 then this is an 802 3 format frame and this field gives the length of the data field If the value is greater than 1535 then this is an Ethernet format frame and this field gives the type The receive interface can be set to check this length against the actual packet length and report an error if they differ Data The data portion of the packet...

Page 297: ... packet is used The maximum offset is 248 31 8 bytes There are separate registers to set the offsets on the transmit and receive sides and their values may be different In both cases the CRC offset specifies the first byte of the packet that will be included in the CRC calculation For the transmit side the tx_pkt_offset is used to locate the Ethernet header for replacement of the source address an...

Page 298: ...s be set unless the part is being run in a test mode Ethernet packets are recovered into a byte stream before being put into the 64 bit wide receive FIFO and data is read in 64 bit chunks from the transmit FIFO and converted to a byte stream before it is sent The system endian configuration is used to correctly order the bytes so that the first byte on the wire is at the lowest memory location The...

Page 299: ...empty entries there must be in the FIFO before it will request data The DMA engine fetches either 32 bytes or 64 bytes at a time so this value should be set to 4 or 8 The data from the transmit FIFO is read out by the protocol engine for transmission Once transmission of a packet has started the DMA engine must ensure that there is always data in the FIFO when the protocol engine needs it If the F...

Page 300: ...err bit in the mac_status register LateCollision ret_drpreq_en The Ethernet protocol sets the minimum packet size so that all collisions will be seen during the transmission of a minimum length packet Any collision after the minimum length has been sent is a late collision and indicates a serious error Late collisions can be caused by the Ethernet segment being longer than allowed by the specifica...

Page 301: ...e are six manipulations that the protocol engine can perform configured per packet by options in the DMA descriptor Replacement of source address The source address that is in the packet supplied by the DMA engine can be overwritten with the address of this interface that has been set in the mac_ethernet_addr register Removal of VLAN tag The four bytes of VLAN tag can be dropped from the packet co...

Page 302: ...he end of the packet is received the data is always reported to the DMA engine If there is any reception error before this point then the packet can be automatically dropped by flushing the data in the FIFO The error will still be counted in the error statistics If the drp_errpkt_en bit in the mac_cfg register is set then all packets with errors will be thrown on the ground in this way If this bit...

Page 303: ...lock for 10 Mbp s and 4 bits per clock for 100 Mbp s However the length of a valid Ethernet packet is always an integral number of bytes If a packet is received where this is not the case a dribble error is reported this error is sometimes called an alignment error This error can never happen during gigabit operation because the interface from the PHY is 8 bits wide any similar error would be repo...

Page 304: ...DMA ed and the packet can be dropped If an error is detected after DMA has started the DMA will be completed and the error flagged in the status bits written back to the descriptor The dropping of packets is enabled by holding the first few entries in the receive FIFO and not informing the DMA logic that there is data to extract until a threshold has been reached If the error happens before the th...

Page 305: ...gine Figure 56 Receive Address Filter mac_addr 0 mac_addr 1 mac_addr 2 mac_addr 3 mac_addr 4 mac_addr 5 mac_addr 6 mac_addr 7 FF_FF_FF_FF_FF_FF Dest Address CRC Bits 9 1 511 448 447 484 483 320 329 256 255 192 191 128 127 64 63 0 mac_hash7 mac_hash6 mac_hash5 mac_hash4 mac_hash3 mac_hash2 mac_hash1 mac_hash0 Index Accept Match bcast_en Broadcast direct_inv mcast_en mcast_inv ucast_en ucast_inv uca...

Page 306: ... to put multicast addresses in the Exact Match filter or enable multicast hash matches is to make use of the match_exact and match_hash flags in the DMA status information 5 Pause Frame If the header of the frame indicates that it is a Pause Frame flow control frame then it will normally be consumed by the interface and the transmitter flow controlled as requested In parts where the system revisio...

Page 307: ...e swapped to match the hardware Input parameters buf buffer len length of buffer Return value CRC as held in MAC hardware define mchash mca eth_hwcrc32 mca ENET_ADDR_LEN 1 0x1FF static unsigned eth_hwcrc32 unsigned char databuf int datalen unsigned int idx crc 0xFFFFFFFFUL tmp static unsigned int crctab 0x00000000 0x1db71064 0x3b6e20c8 0x26d930ac 0x76dc4190 0x6b6b51f4 0x4db26158 0x5005713c 0xedb88...

Page 308: ...can be used to select any nibble in the first 128 bytes of the packet For example if selection is to be made based on the low byte of the Ethernet packet type which is the second byte of the field sent on the wire the offset should be decimal 26 Figure 58 shows how this offset is obtained Even offsets refer to bytes in the received packets odd offsets straddle bytes the high four bits of the index...

Page 309: ...is zero the rx_ch_msn_sel value is ignored and the upper 4 bits of the index are the nibble after the rx_ch_sel_msb rx_ch_sel offset as described above PACKET TYPE IDENTIFICATION The receiver reads the Ethernet packet type field in the inbound packet Some common packet types are detected and encoded in the status that is written to the descriptor Four of the types are fixed the other four are prog...

Page 310: ...ion IP addresses IP protocol type and TCP length IP length 20 is summed then the checksum continues for the TCP length of the packet padded with a byte of 0 if required The bad_tcpcs flag written back to the b portion of the descriptor will be set if the checksum is not 16 hFFFF The same pseudo header and checksumming algorithm is used for UDP as TCP the UDP header itself is slightly different but...

Page 311: ...sion Packet transmission is still possible when back pressure is applied in this way If there is an outgoing packet it will contend for access in the usual manner If the transmitter gains the link then the packet can be sent normally if it loses then the back pressure machine will cause collisions with the packet that another source is trying to send In half duplex mode if fc_cmd is set to 2 b10 t...

Page 312: ...annel then it will pause on flow control otherwise it continues to transmit even when flow control is requested On devices with the system revision PERIPH_REV3 or greater when the fwd_pause_en bit is clear and hardware is acting on the pause frame the current pause state can be read from the tx_pause_on bit in the mac_status register this bit will be set if the MAC is still in the pause interval s...

Page 313: ..._status_debug register The split_ch1 bit in the mac_int_mask register is used to select between the standard and split methods of signalling and clearing interrupts It defaults to 0 to give the standard behaviour STANDARD INTERRUPT SIGNALING In the standard mode the main interrupt for the MAC is raised whenever any status bit is set and the corresponding mask bit is set Reads from the mac_status r...

Page 314: ...output to the mdio_out bit The MDIO data is latched by the PHY on the rising edge of MDC so the mdio_dir and mdio_out bits should never be changed when the mdc bit is changed from a zero to a one To send data to the PHY the mdio_dir bit should be cleared a single write to the mac_mdio register can be used to set mdc low and put the data on mdio_out The same data should be written to mdio_out when ...

Page 315: ...ite to mac_mdio mdc 0 mdio_out bit to send mdio_dir 0 Wait Half Clock Cycle Time Single Write to mac_mdio mdc 1 mdio_out bit to send mdio_dir 0 Wait Half Clock Cycle Time More to Send Single Write to mac_mdio mdc 0 mdio_dir 1 Write Bits No Yes Single Write to mac_mdio mdc 1 mdio_dir 1 Wait Half Clock Cycle Time Single Write to mac_mdio mdc 0 mdio_dir 1 Wait Half Clock Cycle Time Read Bit From mdio...

Page 316: ...ber is written to the counter_addr field in the mac_status register The RMON counters are only updated in Ethernet Mode Table 166 MAC to PHY Management Protocol Protocol Idle Start Op Code Device Addr Register Addr Turn Around Data Idle Read MAC Idle 01 10 AAAAA RRRRR ZZ ZZZZ ZZZZ ZZZZ ZZZZ Idle Read PHY Idle ZZ ZZ ZZZZZ ZZZZZ Z0 XXXX XXXX XXXX XXXX Idle Write MAC Idle 01 01 AAAAA RRRRR 10 XXXX XX...

Page 317: ...fferent minimum frame size has been set in the mac_frame_cfg register then runt packets will be any packet smaller than that number 10 _0 4050 _1 5050 _2 6050 Tx Over Size Packet Counter This Counter counts the total number of oversize packets packets larger than the maximum frame size transmitted by the MAC The maximum frames size for IEEE 802 3 compliance is 1518 bytes if a different maximum fra...

Page 318: ...in the mac_frame_cfg register then oversize packets will be any packet larger than that number 23 _0 40B8 _1 50B8 _2 60B8 Rx FCS Error Packet Counter This Counter counts the total number of packets received by the MAC with an FCS Error i e a bad CRC 24 _0 40C0 _1 50C0 _2 60C0 Rx Length Error Packet Counter This Counter counts the total number of packets received by the MAC with Length Error where ...

Page 319: ...RXDV TXEN and error RXER TXER pins are used to signal framing information In addition in the encoded mode the collision COL and management data MDIO pins get used to provide flow control on the link Switching between Ethernet and any 8 bit Packet mode only affects the interface being switched so there can be any mix of Ethernet and 8 bit Packet interfaces The 16 bit Packet FIFO modes do a larger r...

Page 320: ...lgorithm as for the Ethernet and the bit in the receive DMA status word will be set accordingly If the bypass_fcs_chk bit is clear the status bit will always indicate the CRC check passed The receive channel selection is done in the same way as for the Ethernet mode as described in Section Receive DMA Channel Selection on page 281 The only transmit options see Section Data Buffers and Descriptors ...

Page 321: ...ped instantaneously However there is additional delay If CRCs are not being appended by the transmitter an additional 8 bytes could be sent leaving two bytes margin But if the transmitter was appending CRC then the additional 12 bytes would cause the receive fifo to overflow so the threshold must be increased to 5 doublewords Note that the direction of the MDIO RCFC pin is controllable by software...

Page 322: ... mode is shown in Figure 60 on page 295 The packet data is framed by the TXEN or RXDV signal The first byte that has it active is marked as the start of a packet and the last byte that has it active is the end of the packet all bytes between are valid and part of the packet The TXER or RXER signal can be used to signal an error whenever the frame signal is active Figure 60 8 bit Packet FIFO GMII S...

Page 323: ...n normally the management interface to the PHY as a receive flow control output if a the CPU sets the force flow control configuration bit b the number of descriptors on a receive channel falls below the low watermark and automatic flow control is enabled for that channel or c there are less than 4 64 bit words left free in the receive FIFO If the device the other end of the link honours the flow ...

Page 324: ...et The end of packet is one cycle before the SOP or whenever the data goes invalid this extra EOP is required to push out the last data at the end of a valid sequence Figure 62 8 Bit Packet FIFO SOP Style TXEN RXDV TXER RXER TXD RXD 7 0 TCLKO RCLK 55 SOP EOP SOP EOP Table 172 Codes for 8 Bit SOP Packet FIFO TXEN RXDV TXER RXER Valid Data Start of Packet 1 1 Valid Data 1 0 Valid Data End of Packet ...

Page 325: ... are ignored so in Figure 63 there is not an SOP flagged in the cycle marked X one cycle after TXEN RXDV was low This mode is good for streaming data that uses only the data valid signal If the EOP flag is always low the interface will transfer a single never ending packet for as long as DMA buffers are provided Figure 63 8 Bit Packet FIFO EOP Style TXEN RXDV TXER RXER TXD RXD 7 0 TCLKO RCLK 55 SO...

Page 326: ...hk bit is set in the mac_cfg register the status bit in the receive descriptor will be set accordingly if the bypass_fcs_chk bit is clear the status word will never flag a CRC error If the CRC 32 is used on the receive side there must be at least three clock cycles between the end of packet and the start of the next packet If this inter frame gap is not provided then the CRC checker will give UNPR...

Page 327: ...ng a pause from the sender The transmitter will see the flow control request on the next rising edge of the clock and will send data for 2 4 cycles before suspending transmission one cycle later The interface will assert its flow control output when receive channel flow control is invoked either by one of the DMA channels having fewer descriptors than the low watermark or by an explicit processor ...

Page 328: ...a debugger collecting the system state could cause a hang that would be hard to track down There is no need to provide a periodic clock One possible solution would be to connect the unused REFCLK input to the boot ROM chip select or SCL if the system boots from SMBus since this is guarenteed to toggle when the part comes out of reset before any instructions run the SB 1 will have fetched 16 bytes ...

Page 329: ...t happens collision underrun error excessive collision error or late collision while the FIFO is in locked state i e less than the number of entries set by tx_rl_thrsh have been read from the transmit FIFO for a given packet The retry_en ret_drprep_en and ret_ufl_en bits enable automatic retry selectively for each of the error types If the tx_hold_sop_en bit is clear or the number of entries set b...

Page 330: ...t is set then packets that are signalled with a code error by the PHY are automatically dropped Used in Ethernet mode only 22 drp_drblerrpkt_en 1 b0 If this bit is set then packets with a dribble error are automatically dropped Used in Ethernet mode only 23 drp_rntpkt_en 1 b0 If this bit is set then runt packets those shorter than the minimum packet size configured in the mac_frame_cfg register ar...

Page 331: ...loopback_sel 1 b0 When this bit is set an internal loopback path is enabled connecting the transmitter and receiver GMII pins Used in Ethernet and 8 bit Packet FIFO modes 38 fast_sync 1 b0 This bit must be set for normal operation It defaults to 0 so software should be sure to set it before starting the MAC Used in Ethernet and Packet FIFO modes 39 ss_en 1 b0 This bit must always be set Broadcom U...

Page 332: ... then packets may be transmitted back to back Used in Packet FIFO modes 54 fc_sel 1 b0 This bit is used by software to force flow control If it is set then flow control will be asserted on the link Pause frames in full duplex Ethernet backpressure by the method encoded in the fc_cmd bits for half duplex Ethernet or the link level flow control pin RXFC for encoded Packet Fifo mode Flow control will...

Page 333: ...t is zero so it will self clear as part of the reset sequence 9 reserved 1 b0 Reserved 10 mac_rx_en 1 b0 If this bit is clear the receive Ethernet media access engine will be held in reset If this bit is set it will run normally 11 mac_tx_en 1 b0 If this bit is clear the transmit Ethernet media access engine will be held in reset If this bit is set it will run normally 12 byp_rx_en 1 b0 If this bi...

Page 334: ...ision greater than 2 15 reserved 1 b0 Reserved 21 16 tx_rl_thrsh 6 b0 Transmit FIFO release count This sets the number of 64 bit FIFO entries that will be held in the FIFO when the MAC is configured to hold the start of packets See the tx_hold_sop_en bit in the mac_cfg register See Section Transmitter Configuration on page 272 23 22 reserved 2 b0 Reserved 29 24 reserved 6 b0 Reserved 31 30 reserve...

Page 335: ...ile the engine is active the results are UNPREDICTABLE 17 12 ifg_thrsh 6 b0 This sets the threshold time in interface cycles for checking carrier sense during the inter frame gap At the start of the IFG the MAC will monitor the carrier sense and defer if a carrier is detected the IEEE standard suggests this should last 2 3 of the gap During the remainder of the IFG the MAC ignores the carrier sens...

Page 336: ...he MAC will report a runt packet error for any packet that is received that is smaller than this number of bytes after preamble and SFD have been stripped For IEEE 802 3 compliance this value should be 64 for all speeds of operation This value may only be changed while the protocol engine is held in reset if it is changed while the engine is active the results are UNPREDICTABLE This size must be g...

Page 337: ...f set the flow control is done by the DMA engine Used in both Ethernet and Packet FIFO modes 63 49 notimp 32 b0 Not Implemented Table 182 MAC Status Registers mac_status_0 00_1006_4408 mac_status_1 00_1006_5408 mac_status_2 00_1006_6408 READ ONLY Reading this register will clear all latched bits This register is used in both Ethernet and Packet FIFO modes Bits Name Default Description 0 rx_ch0_eop...

Page 338: ...or the start of packet but the controller runs out of descriptors during the packet reception then the dscr_err bit will be set in the receive status word for the packet The interface will continue dropping data until there are descriptors available when a start of packet is received 16 tx_ch0_eop_count 1 b0 Set if the EOP interrupt was raised as a result of the packet count being reached 17 tx_ch...

Page 339: ...derflows This happens if the DMA or sender in direct mode has delayed inserting data into the FIFO and it was empty when more data was needed to be transmitted 43 tx_ovrfl 1 b0 This bit is set by the transmit FIFO overflowing This happens if the DMA or sender in direct mode writes to the FIFO when it is full This will only happen for DMA if the tx_wr_thrsh threshold is incorrectly set 44 ltcol_err...

Page 340: ...ription Table 183 MAC Status 1 Register mac_status1_0 00_1006_4430 mac_status1_1 00_1006_5430 mac_status1_2 00_1006_6430 READ ONLY Reading this register will clear the channel 1 latched bits This register is used in both Ethernet and Packet FIFO modes Bits Name Default Description 63 0 status 64 h0 Reading this register gives the same result as reading the status register except that only the latc...

Page 341: ...c_tx_fifo_ptrs_2 00_1006_6128 READ ONLY Broadcom Use Only This register is used in both Ethernet and Packet FIFO modes Bits Name Default Description 63 0 status 64 hx Status for fifo and counts Broadcom Use Only Table 187 MAC Receive Address Filter Exact Match Registers mac_addr0_0 00_1006_4280 mac_addr0_1 00_1006_5280 mac_addr0_2 00_1006_6280 mac_addr1_0 00_1006_4288 mac_addr1_1 00_1006_5288 mac_...

Page 342: ...0 mac_hash2_2 00_1006_6250 mac_hash3_0 00_1006_4258 mac_hash3_1 00_1006_5258 mac_hash3_2 00_1006_6258 mac_hash4_0 00_1006_4260 mac_hash4_1 00_1006_5260 mac_hash4_2 00_1006_6260 mac_hash5_0 00_1006_4268 mac_hash5_1 00_1006_5268 mac_hash5_2 00_1006_6268 mac_hash6_0 00_1006_4270 mac_hash6_1 00_1006_5270 mac_hash6_2 00_1006_6270 mac_hash7_0 00_1006_4278 mac_hash7_1 00_1006_5278 mac_hash7_2 00_1006_627...

Page 343: ...192 MAC Receive Address Filter Control Registers mac_adfilter_cfg_0 00_1006_4200 mac_adfilter_cfg_1 00_1006_5200 mac_adfilter_cfg_2 00_1006_6200 This register is used in both Ethernet and Packet FIFO modes Bits Name Default Description 0 allpkt_en 1 b0 When this bit is set all packets will be accepted promiscuous mode Used in both Ethernet and Packet FIFO modes 1 ucast_en 1 b0 When this bit is set...

Page 344: ...llows software to do pause frame flow control for example to only disable the best effort tx DMA channel when a pause is requested but allow the priority traffic to continue Used only in Ethernet mode 33 vlan_det_en 1 b0 System Revision PERIPH_REV3 and later only If this bit is set then 4 is added to the ip_hdr_offset if the type field in the MAC header i e at mac_hdr_off 12 and 13 is the VLAN typ...

Page 345: ...e for mapping the 8 bits from a received packet into a two bit channel number The 256 entry table has bit 0 register 0 as entry 0 and bit 63 register 3 as entry 255 The chup register provides the msb and the chlo register the lsb of the channel number Table 194 MAC MII Management Interface Registers mac_mdio_0 00_1006_4428 mac_mdio_1 00_1006_5428 mac_mdio_2 00_1006_6428 This register is used in bo...

Page 346: ...BCM1250 BCM1125 BCM1125H User Manual 10 21 02 Broadcom Corporation Page 318 Section 9 Ethernet MACs Document 1250_1125 UM100CB R This Page is left blank for notes ...

Page 347: ...User Manual BCM1250 BCM1125 BCM1125H 10 21 02 Broadcom Corporation Document 1250_1125 UM100CB R Section 9 Ethernet MACs Page 319 This Page is left blank for notes ...

Page 348: ...des software will need to re initialize the interface and may need to reset the external device Each serial port has 8 pins associated with it In addition if an interface is in synchronous mode it can use one of the GPIO pins as an output software cannot change the use of this pin it can only be set by the reset configuration The following table shows their use in each mode and for asynchronous mo...

Page 349: ...T serial port 1 in asynchronous mode is driven from channel B BAUD RATE GENERATORS The baud rate is generated on chip by dividing down from the 100MHz reference clock Each channel can have a different baud rate but for a channel the transmit and receive rates must be the same The baud rate is selected by setting the duart_clk_sel register to 100 MHz baud_rate 20 1 Some popular baud rates are shown...

Page 350: ...e except when transmission of the current character including stop bits is complete the line is driven low The break condition is cleared with the stop break command which removes the break synchronously with the transmit bit clock Resetting the transmitter will cause the current transmission to be aborted and all characters in the FIFO to be discarded all transmitter state is cleared and it is le...

Page 351: ...ion of a character has started it will continue until the character has been sent regardless of the state of CTS_TCLKIN When enabled the RTS_TSTROBE pin is driven by the receiver It will be set low if the receiver is enabled and is able to receive a character On receiving a start bit that will cause the receiver to become full the RTS_TSTROBE line will be deasserted set high to indicate that no fu...

Page 352: ...bit in the interrupt status register there is a bit in the interrupt mask register duart_imr if a status bit is set and the corresponding mask bit is also set then an interrupt will be raised Again for programming convenience aliases of the lower and upper bits of the mask are provided in the lower four bits of the duart_imr_a and duart_imr_b registers these are aliases internally there is only a ...

Page 353: ...out This timeout ensures that characters received when the fifo is below threshold will not suffer long latencies before being serviced If either the threshold or timeout mechanism are used the receive interrupt status bit in the duart_isr register will be set based on the threshold or timeout However the duart_rx_ffull bit in the duart_status register will continue to reflect the real full state ...

Page 354: ...aracter in the FIFO 1 Interrupt on receiver FIFO full 7 duart_rx_rts_ena 1 b0 Receiver Request to Send Control enable Channel A If set the S0_RTS_TSTROBE pin will be used as hardware controlled RTS if clear the pin will output the inverse of op 0 Channel B If set the S1_RTS_TSTROBE pin will be used as hardware controlled RTS if clear the pin will output the inverse of op 1 63 8 notimp 56 bx Not im...

Page 355: ... and resume normal transmission 7 reserved 1 b0 Reserved write as zero 63 8 notimp 56 bx Not implemented Table 200 DUART Status Registers duart_status_a 00_1006_0120 duart_status_b 00_1006_0220 READ ONLY Bits Name Default Description 0 duart_rx_rdy 1 b0 Receiver ready at least one character can be read This bit is set whenever there are characters in the receive FIFO even if the receiver is disabl...

Page 356: ...140 duart_full_ctl_b 00_1006_0240 Bits Name Default Description 3 0 duart_sig_full 4 hF This field sets the threshold for the receive fifo full interrupt The interrupt is raised when the number of characters in the fifo is greater than the value set With the default of 15 the interrupt is only raised when the fifo is completely full 7 4 duart_int_time 4 h0 If this field is non zero then the fifo f...

Page 357: ... ext Input pin level 0 Low 1 High ip 2 S0_CIN_RCLKIN 3 duart_in_pin3_val ext Input pin level 0 Low 1 High ip 3 S1_CIN_RCLKIN 4 duart_in_pin4_val ext Input pin level 0 Low 1 High ip 4 S0_TIN 5 duart_in_pin5_val ext Input pin level 0 Low 1 High ip 5 S1_TIN 6 duart_rin0_pin ext Input pin level 0 Low 1 High ip 6 S0_RIN 7 duart_rin1_pin ext Input pin level 0 Low 1 High ip 7 S1_RIN 63 8 notimp 56 bx Not...

Page 358: ...d 63 8 notimp 56 bx Not implemented Table 209 DUART Input Port Change Status Register for Channel B duart_inport_chng_b 00_1006_03E0 READ ONLY Read Clears Channel B Change of State bits Bits Name Default Description Port Pins 3 0 duart_in_pin_val ext Input pin level 0 Low 1 High ip 3 0 These bits match duart_in_port 3 0 7 4 duart_in_pin_chng 4 b0 Input pin change of state ip 3 0 0 No 1 Yes These b...

Page 359: ...p0_chng_ena 1 b0 ip 0 S0_CTS_TCLKIN change of state enable 1 duart_ip1_chng_ena 1 b0 ip 1 S1_CTS_TCLKIN change of state enable 2 duart_ip2_chng_ena 1 b0 ip 2 S0_CIN_RCLKIN change of state enable 3 duart_ip3_chng_ena 1 b0 ip 3 S1_CIN_RCLKIN change of state enable 7 4 reserved 4 h0 Unused always zero 63 8 notimp 56 bx Not implemented Table 213 DUART Per Channel Aux Control Registers duart_aux_ctrl_a...

Page 360: ...or channel B 63 8 notimp 56 bx Not Implemented Table 215 DUART Channel A Only Interrupt Status Register duart_isr_a 00_1006_0320 READ ONLY Bits Name Default Description Convenience register only gives channel A ISR 0 duart_isr_tx 1 b1 Transmitter Ready 1 duart_isr_rx 1 b0 Receiver Ready FIFO Full 2 duart_isr_brk 1 b0 Change in Break 3 duart_isr_in 1 b0 Input Port 0 or 2 Changes Status 7 4 Reserved...

Page 361: ...mr_in_b 1 b0 Mask Input Port 1 3 Changes Status input port changes for channel B 63 8 notimp 56 bx Not Implemented Table 218 DUART Channel A Only Interrupt Mask Register duart_imr_a 00_1006_0330 Bits Name Default Description Convenience register only writes channel A IMR bits 0 duart_imr_tx 1 b0 Mask Transmitter Ready A 1 duart_imr_rx 1 b0 Mask Receiver Ready FIFO Full A 2 duart_imr_brk 1 b0 Mask ...

Page 362: ... the op 0 duart_clr_op 0 W O op 0 1 Clear to low 0 No change 1 duart_clr_op 1 W O op 1 1 Clear to low 0 No change 2 duart_clr_op 2 W O op 2 1 Clear to low 0 No change 3 duart_clr_op 3 W O op 3 1 Clear to low 0 No change 7 4 Reserved W O Reserved only 4 outputs 63 8 notimp 56 bx Not Implemented Table 222 DUART Output Port RTS Register duart_out_port 00_1006_0360 WRITE ONLY Bits Name Default Descrip...

Page 363: ...User Manual BCM1250 BCM1125 BCM1125H 10 21 02 Broadcom Corporation Document 1250_1125 UM100CB R Section 10 Serial Interfaces Page 335 This Page is left blank for notes ...

Page 364: ...led a serial channel The interface provides two identical and independent serial channels 0 and 1 The registers and interrupts associated with each are differentiated by appending _0 or _1 to their names FUNCTIONAL OVERVIEW The serial channels are part of the I O subsystem on the part and connect to the ZBbus through I O bridge 1 Figure 67 on page 338 shows a block diagram Each consists of 3 major...

Page 365: ...rface Block Diagram Bus Interface Transmit FIFO 8 x 64 bit i e 2 cache lines Receive FIFO 16 x 32 bits i e 2 cache lines TxPack RxPack Address Matching TxBit Shifter Stuffing Pading Add Check CRC TxCRC TxFlag Flag Generation TxLine TxMem Dout Tin RxBit Shifter Check CRC RxStuff De stuffing RxFlag Remove Flag Abort RxLine RxMem Din Rin TxParam RxParam Steering ...

Page 366: ...larly port 1 to channel 1 The 8 pins for each interface are used as follows in synchronous mode In addition the following GPIO pins can be driven from the serial port when the appropriate reset time configuration resistors select this use see Section Reset on page 26 Table 223 Synchronous Serial Interface Signal Names Pin Direction Synchronous serial port Function DOUT Output Transmit data output ...

Page 367: ... signal can be generated by an internal sequencer which is itself synchronized to the data stream by a pulse on RIN The sequencer can also provide a strobe on the RSTROBE output The bit stream delivered to the protocol engine consists of the bits sampled during the enabled bit times clock edges occurring during disabled bit times are suppressed and not seen by the protocol engine Input Using an Ex...

Page 368: ...y The synchronization pulse on RIN is latched on the same clock edge as the data on DIN The synchronization pulse is delayed by 0 1 2 or 3 clocks The edge_det bit in the ser_mode register selects either the active level or the inactive to active edge of the delayed pulse as the start signal for the sequencer If the sequencer is currently idle it will reset to map table entry zero when started and ...

Page 369: ...press the transmission of bits 2 External Enable Regardless of clock source the TIN pin can be supplied with an externally generated enable signal This is latched on the active edge of the clock and disables output 0 1 2 or 3 clocks later The DOUT pin is high impedance undriven when disabled 3 Internal Sequencer Regardless of clock source but exclusive with 2 the enable signal can be generated by ...

Page 370: ...ach entry controls the behavior of the line interface for a number of bit times equal to Count 1 if Bit Byte is 0 or to 8 Count 1 if Bit Byte is 1 During those bit times data is accepted from the protocol engine and sent on DOUT on each clock edge if Enable is 1 DOUT is set high impedance and no data is extracted from the protocol engine if Enable is 0 The TSTROBE pin is driven with the value of S...

Page 371: ... engines It has two modes configured in the ser_mode register In HDLC mode frames are encoded on the bit stream using the HDLC protocol In transparent mode the bit stream is packed into bytes and the framing is based on the line interface Enable signal OPERATION IN HDLC MODE In the HDLC mode the frame structure used by the DMA engines is converted into the HDLC form on the line The protocol engine...

Page 372: ...elimit frames of length 0 Frames can also be terminated by HDLC Abort or Idle patterns a zero bit followed by at least 7 ones Abort and Idle termination are not distinguished by the receiver but are reported as aborted frames Bytes are sent and received in order of increasing address according to the system endian mode Within each byte except for the CRC the least significant bit is sent or receiv...

Page 373: ...calculates a CRC either the CRC CCITT or CRC 32 as determined by the crc_mode bit in the ser_mode configuration register The bit stuffed CRC is inserted before the closing flag if the append_CRC option is set in the DMA descriptor The transmitted CRC is always compared to the calculated CRC If the CRC was automatically generated the two necessarily match If the CRC was supplied by the user and it ...

Page 374: ...ous can be sent onto the channel as configured by flag_en in the ser_mode register HDLC Receiver In HDLC mode frames within the bit stream are self identifying The Protocol Engine monitors the input bit stream supplied by the line interface Frame recognition begins with a Flag not followed by another Flag an Abort or an Idle The receive module first removes any bit stuffing to extract the bytes of...

Page 375: ...e is available in the RxFIFO The packet is checked for errors during reception Indications of any errors are passed to the RxFIFO and eventually written back into the DMA descriptor status field For each frame the CRC is computed using CRC CCITT or CRC 32 as selected by the crc_mode in the ser_mode register The computed CRC is compared with the value in the packet If the two do not match crc_error...

Page 376: ...dress according to the system endian mode In transparent mode the following functions may be performed address matching optional padding of short frames to a configured minimum frame size optional CRC calculation and checking optional In transparent mode the data is framed by implicit start and stop indications at the bit level The details depend upon configuration of the line interface Table 228 ...

Page 377: ...Transparent Mode Transparent mode operates similarly to HDLC mode except that neither Flag detection deletion nor removal of bit stuffing is performed CRC checking and address filtering remain available Note that since there is no way to disable the CRC check device drivers for protocols that do not have CRCs must ignore the CRC error flag and therefore cannot use the good packet bit in the DMA de...

Page 378: ...configuring and initializing the serial DMA channels FIFO CONFIGURATION TxFIFO is a 64 bit wide FIFO with 8 entries The ser_tx_wr_thres register sets the number of empty 64 bit entries that must be in the TxFIFO before it will request DMA data Since the DMA engine fetches in blocks of 32 bytes this value must be set to 4 entries To reduce the likelihood of TxFIFO becoming empty during transmission...

Page 379: ...mbined with status interrupts and made available in the ser_status register Bits in this register are masked by the ser_int_mask register and combined to generate the system interrupts 10 for channel 0 and 11 for channel 1 Reading the ser_status register will clear all bits in it For a description of DMA interrupts associated with the serial channels please refer to Section7 DMA on page 147 To all...

Page 380: ...tive 1 b0 edge_det 1 b0 table_en 1 b1 Table 230 RMON Counters Number offset from 00_1006_0000 Counter Description 0 _0 05C0 _1 09C0 Tx Byte low Total number of bytes transmitted Low 16 bits 1 _0 05C8 _1 09C8 Tx Byte high Total number of bytes transmitted High 16 bits 2 _0 05D0 _1 09D0 Rx Byte low Total number of bytes received Low 16 bits 3 _0 05D8 _1 09D8 Rx Byte high Total number of bytes receiv...

Page 381: ...strobe 1 b0 Loopback Strobe mode This configures the Sync Enable inputs during loopback 0 TIN and RIN are taken from the external source 1 TIN is always active and RIN is internally connected to RtsTstrobe 9 loop_data 1 b0 Loopback enable If this bit is set the DIN input be internally connected to the DOUT output to allow loopback testing 15 10 reserved 6 bx Reserved 63 16 notimp 48 bx Not Impleme...

Page 382: ...Interface Mode Register Cont ser_line_mode_0 00_1006_0578 ser_line_mode_1 00_1006_0978 Bits Name Default Description Table 233 Synchronous Serial Command Register Write only ser_cmd_0 00_1006_0540 ser_cmd_1 00_1006_0940 Bits Name Description 0 rx_en Receive enable When the receiver is reset writing a one enables the receiver 1 tx_en Transmit enable When the transmitter is reset or paused writing a...

Page 383: ...ame Default Description 3 0 thrsh 4 b100 Number of filled 64 bit entries the TxFIFO must have before the protocol engine will start transmitting the frame The FIFO is only 8 entries so setting bit 3 will result in UNPREDICTABLE behaviour 15 4 reserved 12 b0 Reserved 63 16 notimp 48 bx Not implemented Table 236 Serial Receive Read Threshold Register ser_rx_rd_thres_0 00_1006_0570 ser_rx_rd_thres_1 ...

Page 384: ... Name Description 0 rx_crcerr Received frame with CRC error 1 rx_abort Received frame terminated by Abort or Idle 2 rx_octet_error Received frame length not a multiple of 8 bits 3 rx_longframe_error Received frame longer than maximum size 4 rx_shortframe_error Received frame shorter than minimum size 5 rx_overrun_error RxFIFO overrun 6 rx_sync_error Received a sync before the end of the receive ta...

Page 385: ... 27 tx_hwm Set if the high watermark interrupt is raised 28 tx_lwm Set if the low watermark interrupt is raised 29 tx_dscr Set if the interrupt is triggered by a descriptor with the interrupt on packet end command 30 tx_derr Set if the controller ran out of descriptors during a packet transmission The channel will be stopped Software must disable and re enable the channel to clear this fault 31 tx...

Page 386: ..._1 00_1006_0938 Bits Name Default Description 15 0 addr 16 b0 The destination address to be matched in all bit positions selected by the ser_addr_mask register Bits 7 0 correspond to the first byte of the frame bits 15 8 to the second 63 16 notimp 48 bx Not implemented Table 245 Sequencer Table Entries ser_rx_table_0 0 15 00_1006_0600 0678 ser_rx_table_1 0 15 00_1006_0A00 0A78 ser_tx_table_0 0 15 ...

Page 387: ...C8 ser_rx_byte_lo_0 00_1006_05D0 ser_rx_byte_lo_1 00_1006_05D0 ser_rx_byte_hi_0 00_1006_05D8 ser_rx_byte_hi_1 00_1006_05D8 ser_tx_underrun_0 00_1006_05E0 ser_tx_underrun_1 00_1006_05E0 ser_rx_overflow_0 00_1006_05E8 ser_rx_overflow_1 00_1006_05E8 ser_rx_errors_0 00_1006_05F0 ser_rx_errors_1 00_1006_05F0 ser_rx_badaddr_0 00_1006_05F8 ser_rx_badaddr_1 00_1006_05F8 Bits Name Default Description 15 0 ...

Page 388: ...BCM1250 BCM1125 BCM1125H User Manual 10 21 02 Broadcom Corporation Page 360 Section 10 Serial Interfaces Document 1250_1125 UM100CB R This Page is left blank for notes ...

Page 389: ... multiplexed or 8 bit non multiplexed bus for the boot region is made using the reset time configuration options An additional reset option diverts accesses made to region 0 to the SMBus interface 0 to allow boot code to be fetched from an SMBus EEPROM see Section Booting Using an SMBus EEPROM on page 413 The address range initially assigned to region 0 also covers the physical address range 00_1F...

Page 390: ...ize register The size of the region is 64KB io_ext_mult_size 1 Since only 12 bits of the register are valid the minimum region size is 64KB and the maximum size is 256MB An alternative way of thinking about this is that the last address in the region has bits 39 30 all zero bits 29 16 equal to io_ext_start_addr io_ext_mult_size and bits 15 0 all ones If the last address of the region is set above ...

Page 391: ...t the address This is provided on the IO_ADP 3 0 pins which are available as GPIO pins if generic bus parity is disabled If parity is enabled for the system then each region can be configured in the io_ext_cfg register to have even odd or no parity check On read transactions from parity generating devices the parity bit of each byte of the incoming data is latched at the same time as the data and ...

Page 392: ... from the byte enables to the byte lanes is shown in Table 247 on page 363 GENERIC BUS TIMING The timing of the generic bus is configurable for each of the chip select regions When multiple devices are connected care must be taken to ensure that the timing for one device does not confuse other devices The chip select signals and idle time between cycles will normally be sufficient to ensure this I...

Page 393: ...ng to IO_WR_L or IO_OE_L deasserting and data being latched in a read access The chip select remains asserted oe_to_cs additional cycles idle_cycle 1 15 cycles 6 The number of cycles that the bus should be idle before the next IO_ALE Note that the cycle does not end until one cycle after the IO_CS_L line has deasserted ale_to_wr 1 7 cycles 7 The number of cycles from IO_ALE deassertion to IO_WR_L ...

Page 394: ...DEFINED behavior FIXED CYCLE READ ACCESS Figure 74 Fixed Cycle Read Access A fixed read cycle has the simplest timing The address is put out at the start of the cycle along with IO_ALE In the non multiplexed version the address remains stable until the end of the cycle and the data lines are high impedance until the device drives them In the multiplexed form the address stays valid until IO_CS_L a...

Page 395: ...s the fixed cycle read except IO_OE_L remains deasserted and the ale_to_wr and wr_width parameters are used to set the assertion of the IO_WR_L signal The data is output on the IO_AD lines with the assertion of chip select wr_width ale_to_wr cs_width ale_to_cs idle_cycle ale_width 1 cycle Address Data Address Data Non Muxed Muxed Parity clk100 io_ale io_ad 23 0 io_ad 31 24 io_ad 31 0 io_adp 3 0 io...

Page 396: ...ter IO_CS_L will be deasserted If the device does not signal that it is ready within the timeout period then the read will be aborted the timeout error status set the io_error_int interrupt will be raised and UNPREDICTABLE data flagged with a bus error will be returned In the case where the peripheral is using the IO_CLK100 and can meet the setup and hold time for IO_RDY the synchronizer may be by...

Page 397: ...asserted rdy_smple cycles after the ready signal is sampled The oe_to_cs parameter is used to set the number of cycles IO_CS_L remains asserted after IO_WR_L is deasserted If the device does not signal that it is ready within the timeout period then the write will be aborted the timeout error status set and the io_error_int interrupt will be raised ale_to_wr rdy_smple ale_to_cs idle_cycle ale_widt...

Page 398: ...asserted with IO_ALE The chip select and strobe IO_OE_L or IO_WR_L are asserted and data transferred as normal When the strobe deasserts again with the normal timing either there are no more transfers in the transaction and the access ends in the usual way or the chip select remains asserted through an idle period of 2 or more cycles before the strobe reasserts for the next data This is shown in F...

Page 399: ...le The ready signal should be held asserted for the remainder of the cycle to ensure the fastest burst or can be deasserted to delay the remaining accesses The chip select width can still be used to ignore the IO_RDY signal but this only applies to the first transfer in the burst i e ready is ignored from the chip select assertion for the cs_width but then must be valid for the rest of the cycle I...

Page 400: ... ROM with 240 ns access time from chip select and output enable The other configuration parameters are set based on the boot_mode configuration resistors as described in Table 250 The SMBus boot modes still use the generic bus module The SMBus interface 0 protocol engine is placed under the control of the generic bus controller Rather than run a generic bus cycle to fetch 32 bits of data a request...

Page 401: ...nterrupt To ensure consistent data software should therefore read the address data and parity registers before this status register In the acknowledgement mode if the access times out because the device does not signal ready the current transaction will be aborted in the case of burst mode the rest of the burst will not be completed If the access was a read then data marked with a bus error will b...

Page 402: ...le parity check 5 io_burst_en 1 b0 When high the interface will use the burst mode to run each transaction 6 io_parity_type 1 b0 When low even parity is used when high odd parity is used 7 io_nonmux 1 b0 When high the bus is used in non multiplexed mode with AD 31 24 being 8 bits of data and AD 23 0 being 24 bits of address If the io_width_sel is not set to 2 b00 for 8 bits then bus operation is U...

Page 403: ...06_1610 io_ext_time_cfg0_3 00_1006_1618 io_ext_time_cfg0_4 00_1006_1620 io_ext_time_cfg0_5 00_1006_1628 io_ext_time_cfg0_6 00_1006_1630 io_ext_time_cfg0_7 00_1006_1638 A write to any bit causes all bits to be written Bits Name Default Description 2 0 io_ale_width _0 3 h4 3 h1 Width of IO_ALE 3 early_cs 1 b0 If this bit is set the external chip select is asserted during the ale_width and ale_to_cs ...

Page 404: ...easserts before IO_CS_L deasserts In acknowledgement mode this parameter is also the number of cycles between IO_WR_L deasserts and IO_CS_L deasserts 15 14 io_cs_to_oe 2 h0 Number of cycles between IO_CS_L assertion and IO_OE_L assertion This parameter must be less than io_cs_width 63 16 notimp 48 bx Not implemented Table 256 Generic Bus Interrupt Status Register io_interrupt_status 00_1006_1A00 R...

Page 405: ...errupt_data0 00_1006_1A10 READ ONLY Bits Name Default Description 15 0 io_int_data0 16 h0 This register contains bits 15 0 of the data containing the parity error or captured when the timeout expired 63 16 notimp 48 bx Not implemented Table 258 Generic Bus Error Data Register 1 io_interrupt_data1 00_1006_1A18 READ ONLY Bits Name Default Description 15 0 io_int_data1 16 h0 This register contains bi...

Page 406: ...16 of the address causing the interrupt 63 16 notimp 48 bx Not implemented Table 263 Generic Bus Error Parity Register io_interrupt_parity 00_1006_1A50 READ ONLY Bits Name Default Description 3 0 io_int_parity 4 h0 This register contains the parity of the data that generated the error 63 4 notimp 60 bx Not implemented Table 264 Output Drive Control Register 0 io_drive_0 00_1006_1300 A write to any...

Page 407: ... Drive Control Register 1 io_drive_1 00_1006_1308 A write to any bit causes all bits to be written Bits Name Default Description 1 0 reserved 2 b11 Reserved 3 2 io_drv_E 2 b01 8 mA Group E drive strength control High drive 6 8 10 12 mA Uses Slew0 GPIO 11 6 GPIO 1 0 5 4 reserved 2 b11 Reserved 7 6 io_drv_F 2 b01 8 mA Group F drive strength control High drive 6 8 10 12 mA Uses Slew0 GPIO 5 2 IO_ADP ...

Page 408: ...Slew2 control for I O groups M and P 15 14 io_drv_M 2 b11 12 mA Group M drive strength control High drive 6 8 10 12mA Uses Slew2 E0_TXEN F0_TXC0 E0_TXER F0_TXC1 E0_TXD 7 0 F0_TXD 7 0 E1_TXEN F1_TXD4 E1_TXER F1_TXD5 E1_TXD 7 0 F0_TXD 15 8 63 16 notimp 48 bx Not implemented Table 267 Output Drive Control Register 3 io_drive_3 00_1006_1318 A write to any bit causes all bits to be written Bits Name De...

Page 409: ...User Manual BCM1250 BCM1125 BCM1125H 10 21 02 Broadcom Corporation Document 1250_1125 UM100CB R Section 11 Generic Boot Bus Page 381 This Page is left blank for notes ...

Page 410: ...BCM1250 BCM1125 BCM1125H User Manual 10 21 02 Broadcom Corporation Page 382 Section 11 Generic Boot Bus Document 1250_1125 UM100CB R This Page is left blank for notes ...

Page 411: ... by a card with a 16 bit data path Detection of card insertion and removal CD1 and CD2 the VCC voltage requested by the card VS1 and VS2 card READY and write protect state WP Software control of the PCMCIA REG signal to select between accessing regular memory and attribute memory and the card RESET signal Outputs to control a supply of VCC and VPP to the card VCC can either be controlled from soft...

Page 412: ... The databus connections for the PCMCIA card reflect the little endian nature of the PCMCIA bus and the big endian byte lane assignment on the generic bus So data 7 0 of the PCMCIA slot should connect via an isolation buffer to IO_AD 31 24 and data 15 8 of the PCMCIA slot should connect through a buffer to IO_AD 23 16 This allows use of both 8 bit and 16 bit cards Figure 80 Example PCMCIA Slot Con...

Page 413: ...ster will be set high when there is no card detected The WP write protect and READY status signals from the card are monitored and made available to software Each of these signals has a transition detector and can raise the pcmcia_interrupt when they change These signals have a 60ns glitch filter The VS1 and VS2 voltage sense signals are monitored and made available to software they have a 60ns gl...

Page 414: ...ured by setting the apron_en bit in the pcmcia_cfg register When this bit is set the hardware detects the VS1 and VS2 signals and will enable the requested power to the card The following table summarizes the VCC power control options This table includes the options for controlling the power enable output bits when the PCMCIA mode is not selected at reset time this is discussed below in Section Us...

Page 415: ...ower Enable Truth Table Cont Mode Control Bits Input signals from PCMCIA card Software Control Bits in pcmcia_cfg Card State Power Outputs Reset AD 16 PCMCIA mode enable pcmcia_cfg pwr_ctl bit CD1 GPIO 12 CD2 GPIO 13 VS1 GPIO 14 VS2 GPIO 15 apron cfg3v cfg5V PC_EN3V PC_EN5V Note In the case of both PC_EN5V and PC_EN3V being asserted which can only be done under software control the PCMCIA power sw...

Page 416: ...his behavior so for cards which need this indicated in the TPCE_IO field of the CISTPL_CFTABLE_ENTRY configuration tuple either the interface must be configured for 8 bit only operations or a software restriction made to ensure only 8 bit accesses are done to registers that are 8 bits The PCMCIA specification indicates that on any card that has a mixture of 8 and 16 bit registers byte registers th...

Page 417: ...low state which selects the common memory The card timing is configured using the generic bus timing registers Since these default to being appropriate for the boot ROM see Section Generic Bus Timing on page 365 software should configure the timing in region 6 for PCMCIA access at system startup The first access to a card after power on should be an attribute memory read The pcmcia_cfg_reg bit sho...

Page 418: ...used for the card timing and the propagation delays of the buffers are chosen for illustration only and do not necessarily match any real devices Table 271 Example Flash Card AC Specs Parameter Name Min ns Max ns Read Cycle Time tRC 150 Address Access Time tAcca 150 Card Enable Access Time tAccce 150 Output Enable Access Time tAccoe 80 Output Disable Time tDis 50 Write Cycle Time tWC 150 Write Pul...

Page 419: ...1 0 D wr 31 0 IO_OE wr IO_WR wr Asserted for low data byte Asserted for low data byte Asserted for high data byte Asserted for high data byte Address latched on ALE enabled by IO_CS 6 Address latched on ALE enabled by IO_CS 6 t_ale_width t_ale_to_cs t_cs_width t_ce_to_oe t_oe_to_cs t_bus_idle tAccoe 160ns tAccce 160ns t_ale_to_wr t_wr_width tSUcewe 70ns tWP 80ns tHce 20ns tRC 220ns tSUd 130ns tSUc...

Page 420: ...te width tWP which directly requires the wr_width to be 8 and the address to write deassertion setup time tSUaweh Fortunately once these are set the data hold time is satisfied with the same chip select width as for the read USING THE POWER OUTPUTS If the PCMCIA mode is not enabled by the reset time configuration resistor then the three power control lines can be controlled by software directly th...

Page 421: ... is set this bit is set low whenever no card is detected In Non PCMCIA mode this pin allows software control of the ENVPP output 4 pcmcia_cfg_reset 1 b1 When high apply reset to the pcmcia card This bit is set when the system is reset or whenever no card is detected 5 pcmcia_cfg_apron_en 1 b0 When high enable auto power on 6 pcmcia_cfg_cd_mask 1 b1 When high disable Card detect interrupt When low ...

Page 422: ... PC_WP from the PCMCIA card When high write protect is enabled 5 pcmcia_status_rdy ext This bit reflects the state of the ready signal PC_READY from the PCMCIA card When high indicates the card is ready for access 6 pcmcia_status_3v_en 1 b0 When high indicates 3 volt VCC is enabled This bit reflects the value driven on the PC_EN3V signal 7 pcmcia_status_5v_en 1 b0 When high indicates 5 volt VCC is...

Page 423: ...User Manual BCM1250 BCM1125 BCM1125H 10 21 02 Broadcom Corporation Document 1250_1125 UM100CB R Section 12 PCMCIA Control Interface Page 395 This Page is left blank for notes ...

Page 424: ...s state even when the line is configured as an input so if an open collector output is required the output register only needs to be set low once and the direction of the pin can be changed from output to pull low to input to float The input path is always active An optional inverter is enabled by setting the corresponding bit in the gpio_input_invert register The 100MHz reference clock is used to...

Page 425: ... of the line if the GPIO pin is set as an output then the interrupt will be raised whenever the output is set appropriately after the glitch filtering delay Some of the GPIO pins are used by the PCMCIA controller and some to provide parity on the generic bus These functions are set by reset time configuration resistors on the generic bus AD lines When used for PCMCIA operation the input inverters ...

Page 426: ...Both GPIO pins are level sensitive interrupts 11 The even numbered pin is an edge sensitive interrupt The odd numbered pin is a level sensitive interrupt 3 2 int_type2 2 b0 5 4 int_type4 2 b0 7 6 int_type6 2 b0 9 8 int_type8 2 b0 11 10 int_type10 2 b0 13 12 int_type12 2 b0 15 14 int_type14 2 b0 63 16 notimp 48 bx Not Implemented Table 278 GPIO Read Register gpio_read 00_1006_1AA0 READ ONLY Bits Na...

Page 427: ...ion 00_1006_1AA8 Bits Name Default Description 1 0 gpio_ddr 2 h0 High for output driven from the output latch low for input If the synchronous serial interface RstrobeOut output is enabled this register is ignored and the pin will be an output 5 2 gpio_ddr 4 h0 High for output low for input When generic bus parity is enabled these bits are ignored 15 6 gpio_ddr 10 h0 High for output low for input ...

Page 428: ... PCI interrupt lines can be used as active low level interrupt inputs as can the SERR and PERR signals If the PCI is in device mode the P_INTB_L P_INTC_L and P_INTD_L lines can be used as active low level interrupt lines MACS The MAC management interface provides the only pins that can easily be used from an unused MAC interface The MDIO line provides input and output and the MDC line is output on...

Page 429: ...User Manual BCM1250 BCM1125 BCM1125H 10 21 02 Broadcom Corporation Document 1250_1125 UM100CB R Section 13 GPIO Page 401 This Page is left blank for notes ...

Page 430: ...BCM1250 BCM1125 BCM1125H User Manual 10 21 02 Broadcom Corporation Page 402 Section 13 GPIO Document 1250_1125 UM100CB R This Page is left blank for notes ...

Page 431: ...fication that may be found on the SMBus web site at http www smbus org and the related documents Devices on the serial configuration bus may be masters or slaves or both The interface is always a master Masters can issue commands provide the clock and control the transfer Slaves respond to commands from masters and use the supplied clock Each slave has a unique 7 bit address or a few addresses tha...

Page 432: ...een transferred The transaction is then ended by the master signalling a stop which returns both lines to idle There may be multiple masters on the bus Most of the time they will see the start and stop framing of other masters to avoid collision however if two masters start at the same time they may collide In this case the first time their SDA signals differ the master that drives the line to zer...

Page 433: ...e with the transaction During the reset procedure accesses to the control registers are held off This will at most last for the first 90us after reset so it is unlikely to be noticed in practice SMBUS PROTOCOL The SMBus protocol defines a number of transfer types between the host and peripherals The interface implements all of these except for process call and block transfers The latest revision o...

Page 434: ...a command to the slave and read back a byte Write Word 010 Yes LSB MSB Send a command and two bytes to the slave Read Word 100 Yes LSB MSB Send a command to the slave and read two bytes EEPROM Read 111 Yes LSB MSB Send a command and one byte to the slave and read four bytes back This matches a 32 bit read from a 16 kbit EEPROM Table 285 Supported SMBus Transfer Types Cont Transfer Type smb_tt Comm...

Page 435: ... 286 followed by a repeated START and reading data as shown in Table 288 If PEC is enabled then an additional byte will be read into the smb_pec register before the NACK and STOP The command address may be null in which case the START shown in Table 288 will be a standard START not a repeated one The extended mode is invoked by setting the extend bit in the smb_start register this changes the inte...

Page 436: ...art 10 8 Data Format Operation 000 1 Byte 001 2 Bytes 010 3 Bytes 011 4 Bytes 100 No Data 101 5 Bytes S Slave Address Rd 1 7 1 1 8 1 Data 7 0 A P 1 A S Slave Address Rd A 1 7 1 1 8 1 Data 15 8 1 Data 7 0 A 8 1 P A S Slave Address Rd A 1 7 1 1 8 1 Data 15 8 A 1 Data 7 0 A P 8 1 A 1 Xtra 7 0 8 S Slave Address Rd A 1 7 1 1 8 1 Data 15 8 A 1 Data 7 0 A A P 8 1 1 Xtra 15 8 A 1 Xtra 7 0 8 8 S Slave Addr...

Page 437: ...the transaction finishes the busy bit will be cleared This can either be detected by polling the smb_status or by enabling the smb_finish interrupt The error bit indicates that an acknowledgement was not received from the slave device when the master attempted to start the transaction 5 Read the data from the smb_data register If one byte was requested only the lsb field will be valid 6 If PEC is ...

Page 438: ... by a read of four data bytes and optional PEC Typically the command and data byte will contain the address to be read The command sequence reflects this 1 Wait until the busy bit in the smb_status register is clear The interface will ignore accesses while the bit is set 2 Specify the command high address bits to be sent as the first byte by writing it in the smb_cmd register 3 Specify the data lo...

Page 439: ...bled the smb_pec register should be read Writing to a slave on the serial bus involves these steps 1 Wait until the busy bit in the smb_status register is clear The interface will ignore accesses while the bit is set 2 If an address command is needed write 8 or 16 bits to the smb_cmd register 3 Write the data to the smb_data and smb_xtra registers 4 If PEC is enabled an extra data byte should be w...

Page 440: ...neric bus chip select 0 While the SMBus interface is being used for booting any access to its control registers have UNPREDICTABLE results Once booting is complete software can clear bit 18 in the System Configuration register to allow normal SMBus use This will return the chip select 0 space to using the generic bus to service accesses Following SMBus use software must set the chip select 0 timin...

Page 441: ... the boot rom it will also be unable to make progress SWITCHING FROM SMBUS MODE Care must be taken when switching out of the SMBbus boot mode There must be no accesses in progress to the chip select 0 region when the switch is made or the system will behave in UNDEFINED ways for example a response could be lost Instruction fetches are a particular concern and careful location of instructions is re...

Page 442: ...se of chip select 1 to 00_1FC0_0000 It is important that the second group of instructions are together since they change the target of the next instruction fetch Again the sync instruction is used to ensure that the stores have completed before the CPU will issue the next instruction fetch If the chip select region 1 were located at a different address then there would be no need to move the chip ...

Page 443: ... smb_cmd_0 00_1006_0030 smb_cmd_1 00_1006_0038 Read returns value from previous smbus read command Write sets value for next smbus write command Bits Name Default Description 7 0 smb_cmd 8 h0 Write Low byte of command to be sent following address Read First byte received in type 5 or 6 extended mode read 15 8 smb_cmdh 8 h0 Write High byte of command to send in extended mode Read 2nd Byte received ...

Page 444: ...this bit shows the output of the serial clock generator that would be driven to the clock pin in normal mode Software may use this as a reference clock If direct mode is not enabled this bit is zero 7 smb_data_in 1 b0 In direct mode smb_direct set in the control register this bit shows the value on the data pin otherwise it is zero 63 8 notimp 56 bx Not implemented Table 293 SMBus Data Registers s...

Page 445: ...nterface 7 smb_qdata 1 b0 Bit of data to send as R W bit in a Quick Command Ignored write as zero for all other commands 10 8 smb_tt 3 h0 Value Transfer Type 000 1 byte write address command 001 2 byte write address command write least significant field of smb_data 010 3 byte write address command write both fields of smb_data 011 Command and 1 byte read address command address read byte into LB f...

Page 446: ... 15 8 010 Data 7 0 Data 15 8 Xtra 7 0 011 Data 7 0 Data 15 8 Xtra 7 0 Xtra 15 8 100 No data 101 Only valid for read transactions Cmd 7 0 Data 7 0 Data 15 8 Xtra 7 0 Xtra 15 8 110 Only valid for read transactions Cmd 7 0 Cmd 15 8 Data 7 0 Data 15 8 Xtra 7 0 Xtra 15 8 111 Reserved 12 11 smb_afmt 2 h0 Address Command Format Value Address Command Transfer 00 Only valid for read transactions No Address...

Page 447: ...User Manual BCM1250 BCM1125 BCM1125H 10 21 02 Broadcom Corporation Document 1250_1125 UM100CB R Section 14 Serial Configuration Interface Page 419 This Page is left blank for notes ...

Page 448: ...BCM1250 BCM1125 BCM1125H User Manual 10 21 02 Broadcom Corporation Page 420 Section 14 Serial Configuration Interface Document 1250_1125 UM100CB R This Page is left blank for notes ...

Page 449: ...vances each TCK rising edge as directed by the TMS level The states are as defined in the JTAG specification The IR scan branch is used to scan instructions into the Instruction register described in Section Instruction Register on page 424 The DR branch scans bits into and out of whatever data scan chain has been selected by an instruction When TRST_L is asserted or the TAP enters the Test Logic ...

Page 450: ...g Document 1250_1125 UM100CB R Figure 84 JTAG TAP State Machine Test Logic Reset Run Test Idle Select DR Scan Select IR Scan Capture DR Capture IR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Shift IR Exit1 IR Pause IR Exit2 IR Update IR 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 ...

Page 451: ...s the EJTAG Data Register 0x0A CONTROL Selects the EJTAG Control Register 0x0B EJTAGALL Selects the EJTAG Address Data and Control Registers 0x0C EJTAGBOOT Force the CPUs to boot in debug mode 0x0D NORMALBOOT Force the CPUs to boot in the normal mode 0x0E 0x1F EJTAG reserved Reserved for EJTAG 0x20 SYSCTRL Selects System Control and Status Register 0x21 TRACE Selects Trace Register for Scan Out 0x...

Page 452: ...elects the WaferId register to be connected between TDI and TDO The WaferId register is a 32 bit shift register containing a manufacturing lot code number The register is scanned out LSB 0x33 reserved 0x34 SCANMC Broadcom Use Only Selects MC Chain 0x35 reserved 0x36 SCANSCD Broadcom Use Only Selects SCD Scan Chain 0x37 reserved 0x38 SCANALL Broadcom Use Only Selects All Agent Scan Chains in Series...

Page 453: ...he Data Register as the captured data is shifted out via the TDO pin The Data Register is described in Section Data Register on page 439 CONTROL Instruction This instruction is used to select the EJTAG Control register to be connected between TDI and TDO The EJTAG Probe shifts 12 bits of data into the EJTAG Control register through the TDI pin and shifts out the current value via TDO The Control R...

Page 454: ...OOT state The Bypass register is selected when the EJTAGBOOT instruction is given NORMALBOOT Instruction When the NORMALBOOT instruction is given and Update IR state is left then the DBBOOT signal is deasserted and the PrTrap0 PrTrap1 and ProbEn bits in the EJTAG Control register are set to 0 Since DBBOOT is deasserted the CPUs will start at the standard Reset vector the next time they are reset T...

Page 455: ...ial interface 0 is in synchronous mode 13 ser0_rstb_en ext Configuration bit for IO_AD 13 that allocates GPIO 0 pin to the synchronous serial interface 14 ser1_enable ext Configuration bit for IO_AD 14 0 Serial interface 1 is in asynchronous uart mode 1 Serial interface 1 is in synchronous mode 15 ser1_rstb_en ext Configuration bit for IO_AD 15 that allocates GPIO 1 pin to the synchronous serial i...

Page 456: ...CPU 1 will be held in reset This bit is set on a BCM1250 reset causing the processor to remain in reset until released under software control 56 unicpu0 1 b0 Set to indicate uniprocessor using physical processor 0 This bit will always be set on the BCM1125 H 57 unicpu1 1 b0 Set to indicate uniprocessor using physical processor 1 58 sb_softres 1 b0 When a write changes this bit from a 0 to a 1 a so...

Page 457: ... that the contents of the system control register are not reset This allows testing of various modes TRACE Instruction When the TRACE instruction is set the trace_read register is selected between TDI and TDO This is a read only register It is scanned out LSB first The trace buffer should be frozen and the startread bit set prior to reading out This is a 64 bit register and gets the next 64 bits o...

Page 458: ...4 Table 304 Trace Control Scan Chain Bits Register Description 31 0 trace_event_0 31 0 Trace Event Registers See Table 46 on page 72 63 32 trace_event_1 31 0 95 64 trace_event_2 31 0 127 96 trace_event_3 31 0 152 128 trace_sequence_0 24 0 Trace sequence Registers See Table 47 on page 74 177 153 trace_sequence_1 24 0 202 178 trace_sequence_2 24 0 227 203 trace_sequence_3 24 0 259 228 trace_event_4 ...

Page 459: ... register is selected between TDI and TDO when INTEST or EXTEST instructions are set in the instruction register When the TAP controller traverses the Capture DR state the inputs are sampled into the shadow register During the Shift DR state of the TAP controller the contents of the boundary scan shadow register are shifted in between TDI and TDO When the Update DR state is traversed the contents ...

Page 460: ...for most of the pins on the part All the pins apart from HyperTransport use this input output pin building block It consists of three BC_1 scan cells one for the output one for the output enable and one for the input The Mode signal causes the JTAG to drive both the INTEST and EXTEST data Figure 85 JTAG Boundary Scan Register Block TDI Out shift_dr Mode pad out enable input Mode TDO update_dr cloc...

Page 461: ...ut from the shadow register At the same time the next test pattern can be scanned in The differential signals on the HyperTransport interface are scanned a little differently All of these are unidirectional but the signals are also differential and double data rate The data rate is doubled and the differential is formed in the output pads the differential is received and the data rate halved in th...

Page 462: ...ve driving pins or into the part and scan other internal registers because the boundary scan must be made inactive when a non BSR instruction is scanned in to the instruction register The large ammount of internal state in the part makes it useful to be able to do this so the BSRMODE instruction has been added If the BSRMODE instruction is used after EXTEST CLAMP or INTEST then the BSR mode is mai...

Page 463: ...gister These are described in the subsequent sections JTAG commands are provided for scanning these registers individually or as a concatenated chain There are two Control Register bits that set the behavior of the probe agent The ProbEn bit enables accesses to the EJTAG range and the MaSl bit selects if the probe is a master or a slave Table 307 shows the behavior for the possible cases Table 307...

Page 464: ...quests When it needs to run an access for example to read memory it will scan in the Control Register with the MaSl bit set A check needs to be done for CPU accesses that may have arrived while the mode was being changed once they are serviced the interface is ready for the master access Need JTAG Scan Out Scan In Out to ZBbus EJTAG Control Register PrAcc Bit 1 Service CPU Access Y N N Y PrAcc Bit...

Page 465: ...ll then scan out the Address Register decode A_CMD as a write scan the Data Register and write the data in the debugger memory It will then scan in the Control Register with the PrAcc bit cleared causing the JTAG unit to free up the buffers and allow more transactions The CPU can map the JTAG space cacheable non coherent or uncacheable It must not be mapped cacheable coherent or the behavior of th...

Page 466: ...er the byte address associated with each byte lane depends on the system endian mode as shown in Table 5 on page 24 Table 308 JTAG Address Register Scan Chain Bits ZBbus signal see Table 2 on page 20 Description 34 0 A_AD 39 5 Address 66 35 A_BE 31 0 Byte Enables Indicate which byte lanes are valid in the Data Register see Table 5 on page 24 for the mapping from byte enable to byte address 69 67 A...

Page 467: ... to CPU1 to be set This allows the probe to signal a debug interrupt to CPU1 The bit must be cleared to remove the interrupt On the BCM1125 H this bit is not used R W 0 4 PrTrap0 Probe Trap0 Setting this bit to 1 forces the DBBOOT signal to CPU0 to 1 This allows the probe to force CPU0 into debug mode upon the next deassertion of reset This bit is set on the Update IR state of the EJTAGBOOT instru...

Page 468: ...ion The JTAG unit clears this bit when the transaction has been completed This bit can only be set if the ProbEn bit is cleared Probe initiated transactions can occur only if the MaSl bit is set 0 No pending probe access 1 Pending probe access If the probe writes a zero to this bit it is ignored The only way the bit can be set is by the probe writing a 1 the only way the bit can be cleared is by t...

Page 469: ...ector location is FFFF_FFFF_B000_0480 Set by SW in EDEBUG register Set by DBBOOT signal from JTAG TAP in EJTAG control register 2 3 5 2 3 6 Hardware breakpoints watchpoints can be done in extended debug mode using the regular Watch registers not special ones 2 3 7 Watch register exceptions are precise for both data and instructions 2 6 3 Processor reset is done through System Config register not E...

Page 470: ...Supported works with additional MaSl bit to set direction ProbTrap Two Copies one per CPU Also causes EJTAG boot on reset EjtagBrk Two Copies one per CPU level sensitive probe must clear DM Two copies But shows CPU EDEN signal rather than DM 5 6 3 Rocc is not supported 5 6 4 Processor access is through physical address 00_1000_0000 00_1001_FFFF and uses ZBbus request There is an additional mode fo...

Page 471: ...User Manual BCM1250 BCM1125 BCM1125H 10 21 02 Broadcom Corporation Document 1250_1125 UM100CB R Section 15 JTAG and Debug Page 443 This Page is left blank for notes ...

Page 472: ...BCM1250 BCM1125 BCM1125H User Manual 10 21 02 Broadcom Corporation Page 444 Section 15 JTAG and Debug Document 1250_1125 UM100CB R This Page is left blank for notes ...

Page 473: ...rs will be ignored Table 311 Internal Register Addresses by Function Name Address Table Page Description Memory Controller mc_config_0 00_1005_1100 72 135 Channel 0 attributes mc_dramcmd_0 00_1005_1120 75 139 Channel 0 SDRAM command mc_drammode_0 00_1005_1140 76 139 Channel 0 SDRAM mode mc_timing1_0 00_1005_1160 77 140 Channel 0 SDRAM timing 1 mc_timing2_0 00_1005_1180 78 141 Channel 0 SDRAM timin...

Page 474: ...is range of addresses will write the value x to l2_cache_disable 3 0 register See Section Reduced Cache Size on page 94 l2_misc_config 00_1004_3x00 99 Accesses made to this range of addresses will write the value x to l2_misc_config 3 0 register See Section Cache Configuration Register on page 99 PCI Host Bridge Type 00 PCI header 00_FE00_0000 00_FE00_00FF 127 236 Configuration space bus 0 dev 0 H...

Page 475: ...ame configuration mac_rx_fifo_ptrs_0 00_1006_4120 186 314 MAC FIFO pointers Debug Read Only mac_tx_fifo_ptrs_0 00_1006_4128 186 314 MAC FIFO pointers Debug Read Only mac_adfilter_cfg_0 00_1006_4200 192 316 MAC receive address filter configuration register mac_ethernet_addr_0 00_1006_4208 190 315 MAC source ethernet address for insertion during transmission mac_type_cfg_0 00_1006_4210 191 316 MAC p...

Page 476: ... mask register dma_asic_addr_mac_0 00_1006_4418 94 166 ASIC mode base address mac_txd_ctl_0 00_1006_4420 178 306 Transmit DMA control register mac_mdio_0 00_1006_4428 194 318 MDIO pin control register mac_debug_status_0 00_1006_4448 184 313 MAC status error register Debug Read Only no side effects dma_config0_mac_0_rx_ch_0 00_1006_4800 91 163 DMA config 0 register dma_config1_mac_0_rx_ch_0 00_1006...

Page 477: ... B duart_rx_hold_reg_b 00_1006_0260 203 329 RX holding register port B Read Only read pops character from FIFO duart_tx_hold_reg_b 00_1006_0270 204 330 TX holding register port B Write Only duart_opcr_b 00_1006_0280 211 332 Output port control register alias that only alters port B bits duart_aux_ctrl_b 00_1006_0290 213 332 Aux control register alias that only alters port B bits duart_inport_chng ...

Page 478: ...current descriptor A Read Only dma_cur_dscr_b_ser_0_tx 00_1006_04A8 97 167 Transmit DMA current descriptor B Read Only dma_cur_daddr_ser_0_tx 00_1006_04B0 98 167 Transmit DMA current descriptor address Read Only ser_mode_0 00_1006_0500 231 354 Mode select ser_minfrm_sz_0 00_1006_0508 237 356 Min frame size ser_maxfrm_sz_0 00_1006_0510 238 357 Max frame size ser_addr_mask_0 00_1006_0518 243 359 Add...

Page 479: ...ble7_0 00_1006_0638 245 359 Sequence table ser_rx_table8_0 00_1006_0640 245 359 Sequence table ser_rx_table9_0 00_1006_0648 245 359 Sequence table ser_rx_table10_0 00_1006_0650 245 359 Sequence table ser_rx_table11_0 00_1006_0658 245 359 Sequence table ser_rx_table12_0 00_1006_0660 245 359 Sequence table ser_rx_table13_0 00_1006_0668 245 359 Sequence table ser_rx_table14_0 00_1006_0670 245 359 Seq...

Page 480: ...ad Only dma_cur_daddr_ser_1_tx 00_1006_08B0 98 167 Transmit DMA current descriptor address Read Only ser_mode_1 00_1006_0900 231 354 Mode select ser_minfrm_sz_1 00_1006_0908 237 356 Min frame size ser_maxfrm_sz_1 00_1006_0910 238 357 Max frame size ser_addr_mask_1 00_1006_0918 243 359 Address mask ser_usr0_addr_1 00_1006_0920 244 359 Match address 0 ser_usr1_addr_1 00_1006_0928 244 359 Match addre...

Page 481: ...0 245 359 Sequence table ser_rx_table9_1 00_1006_0A48 245 359 Sequence table ser_rx_table10_1 00_1006_0A50 245 359 Sequence table ser_rx_table11_1 00_1006_0A58 245 359 Sequence table ser_rx_table12_1 00_1006_0A60 245 359 Sequence table ser_rx_table13_1 00_1006_0A68 245 359 Sequence table ser_rx_table14_1 00_1006_0A70 245 359 Sequence table ser_rx_table15_1 00_1006_0A78 245 359 Sequence table ser_t...

Page 482: ... size in 64KB units io_ext_start_addr_0 00_1006_1200 253 376 cs0 region start address put outside generic bus range to disable io_ext_start_addr_1 00_1006_1208 253 376 cs1 region start address put outside generic bus range to disable io_ext_start_addr_2 00_1006_1210 253 376 cs2 region start address put outside generic bus range to disable io_ext_start_addr_3 00_1006_1218 253 376 cs3 region start a...

Page 483: ...nly io_interrupt_data2 00_1006_1a20 259 378 Data latched on generic interrupt assertion Read Only io_interrupt_data3 00_1006_1a28 260 378 Data latched on generic interrupt assertion Read Only io_interrupt_addr0 00_1006_1a30 261 379 Address latched on generic interrupt assertion Read Only io_interrupt_addr1 00_1006_1a40 262 379 Address latched on generic interrupt assertion Read Only io_interrupt_p...

Page 484: ...smb_serial_control_0 00_1006_0060 291 416 SMB port control register smb_serial_control_1 00_1006_0068 291 416 SMB port control register smb_serial_pec_0 00_1006_0070 295 418 SMB port pec register smb_serial_pec_1 00_1006_0078 295 418 SMB port pec register SCD Timers watchdog_timer_init_cnt_0 00_1002_0050 23 59 Watchdog initial count watchdog_timer_cnt_0 00_1002_0058 24 59 Watchdog current count Re...

Page 485: ...14 43 Read Only Manufacturing Information Register SCD Address Trap addr_trap_index 00_1002_00b0 40 68 Index of interrupting trap Read Only addr_trap_reg 00_1002_00b8 42 68 Address of interrupting trap Read Only read clears interrupt addr_trap_reg_debug 00_1002_0460 41 68 Address of interrupting trap Read Only No side effects addr_trap_up_cfg_0 00_1002_0400 43 68 Top of address trap range addr_tra...

Page 486: ...lear bits in mailbox_cpu_0 by writing 1s to this location Write Only interrupt_status0_0 00_1002_0100 21 52 Status of mapped interrupt sources Read Only interrupt_status1_0 00_1002_0108 21 52 Status of mapped interrupt sources Read Only interrupt_status2_0 00_1002_0110 21 52 Status of mapped interrupt sources Read Only interrupt_status3_0 00_1002_0118 21 52 Status of mapped interrupt sources Read ...

Page 487: ...ce to IRQ map register interrupt_map28_0 00_1002_02e0 18 47 Source to IRQ map register interrupt_map29_0 00_1002_02e8 18 47 Source to IRQ map register interrupt_map30_0 00_1002_02f0 18 47 Source to IRQ map register interrupt_map31_0 00_1002_02f8 18 47 Source to IRQ map register interrupt_map32_0 00_1002_0300 18 47 Source to IRQ map register interrupt_map33_0 00_1002_0308 18 47 Source to IRQ map re...

Page 488: ... to IRQ map register interrupt_map63_0 00_1002_03f8 18 47 Source to IRQ map register int_mapper_1 00_1002_2000 2000 23f8 Registers for CPU 1 interrupt mapper 2000 from CPU 0 SCD Performance Counters perf_cnt_cfg 00_1002_04c0 31 61 Performance counter control perf_cnt_0 00_1002_04d0 32 62 Performance counter perf_cnt_1 00_1002_04d8 32 62 Performance counter perf_cnt_2 00_1002_04e0 32 62 Performance...

Page 489: ...2_0a88 47 74 Trace sequence and action trace_sequence_6 00_1002_0a90 47 74 Trace sequence and action trace_sequence_7 00_1002_0a98 47 74 Trace sequence and action SCD Data Mover dm_dscr_base_0 00_1002_0b00 114 184 Data Mover channel 0 ring base address Read clears some bits dm_dscr_count_0 00_1002_0b08 116 185 Data Mover channel 0 descriptor count dm_dscr_addr_0 00_1002_0b10 117 185 Data Mover cha...

Page 490: ... bits dm_dscr_count_3 00_1002_0b68 116 185 Data Mover channel 3 descriptor count dm_dscr_addr_3 00_1002_0b70 117 185 Data Mover channel 3 current address Read Only dm_debug_dscr_base_3 00_1002_0b78 115 184 Debug alias for channel 3 ring base address Read Only no side effects dm_partial_3 00_1002_0bb8 120 186 CRC Checksum partial result register crc_def_0 00_1002_0b80 118 185 CRC definition registe...

Page 491: ...t Read Only watchdog_timer_cfg_0 00_1002_0060 25 59 Watchdog configuration Write clears interrupt general_timer_init_cnt_0 00_1002_0070 26 60 General timer initial count general_timer_init_cnt_1 00_1002_0078 26 60 General timer initial count general_timer_cnt_0 00_1002_0080 27 60 General timer current count Read Only general_timer_cnt_1 00_1002_0088 27 60 General timer current count Read Only gene...

Page 492: ...0 18 47 Source to IRQ map register interrupt_map3_0 00_1002_0218 18 47 Source to IRQ map register interrupt_map4_0 00_1002_0220 18 47 Source to IRQ map register interrupt_map5_0 00_1002_0228 18 47 Source to IRQ map register interrupt_map6_0 00_1002_0230 18 47 Source to IRQ map register interrupt_map7_0 00_1002_0238 18 47 Source to IRQ map register interrupt_map8_0 00_1002_0240 18 47 Source to IRQ ...

Page 493: ...rce to IRQ map register interrupt_map41_0 00_1002_0348 18 47 Source to IRQ map register interrupt_map42_0 00_1002_0350 18 47 Source to IRQ map register interrupt_map43_0 00_1002_0358 18 47 Source to IRQ map register interrupt_map44_0 00_1002_0360 18 47 Source to IRQ map register interrupt_map45_0 00_1002_0368 18 47 Source to IRQ map register interrupt_map46_0 00_1002_0370 18 47 Source to IRQ map r...

Page 494: ...g trap Read Only No side effects perf_cnt_cfg 00_1002_04c0 31 61 Performance counter control perf_cnt_0 00_1002_04d0 32 62 Performance counter perf_cnt_1 00_1002_04d8 32 62 Performance counter perf_cnt_2 00_1002_04e0 32 62 Performance counter perf_cnt_3 00_1002_04e8 32 62 Performance counter bus_err_status 00_1002_0880 35 65 Bus error status Read Only bus_err_data_0 00_1002_08a0 37 65 Data or addr...

Page 495: ...0 ring base address Read Only no side effects dm_dscr_base_1 00_1002_0b20 114 184 Data Mover channel 1 ring base address Read clears some bits dm_dscr_count_1 00_1002_0b28 116 185 Data Mover channel 1 descriptor count dm_dscr_addr_1 00_1002_0b30 117 185 Data Mover channel 1 current address Read Only dm_debug_dscr_base_1 00_1002_0b38 115 184 Debug alias for channel 1 ring base address Read Only no ...

Page 496: ...Last address tag in a read for testing l2_ecc_address 00_1004_0038 56 100 Read only Last address with ecc error correctable or not l2_misc_value 00_1004_0058 57 100 Read only PERIPH_REV3 and later Value of L2 hidden registers l2_way_disable 00_1004_1x00 91 Accesses made to this range of addresses will write the value x to l2_wayen 3 0 register If l2_wayen i is clear Way i is removed from the L2 re...

Page 497: ... smb_serial_xtra_0 00_1006_0000 294 417 SMB port extra data register smb_serial_xtra_1 00_1006_0008 294 417 SMB port extra data register smb_serial_freq_0 00_1006_0010 289 416 Frequency for SMB port smb_serial_freq_1 00_1006_0018 289 416 Frequency for SMB port smb_serial_status_0 00_1006_0020 292 417 SMB port status Read clears finish interrupt smb_serial_status_1 00_1006_0028 292 417 SMB port sta...

Page 498: ...ntrol register alias that only alters port B bits duart_inport_chng 00_1006_0300 206 330 Input port change register Read Only read clears duart_aux_cntrl 00_1006_0310 212 332 Aux control register duart_isr_a 00_1006_0320 215 333 Interrupt status register port A Read Only duart_imr_a 00_1006_0330 218 334 Interrupt mask register port A duart_isr_b 00_1006_0340 216 333 Interrupt status register port ...

Page 499: ...ess mask ser_usr0_addr_0 00_1006_0520 244 359 Match address 0 ser_usr1_addr_0 00_1006_0528 244 359 Match address 1 ser_usr2_addr_0 00_1006_0530 244 359 Match address 2 ser_usr3_addr_0 00_1006_0538 244 359 Match address 3 ser_cmd_0 00_1006_0540 233 355 Command ser_tx_rd_thrsh_0 00_1006_0560 235 356 Transmit FIFO read threshold ser_tx_wr_thrsh_0 00_1006_0568 234 356 Transmit FIFO write threshold ser...

Page 500: ...14_0 00_1006_0670 245 359 Sequence table ser_rx_table15_0 00_1006_0678 245 359 Sequence table ser_tx_table0_0 00_1006_0700 245 359 Sequence table ser_tx_table1_0 00_1006_0708 245 359 Sequence table ser_tx_table2_0 00_1006_0710 245 359 Sequence table ser_tx_table3_0 00_1006_0718 245 359 Sequence table ser_tx_table4_0 00_1006_0720 245 359 Sequence table ser_tx_table5_0 00_1006_0728 245 359 Sequence ...

Page 501: ...00_1006_0928 244 359 Match address 1 ser_usr2_addr_1 00_1006_0930 244 359 Match address 2 ser_usr3_addr_1 00_1006_0938 244 359 Match address 3 ser_cmd_1 00_1006_0940 233 355 Command ser_tx_rd_thrsh_1 00_1006_0960 235 356 Transmit FIFO read threshold ser_tx_wr_thrsh_1 00_1006_0968 234 356 Transmit FIFO write threshold ser_rx_rd_thrsh_1 00_1006_0970 236 356 Receive FIFO read threshold ser_line mode_...

Page 502: ..._1 00_1006_0A78 245 359 Sequence table ser_tx_table0_1 00_1006_0B00 245 359 Sequence table ser_tx_table1_1 00_1006_0B08 245 359 Sequence table ser_tx_table2_1 00_1006_0B10 245 359 Sequence table ser_tx_table3_1 00_1006_0B18 245 359 Sequence table ser_tx_table4_1 00_1006_0B20 245 359 Sequence table ser_tx_table5_1 00_1006_0B28 245 359 Sequence table ser_tx_table6_1 00_1006_0B30 245 359 Sequence tab...

Page 503: ... address put outside generic bus range to disable io_ext_start_addr_4 00_1006_1220 253 376 cs4 region start address put outside generic bus range to disable io_ext_start_addr_5 00_1006_1228 253 376 cs5 region start address put outside generic bus range to disable io_ext_start_addr_6 00_1006_1230 253 376 cs6 region start address put outside generic bus range to disable io_ext_start_addr_7 00_1006_1...

Page 504: ...eneric interrupt assertion Read Only io_interrupt_addr1 00_1006_1a40 262 379 Address latched on generic interrupt assertion Read Only io_interrupt_parity 00_1006_1a50 263 379 Parity latched on generic interrupt assertion Read Only pcmcia_cfg 00_1006_1a60 273 394 PCICMA controller configuration pcmcia_status 00_1006_1a70 274 395 PCMCIA controller status Read Only read clears interrupt gpio_clr_edge...

Page 505: ...07 Ethernet interface FIFO threshold configuration register mac_vlantag_0 00_1006_4110 181 310 VLAN tag for insertion into packets on transmit mac_frame_cfg_0 00_1006_4118 180 308 Ethernet interface MAC frame configuration mac_rx_fifo_ptrs_0 00_1006_4120 186 314 MAC FIFO pointers Debug Read Only mac_tx_fifo_ptrs_0 00_1006_4128 186 314 MAC FIFO pointers Debug Read Only mac_adfilter_cfg_0 00_1006_42...

Page 506: ...upt mask register dma_asic_addr_mac_0 00_1006_4418 94 166 ASIC mode base address mac_txd_ctl_0 00_1006_4420 178 306 Transmit DMA control register mac_mdio_0 00_1006_4428 194 318 MDIO pin control register mac_status1_0 00_1006_4430 183 313 MAC status error register Read Only read clears ch 1 mac_debug_status_0 00_1006_4448 184 313 MAC status error register Debug Read Only no side effects dma_config...

Page 507: ...CB R Section 16 Reference Page 479 Type 00 PCI header 00_FE00_0000 00_FE00_00FF 127 236 Configuration space bus 0 dev 0 Type 01 PCI header 00_FE00_0800 00_FE00_08FF 140 245 Configuration space bus 0 dev 1 Table 312 Internal Registers Ordered by Address Cont Name Address Table Page Description ...

Page 508: ...BCM1250 BCM1125 BCM1125H User Manual 10 21 02 Broadcom Corporation Page 480 Section 16 Reference Document 1250_1125 UM100CB R ...

Page 509: ...12 215 235 240 241 364 369 374 Bus Error Exceptions 18 Bus Width 365 bus_err_data 65 bus_err_status 17 18 53 65 bus_err_status_debug 65 bus_io_error 364 bus_l2_errors 17 66 bus_mem_io_errors 17 18 66 BusErr DPA 18 C Cache Block 5 cache error 17 Cache Error Exceptions 17 Cache Line 5 Cache Management Access 94 cacheability attribute 68 69 89 CacheErr D 17 CacheErr DPA 17 CacheErr I 17 CAS time chec...

Page 510: ... 330 duart_inport_chng_a 331 duart_inport_chng_b 331 duart_inport_chng_debug 331 duart_isr 325 333 334 duart_isr_a 325 duart_isr_b 325 duart_mode_reg_1 323 324 326 327 duart_mode_reg_2 323 324 327 duart_opcr 322 324 331 340 342 duart_out_port 324 335 duart_rx_hold 326 329 duart_set_opr 324 335 duart_status 323 328 duart_tx_hold 323 330 E ECC 125 ECC Diagnostic Management Accesses ECC diag bits non...

Page 511: ... 234 Diagnostic Receive CRC Expected 255 Diagnostic Receive CRC Received 255 double hosted chain 212 EOI 198 Error Control Register 253 Error Status Register 254 expansion space 194 function 234 generating interrupt messages 199 I O space 195 interrupt acknowledgement 199 Isochronous BAR 252 isochronous bit 211 Isochronous Ignore Mask 253 Link Configuration Register 251 Link Control Register 250 L...

Page 512: ...ptrs 314 mac_status 157 271 273 277 285 286 310 mac_status_0 54 mac_status_1 54 mac_status_2 54 mac_status_debug 286 mac_status1 286 313 mac_status1_0 56 mac_status1_1 56 mac_status1_2 56 mac_thrsh_cfg 272 275 294 307 mac_txd_ctl 274 306 mac_type_cfg 316 mac_vlantag 152 164 274 285 310 MACs 401 mailbox 48 49 mailbox_0 46 mailbox_1 46 mailbox_cpu 46 Management Interface to PHY 287 Mapping 109 mbox_...

Page 513: ...nd HyperTransport Fabric 190 PCI Bus To HyperTransport Fabric 219 PCI Configuration Header 236 PCI Full Access Space 199 PCI I O Space 195 PCMCIA 384 attribute memory 386 status signals 386 PCMCIA Power Control Pins 401 pcmcia_cfg 386 387 390 393 394 pcmcia_status 395 PEC 406 Peer to Peer Accesses 219 perf_cnt 62 perf_cnt_cfg 61 Performance Monitoring Features 134 Performance of the PCI and HyperT...

Page 514: ...chronous Serial Loopback 352 Synchronous Serial Protocol Engine 344 system 41 System Control and Debug Unit 41 System Overview 9 System Reset Initialization of the HyperTransport Interface 256 system_cfg 41 42 43 321 373 system_manuf 43 system_reset 41 system_revision 41 42 system_scratch 42 45 T TCP 178 180 TCP checksum 283 Terminology 5 The GPIO Pins 397 Timer Registers 59 Timer Special Cases 58...

Page 515: ...BCM1250 BCM1125 BCM1125H User Manual 10 21 02 Broadcom Corporation Page vii Index Document 1250_1125 UM100CB R ...

Page 516: ...y function or design Information furnished by Broadcom Corporation is believed to be accurate and reliable However Broadcom Corporation does not assume any liability arising out of the application or use of this information nor the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others BCM1250 BCM1125 BCM112...

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