Commissioning
EL5101, EL5101-0010, EL5101-0011
133
Version: 4.2
Note
Frequency and period measurement
From the explanatory notes above it is apparent that the frequency measurement can mea-
sure the current axis status (velocity) significantly more accurately than the period mea-
surement. Frequency measurement is therefore preferable, if possible.
Latch
Activation of latch C input (“C”) and saving (“latching”) of the counter value (index
0x70n0:01
[
}
143]
)
• The counter value is saved at the first external latch pulse (positive edge at input “C”) after the bit has
been set (“TRUE”) in index
0x70n0:01 [
}
143]
(has priority before
0x70n0:02 [
}
143]
/
0x70n0:04
[
}
143]
). The subsequent pulses at the other inputs have no influence on the latch value in index
0x60n0:12 [
}
142]
if the bit is set.
• Note for “Latch C valid” bit: A new counter value at the latch input can only be written once the value of
the “Latch C valid” bit (index
0x60n0:01 [
}
142]
) is “FALSE”.
Activation of the external latch input (“gate/latch”) and latching of the counter value (index
0x70n0:02 [
}
143]
,
0x70n0:04 [
}
143]
)
• The counter value at the latch input (Index
0x70n0:02 [
}
143]
) will be saved upon the first external latch
pulse with a rising edge if the bit (“TRUE”) is set in index
0x60n0:12 [
}
142]
. The subsequent pulses
have no influence on the latch value in index
0x60n0:12 [
}
142]
.
• The counter value at the latch input (Index
0x60n0:12 [
}
142]
) will be saved upon the first external latch
pulse with a falling edge if the bit (“TRUE”) is set in index
0x70n0:04 [
}
143]
. The subsequent pulses
have no influence on the latch value in index
0x60n0:12 [
}
142]
.
• Note for "Latch extern valid" bit: A new counter value at the latch input can only be written once the
value of the “Latch extern valid” bit (index
0x60n0:02 [
}
142]
) is “FALSE”.
Reset
• Counter reset (index
0x80n0:01 [
}
139]
,
0x80n0:02 [
}
139]
,
0x80n0:10 [
}
139]
): For a counter reset via
input C set the bit in index
0x80n0:01 [
}
139]
, for a reset via the external latch input set the bit in index
0x80n0:02 [
}
139]
.
• The functions “Enable C reset” (
0x80n0:01 [
}
139]
) and “Enable extern reset” (
0x80n0:02 [
}
139]
)
cannot be activated simultaneously.
• Note for “Extern reset polarity”, index
0x80n0:10 [
}
139]
: The edge for setting the counter to zero can
be selected via index
0x80n0:10 [
}
139]
.
Bit not set: counter is set to zero with falling edge.
Bit set: counter is set to zero with rising edge.
Up/down counter (only EL5101-0000)
• The mode (encoder or up/down counter) is set via the CoE objects (profile-specific objects, tab CoE -
Online, index
0x80n0:03 [
}
139]
“Non-volatile settings”). Click on the corresponding row of the index to
be parameterized, enter 1 in the SetValue dialog and confirm with OK.
• Set the gate polarity accordingly via object
0x80n0:04 [
}
139]
.
• An additional option for reversing the rotation direction is available by setting the bit in index
0x80n0:0E
[
}
139]
.
Overflow/underflow (only EL5101-0000)
• Overflow/underflow control is inactive in combination with an activated reset function (C/external).
• The
underflow
bit (
0x60n0:04 [
}
142]
) is set if an underflow ...00 →...FF occurs. It is reset if 2/3 of the
counter range are underrun.
Summary of Contents for EL5101
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