Altera Cyclone IV, Device Handbook

Page: 305 / 490

Chapter 1: Cyclone IV Transceivers Architecture 1–25
Receiver Channel Datapath
February 2015 Altera Corporation Cyclone IV Device Handbook,
Volume 2
The byte ordering block operates in either word-alignment-based byte ordering or
user-controlled byte ordering modes.
In word-alignment-based byte ordering mode, the byte ordering block starts looking
for the byte ordering pattern in the byte-deserialized data and restores the order if
necessary when it detects a rising edge on the
rx_syncstatus
signal. Whenever the
byte ordering pattern is found, the
rx_byteorderalignstatus
signal is asserted
regardless if the pad byte insertion is necessary. If the byte ordering block detects
another rising edge on the
rx_syncstatus
signal from the word aligner, it deasserts
the
rx_byteorderalignstatus
signal and repeats the byte ordering operation.
In user-controlled byte ordering mode, the byte ordering operation is user-triggered
using
rx_enabyteord
port. A rising edge on
rx_enabyteord
port triggers the byte
ordering block to start looking for the byte ordering pattern in the byte-deserialized
data and restores the order if necessary. When the byte ordering pattern is found, the
rx_byteorderalignstatus
signal is asserted regardless if a pad byte insertion is
necessary.
RX Phase Compensation FIFO
The RX phase compensation FIFO compensates for the phase difference between the
parallel receiver clock and the FPGA fabric interface clock, when interfacing the
receiver channel to the FPGA fabric (directly or through the PIPE and PCIe hard IP
blocks). The FIFO is four words deep, with latency between two to three parallel clock
cycles.
Figure 1–24 shows the RX phase compensation FIFO block diagram.
1
The FIFO can operate in registered mode, contributing to only one parallel clock cycle
of latency in the Deterministic Latency functional mode. For more information, refer
to
“Deterministic Latency Mode” on page 1–73 . For more information about FIFO
clocking, refer to “FPGA Fabric-Transceiver Interface Clocking” on page 1–43 .
Miscellaneous Receiver PCS Feature
The receiver PCS supports the following additional feature:
■ Output bit-flip—reverses the bit order at a byte level at the output of the receiver
phase compensation FIFO. For example, if the 16-bit parallel receiver data at the
output of the receiver phase compensation FIFO is '10111100 10101101'
(16'hBCAD), enabling this option reverses the data on
rx_dataout
port to
'00111101 10110101' (16'h3DB5).
Figure 1–24. RX Phase Compensation FIFO Block Diagram
Note to Figure 1–24 :
(1) Parameter x refers to the transceiver channel width, where 8, 10, 16, or 20 bits are supported.
RX Phase
Compensation
FIFO
rx_datao u t[x..0] (1)
rx_phase_comp_fifo_error
w r_clk rd_clk