Altera Cyclone IV, Device Handbook

Page: 82 / 490

5–20 Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Cyclone IV PLL Hardware Overview
Cyclone IV Device Handbook, October 2012 Altera Corporation
Volume 1
Cyclone IV PLL Hardware Overview
This section gives a hardware overview of the Cyclone IV PLL.
Figure 5–9 shows a simplified block diagram of the major components of the PLL of
Cyclone IV GX devices.
Loss of lock detection
v
Notes to Table 5–6 :
(1) C counters range from 1 through 512 if the output clock uses a 50% duty cycle. For any output clocks using a
non-50% duty cycle, the post-scale counters range from 1 through 256.
(2) Only applicable if the input clock jitter is in the input jitter tolerance specifications.
(3) The smallest phase shift is determined by the VCO period divided by eight. For degree increments, Cyclone IV E
devices can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible
depending on the frequency and divide parameters.
Table 5–6. Cyclone IV E PLL Features (Part 2 of 2)
Hardware Features Availability
Figure 5–9. Cyclone IV GX PLL Block Diagram
(1)
Notes to Figure 5–9 :
(1) Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.
(2) There are additional 4 pairs of dedicated differential clock inputs in EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 devices that can only
drive general purpose PLLs and multipurpose PLLs on the left side of the device.
CLK[19..16]
can access
PLL_2
,
PLL_6
,
PLL_7
, and
PLL_8
while
CLK[23..20]
can access
PLL_1
,
PLL_5
,
PLL_6
, and
PLL_7
. For the location of these clock input pins, refer to Figure 5–3 on page 5–13 .
(3) This is the VCO post
-
scale counter K.
(4) This input port is fed by a pin
-
driven dedicated GCLK, or through a clock control block if the clock control block is fed by an output from another
PLL or a pin
-
driven dedicated GCLK. An internally generated global signal cannot drive the PLL.
(5) For the general purpose PLL and multipurpose PLL counter outputs connectivity to the GCLKs, refer to Table 5–1 on page 5–2 and Table 5–2 on
page 5–4 .
(6) Only the CI output counter can drive the TX serial clock.
(7) Only the C2 output counter can drive the TX load enable.
(8) Only the C3 output counter can drive the TX parallel clock.
Clock
Switchover
Block
inclk0
inclk1
Clock inp u ts
from pins
GCLK
pfdena
clkswitch
clkbad0
clkbad1
activeclock
FREF for ppm detect
(MPLLs, GPLL1, and GPLL2 only)
PFD
LOCK
circ u it
lock
To RX CDR clocks
(MPLLs only)
÷n
CP LF VCO ÷2
(3)
÷C0
÷C1
÷C2
÷C3
÷C4
÷M
PLL
o u tp u t
m u x
GCLKs (5)
TX serial clock (MPLLs,
GPLL1, and GPLL2 only)
(6)
TX load enable (MPLLs,
GPLL1, and GPLL2 only)
(7)
TX parallel clock (MPLLs ,
GPLL1, and GPLL2only)
( 8 )
External clock o u tp u t
8
8
8
÷ 2, ÷4
4
(2)
GCLK networks
no compensation;
ZDB mode
so u rce-synchrono u s;
normal mode
VCO
Range
Detector
VCOOVRR
VCOUNDR
(4)