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Altera Cyclone IV, Device Handbook

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Altera Cyclone IV Device Handbook Download Page 353

Chapter 1: Cyclone IV Transceivers Architecture

1–73

Transceiver Functional Modes

February 2015

Altera Corporation

Cyclone IV Device Handbook,

Volume 2

Clock Rate Compensation

In XAUI mode, the rate match FIFO compensates up to ±100 ppm (200 ppm total) 
difference between the upstream transmitter and the local receiver reference clock. 
The XAUI protocol requires the transmitter to send /R/ (/K28.0/) code groups 
simultaneously on all four lanes (denoted as ||R|| column) during inter-packet 
gaps, adhering to rules listed in the IEEE P802.3ae specification.

The rate match operation begins after 

rx_syncstatus

 and 

rx_channelaligned

 are 

asserted. The 

rx_syncstatus

 signal is from the word aligner, indicating that 

synchronization is acquired on all four channels, while 

rx_channelaligned

 signal is 

from the deskew FIFO, indicating channel alignment. 

The rate match FIFO looks for the ||R|| column (simultaneous /R/ code groups on 
all four channels) and deletes or inserts ||R|| columns to prevent the rate match 
FIFO from overflowing or under running. The rate match FIFO can insert or delete as 
many ||R|| columns as necessary to perform the rate match operation.

The 

rx_rmfifodatadeleted

 and 

rx_rmfifodatainserted

 flags that indicate rate 

match FIFO deletion and insertion events, respectively, are forwarded to the FPGA 
fabric. If an ||R|| column is deleted, the 

rx_rmfifodeleted

 flag from each of the 

four channels goes high for one clock cycle per deleted ||R|| column. If an ||R|| 
column is inserted, the 

rx_rmfifoinserted

 flag from each of the four channels goes 

high for one clock cycle per inserted ||R|| column.

1

The rate match FIFO does not insert or delete code groups automatically to overcome 
FIFO empty or full conditions. In this case, the rate match FIFO asserts the 

rx_rmfifofull

 and 

rx_rmfifoempty

 flags for at least three recovered clock cycles to 

indicate rate match FIFO full and empty conditions, respectively. You must then assert 
the 

rx_digitalreset

 signal to reset the receiver PCS blocks.

Deterministic Latency Mode

Deterministic Latency mode provides the transceiver configuration that allows no 
latency uncertainty in the datapath and features to strictly control latency variation. 
This mode supports non-bonded (×1) and bonded (×4) channel configurations, and is 
typically used to support CPRI and OBSAI protocols that require accurate delay 
measurements along the datapath. The Cyclone IV GX transceivers configured in 
Deterministic Latency mode provides the following features:

■

registered mode phase compensation FIFO

■

receive bit-slip indication

■

transmit bit-slip control

■

PLL PFD feedback

Summary of Contents for Cyclone IV

Page 1: ...101 Innovation Drive San Jose CA 95134 www altera com CYIV 5V1 2 2 Volume 1 Cyclone IV Device Handbook Cyclone IV Device Handbook Volume 1...

Page 2: ...conductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes...

Page 3: ...ansceivers Cyclone IV GX Devices Only 1 10 Hard IP for PCI Express Cyclone IV GX Devices Only 1 11 Reference and Ordering Information 1 12 Document Revision History 1 13 Chapter 2 Logic Elements and L...

Page 4: ...e 4 2 Input Registers 4 3 Multiplier Stage 4 3 Output Registers 4 4 Operational Modes 4 4 18 Bit Multipliers 4 5 9 Bit Multipliers 4 6 Document Revision History 4 7 Chapter 5 Clock Networks and PLLs i...

Page 5: ...Diode 6 6 OCT Support 6 6 On Chip Series Termination with Calibration 6 8 On Chip Series Termination Without Calibration 6 10 I O Standards 6 11 Termination Scheme for I O Standards 6 13 Voltage Refer...

Page 6: ...ry 7 16 Section III System Integration Chapter 8 Configuration and Remote System Upgrades in Cyclone IV Devices Configuration 8 1 Configuration Features 8 2 Configuration Data Decompression 8 2 Config...

Page 7: ...ce Configuration Pins 8 62 Remote System Upgrade 8 69 Functional Description 8 69 Enabling Remote Update 8 70 Configuration Image Types 8 70 Remote System Upgrade Mode 8 71 Remote Update Mode 8 71 Ded...

Page 8: ...Requirements for Cyclone IV Devices External Power Supply Requirements 11 1 Hot Socketing Specifications 11 2 Devices Driven Before Power Up 11 2 I O Pins Remain Tri stated During Power Up 11 2 Hot so...

Page 9: ...ultipliers in Cyclone IV Devices Revised February 2010 Part Number CYIV 51004 1 1 Chapter 5 Clock Networks and PLLs in Cyclone IV Devices Revised October 2012 Part Number CYIV 51005 2 4 Chapter 6 I O...

Page 10: ...x Chapter Revision Dates Cyclone IV Device Handbook March 2016 Altera Corporation Volume 1...

Page 11: ...o Table 1 You can also contact your local Altera sales office or sales representative Visual Cue Meaning Bold Type with Initial Capital Letters Indicate command names dialog box titles dialog box opti...

Page 12: ...eps indicate a list of items when the sequence of the items is important such as the steps listed in a procedure Bullets indicate a list of items when the sequence of the items is not important 1 The...

Page 13: ...following chapters Chapter 1 Cyclone IV FPGA Device Family Overview Chapter 2 Logic Elements and Logic Array Blocks in Cyclone IV Devices Chapter 3 Memory Blocks in Cyclone IV Devices Chapter 4 Embed...

Page 14: ...I 2 Section I Device Core Cyclone IV Device Handbook March 2016 Altera Corporation Volume 1...

Page 15: ...ra s new Cyclone IV FPGA device family extends the Cyclone FPGA series leadership in providing the market s lowest cost lowest power FPGAs now with a transceiver variant Cyclone IV devices are targete...

Page 16: ...ization and pre emphasis for superior signal integrity 150 mW per channel power consumption Flexible clocking structure to support multiple protocols in a single transceiver block Cyclone IV GX device...

Page 17: ...IV E Device Family Resources EP4CE6 EP4CE10 EP4CE15 EP4CE22 EP4CE30 EP4CE40 EP4CE55 EP4CE75 EP4CE115 Logic elements LEs 6 272 10 320 15 408 22 320 28 848 39 600 55 856 75 408 114 480 Embedded memory K...

Page 18: ...I O 9 72 150 150 290 310 310 475 475 Notes to Table 1 2 1 Applicable for the F169 and F324 packages 2 Applicable for the F484 package 3 Only two multipurpose PLLs for F484 package 4 Two of the genera...

Page 19: ...21 165 53 165 53 165 53 343 137 EP4CE22 79 17 153 52 153 52 EP4CE30 193 68 328 124 532 224 EP4CE40 193 68 328 124 328 124 532 224 EP4CE55 324 132 324 132 374 160 EP4CE75 292 110 292 110 426 178 EP4CE1...

Page 20: ...s User I O LVDS 2 XCVRs User I O LVDS 2 XCVRs EP4CGX15 72 25 2 EP4CGX22 72 25 2 150 64 4 EP4CGX30 72 25 2 150 64 4 290 130 4 EP4CGX50 290 130 4 310 140 8 EP4CGX75 290 130 4 310 140 8 EP4CGX110 270 120...

Page 21: ...or the Cyclone IV E Device Family 1 2 Device E144 M164 M256 U256 F256 F324 U484 F484 F780 EP4CE6 C8L C9L I8L C6 C7 C8 I7 A7 I7N C8L C9L I8L C6 C7 C8 I7 A7 EP4CE10 C8L C9L I8L C6 C7 C8 I7 A7 I7N C8L C9...

Page 22: ...dual port RAM as well as FIFO buffers or ROM They can also be configured to implement any of the data widths in Table 1 7 The multiplier architecture in Cyclone IV devices is the same as in the existi...

Page 23: ...Cyclone IV GX devices support two types of PLLs multipurpose PLLs and general purpose PLLs Use multipurpose PLLs for clocking the transceiver blocks You can also use them for general purpose clocking...

Page 24: ...lel FPP configuration mode for the EP4CGX30F484 and EP4CGX50 75 110 150 devices f For more information refer to the Configuration and Remote System Upgrades in Cyclone IV Devices chapter The cyclical...

Page 25: ...tionality The hard IP for the PCIe PIPE block supports root port and end point configurations This pre verified hard IP block reduces risk design time timing closure and verification You can configure...

Page 26: ...100 C 6 fastest 7 8 N Lead free packaging ES Engineering sample EP4C GX 30 C F 19 C 7 N Member Code FamilyVariant Figure 1 3 Packaging Ordering Information for the Cyclone IV E Device Family Signatur...

Page 27: ...1 6 Updated Table 1 3 and Table 1 4 November 2011 1 5 Updated Cyclone IV Device Family Features section Updated Figure 1 2 and Figure 1 3 December 2010 1 4 Updated for the Quartus II software version...

Page 28: ...1 14 Chapter 1 Cyclone IV FPGA Device Family Overview Document Revision History Cyclone IV Device Handbook March 2016 Altera Corporation Volume 1...

Page 29: ...in the latest version of device specifications before relying on any published information and before placing orders for products or services Cyclone IV Device Handbook Volume 1 November 2009 Feedback...

Page 30: ...put while the register drives another output This feature called register packing improves device utilization because the device can use the register and the LUT for unrelated functions The LAB wide s...

Page 31: ...th parameterized functions such as the library of parameterized modules LPM functions You can also create special purpose functions that specify which LE operating mode to use for optimal performance...

Page 32: ...eates carry chains longer than 16 LEs by automatically linking LABs in the same column For enhanced fitting a long carry chain runs vertically which allows fast horizontal connections to M9K memory bl...

Page 33: ...same LAB Register chain connections transfer the output of one LE register to the adjacent LE register in an LAB The Quartus II Compiler places associated logic in an LAB or adjacent LABs allowing the...

Page 34: ...edicated logic for driving control signals to its LEs The control signals include Two clocks Two clock enables Two asynchronous clears One synchronous clear One synchronous load You can use up to eigh...

Page 35: ...of the register The LE directly supports an asynchronous clear function Each LAB supports up to two asynchronous clear signals labclr1 and labclr2 A LAB wide asynchronous load signal to control the l...

Page 36: ...2 8 Chapter 2 Logic Elements and Logic Array Blocks in Cyclone IV Devices Document Revision History Cyclone IV Device Handbook November 2009 Altera Corporation Volume 1...

Page 37: ...ne IV Device Handbook Volume 1 November 2011 Feedback Subscribe ISO 9001 2008 Registered 3 Memory Blocks in Cyclone IV Devices Cyclone IV devices feature embedded memory structures to address the on c...

Page 38: ...port mode v Simple dual port mode v True dual port mode v Embedded shift register mode 1 v ROM mode v FIFO buffer 1 v Simple dual port mixed width support v True dual port mixed width support 2 v Memo...

Page 39: ...ices M9K memory blocks support byte enables that mask the input data so that only specific bytes of data are written The unwritten bytes retain the previous written value The wren signals along with t...

Page 40: ...locks are multiples of 8 or 9 bits Packed Mode Support Cyclone IV devices M9K memory blocks support packed mode You can implement two single port memory blocks in a single block under the following co...

Page 41: ...t has its own independent address clock enable Figure 3 2 shows an address clock enable block diagram The address register output feeds back to its input using a multiplexer The multiplexer output is...

Page 42: ...ent widths supported per memory mode refer to Memory Modes on page 3 7 Figure 3 3 Cyclone IV Devices Address Clock Enable During Read Cycle Waveform Figure 3 4 Cyclone IV Devices Address Clock Enable...

Page 43: ...memory content Figure 3 5 shows the functional waveform for the asynchronous clear feature 1 You can selectively enable asynchronous clears per logical memory using the Quartus II RAM MegaWizard Plug...

Page 44: ...n or the old data at that address If you perform a write operation with rden deactivated the RAM outputs retain the values they held during the most recent active rden signal To choose the desired beh...

Page 45: ...port widths Table 3 3 lists mixed width configurations Figure 3 7 Cyclone IV Devices Single Port Mode Timing Waveform clk_a wren_a address_a data_a rden_a q_a old data a0 a1 A B C D E F a0 old data a1...

Page 46: ...are For more information about this behavior refer to Read During Write Operations on page 3 15 Figure 3 9 shows the timing waveform for read and write operations in simple dual port mode with unregis...

Page 47: ...the same address can either output New Data at that location or Old Data To choose the desired behavior set the Read During Write option to either New Data or Old Data in the RAM MegaWizard Plug In Ma...

Page 48: ...processing DSP applications such as finite impulse response FIR filters pseudo random number generators multi channel filtering and auto correlation and cross correlation functions These and other DS...

Page 49: ...peration in the single port RAM configuration FIFO Buffer Mode Cyclone IV devices M9K memory blocks support single clock or dual clock FIFO buffers Dual clock FIFO buffers are useful when transferring...

Page 50: ...king mode versus memory mode support matrix Independent Clock Mode Cyclone IV devices M9K memory blocks can implement independent clock mode for true dual port memories In this mode a separate clock i...

Page 51: ...he appropriate read during write behavior in the MegaWizard Plug In Manager Single Clock Mode Cyclone IV devices M9K memory blocks can implement single clock mode for FIFO ROM true dual port simple du...

Page 52: ...written into the memory passes to the output flow through When byteena is low the masked off data is not written into the memory and the old data in the memory appears on the outputs Therefore the out...

Page 53: ...l clocks the relationship between the clocks determines the output behavior of the memory If you use the same clock for the two clocks the output is the old data from the address location However if y...

Page 54: ...utputs the pre initialized values f For more information about mifs refer to the RAM Megafunction User Guide and the Quartus II Handbook Power Management The M9K memory block clock enables of Cyclone...

Page 55: ...ation of on chip resources and external interfaces that help increase performance reduce system cost and lower the power consumption of digital signal processing DSP systems Cyclone IV devices either...

Page 56: ...For more information about M9K memory blocks refer to the Memory Blocks in Cyclone IV Devices chapter f For more information about soft multipliers refer to AN 306 Implementing Multipliers in FPGA Dev...

Page 57: ...in a single embedded multiplier are fed by the same clock clock enable and asynchronous clear signals Multiplier Stage The multiplier stage of an embedded multiplier block supports 9 9 or 18 18 multip...

Page 58: ...multiplier to perform unsigned multiplication by default Output Registers You can register the embedded multiplier output with output registers in either 18 or 36 bit sections depending on the operat...

Page 59: ...lier configured to support an 18 bit multiplier All 18 bit multiplier inputs and results are independently sent through registers The multiplier inputs can accept signed integers unsigned integers or...

Page 60: ...inputs can accept signed integers unsigned integers or a combination of both Two 9 9 multipliers in the same embedded multiplier block share the same signa and signb signal Therefore all the Data A i...

Page 61: ...Cyclone IV Device Handbook Volume 1 Document Revision History Table 4 3 lists the revision history for this chapter Table 4 3 Document Revision History Date Version Changes February 2010 1 1 Added Cyc...

Page 62: ...4 8 Chapter 4 Embedded Multipliers in Cyclone IV Devices Document Revision History Cyclone IV Device Handbook February 2010 Altera Corporation Volume 1...

Page 63: ...device family It includes details about the ability to reconfigure the PLL counter clock frequency and phase shift in real time allowing you to sweep PLL output frequencies and dynamically adjust the...

Page 64: ...rated GCLKs and asynchronous clears clock enables or other control signals with high fan out Table 5 1 Table 5 2 on page 5 4 and Table 5 3 on page 5 7 list the connectivity of the clock sources to the...

Page 65: ...v DPCLK8 v DPCLK9 4 v DPCLK10 v DPCLK11 4 v DPCLK12 4 v DPCLK13 v Notes to Table 5 1 1 EP4CGX30 information in this table refers to all EP4CGX30 packages except F484 package 2 PLL_1 and PLL_2 are mult...

Page 66: ...0 21 22 23 24 25 26 27 28 29 CLKIO4 DIFFCLK_2n v v v CLKIO5 DIFFCLK_2p v v v CLKIO6 DIFFCLK_3n v v v CLKIO7 DIFFCLK_3p v v v CLKIO8 DIFFCLK_5n v v v CLKIO9 DIFFCLK_5p v v v CLKIO10 DIFFCLK_4n RE FCLK3...

Page 67: ...v PLL_4_C2 v v v v PLL_4_C3 v v v v PLL_4_C4 v v v v v v PLL_5_C0 v v PLL_5_C1 PLL_5_C2 PLL_5_C3 v v PLL_5_C4 v v v PLL_6_C0 v v v PLL_6_C1 PLL_6_C2 PLL_6_C3 PLL_6_C4 v v PLL_7_C0 3 v v v PLL_7_C1 3...

Page 68: ...3 v v v DPCLK0 v DPCLK1 v DPCLK2 v DPCLK3 v DPCLK4 v DPCLK5 v DPCLK6 v DPCLK7 v DPCLK8 v DPCLK9 v DPCLK10 v DPCLK11 v DPCLK12 v DPCLK13 v DPCLK14 v DPCLK15 v DPCLK16 v Table 5 2 GCLK Network Connecti...

Page 69: ...GCLK Network Connections for EP4CGX30 EP4CGX50 EP4CGX75 EP4CGX110 and EP4CGX150 Devices 1 2 Part 4 of 4 GCLK Network Clock Sources GCLK Networks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21...

Page 70: ..._C4 3 v v PLL_2_C0 3 v v PLL_2_C1 3 v v PLL_2_C2 3 v v PLL_2_C3 3 v v PLL_2_C4 3 v v PLL_3_C0 v v PLL_3_C1 v v PLL_3_C2 v v PLL_3_C3 v v PLL_3_C4 v v PLL_4_C0 v v PLL_4_C1 v v PLL_4_C2 v v PLL_4_C3 v...

Page 71: ...PCLK3 v v Notes to Table 5 3 1 EP4CE6 and EP4CE10 devices only have GCLK networks 0 to 9 2 These pins apply to all Cyclone IV E devices except EP4CE6 and EP4CE10 devices 3 EP4CE6 and EP4CE10 devices o...

Page 72: ...blocks on each side of the device periphery depending on device density providing up to 30 clock control blocks in each Cyclone IV GX device The maximum number of clock control blocks per Cyclone IV...

Page 73: ...exer is the input clock fIN for the PLL 2 The clkselect 1 0 signals are fed by internal logic and are used to dynamically select the clock source for the GCLK when the device is in user mode 3 The sta...

Page 74: ...84 package 2 PLL_1 and PLL_2 are multipurpose PLLs while PLL_3 and PLL_4 are general purpose PLLs 3 There are five clock control blocks on each side 4 PLL_4 is only available in EP4CGX22 and EP4CGX30...

Page 75: ...side of the device 4 REFCLK 0 1 p n and REFCLK 4 5 p n can only drive the general purpose PLLs and multipurpose PLLs on the left side of the device These clock pins do not have access to the clock co...

Page 76: ...ure 5 4 1 There are five clock control blocks on each side 2 Only one of the corner CDPCLK pins in each corner can feed the clock control block at a time You can use the other CDPCLK pins as general p...

Page 77: ...PCLK pins from both the left and right sides and four DPCLK pins from both the top and bottom Five signals from internal logic From the clock sources listed above only two clock input pins two PLL clo...

Page 78: ...directly on the clock network as shown in Figure 5 1 on page 5 11 You can set the input clock sources and the clkena signals for the GCLK multiplexers through the Quartus II software using the ALTCLK...

Page 79: ...e clock outputs if the system is not tolerant to frequency overshoot during PLL resynchronization Altera recommends using the clkena signals when switching the clock source to the PLLs or the GCLK The...

Page 80: ...thesis for device clock management external system clock management and high speed I O interfaces f For more information about the number of general purpose PLLs and multipurpose PLLs in each device d...

Page 81: ...es and cannot access the GCLK networks CLK 17 19 20 21 p can be used as single ended clock input pins 8 Only applicable if the input clock jitter is in the input jitter tolerance specifications 9 The...

Page 82: ...CGX50 EP4CGX75 EP4CGX110 and EP4CGX150 devices that can only drive general purpose PLLs and multipurpose PLLs on the left side of the device CLK 19 16 can access PLL_2 PLL_6 PLL_7 and PLL_8 while CLK...

Page 83: ...tial clock output Only the C0 output counter can feed the dedicated external clock outputs as shown in Figure 5 11 without going through the GCLK Other output counters can feed other I O pins through...

Page 84: ...lock input and output pins refer to the Cyclone IV Device I O Features chapter Cyclone IV PLLs can drive out to any regular I O pin through the GCLK You can also use the external clock output pins as...

Page 85: ...e input pins the phase relationship between the data and clock remains the same at the data and clock ports of any I O element input register Figure 5 12 shows an example waveform of the data and cloc...

Page 86: ...f the PLL clock in this mode Normal Mode An internal clock in normal mode is phase aligned to the input clock pin The external clock output pin has a phase delay relative to the clock input pin if con...

Page 87: ...e input clock and output clocks to guarantee clock alignment at the input and output pins Figure 5 15 shows an example waveform of the phase relationship of the PLL clocks in ZDB mode Figure 5 14 Phas...

Page 88: ...h frequency VCO For multiple PLL outputs with different frequencies the VCO value is the least common multiple of the output frequencies that meets its frequency specifications For example if output f...

Page 89: ...y cycle allows PLLs to generate clock outputs with a variable duty cycle This feature is supported on the PLL post scale counters You can achieve the duty cycle setting by a low and high time count se...

Page 90: ...s the block diagram of the switchover circuit built into the PLL There are two ways to use the clock switchover feature Use the switchover circuitry for switching from inclk0 to inclk1 running at the...

Page 91: ...ng the automatic switchover you must switch input clocks with the manual override feature with the clkswitch input Figure 5 19 shows an example of a waveform illustrating the switchover feature when c...

Page 92: ...anual switchover in which the clkswitch signal controls whether inclk0 or inclk1 is the input clock to the PLL The characteristics of a manual switchover are similar to the manual override feature in...

Page 93: ...od for the PLL to lock onto a new clock The exact amount of time it takes for the PLL to re lock is dependent on the PLL configuration If the phase relationship between the input clock to the PLL and...

Page 94: ...e output clocks from the PLLs of Cyclone IV devices in one of two ways Fine resolution using VCO phase taps Coarse resolution using counter starting time Fine resolution phase shifts are implemented b...

Page 95: ...set to three This creates a delay of two coarse two complete VCO periods You can use the coarse and fine phase shifts to implement clock delays in Cyclone IV devices Cyclone IV devices support dynamic...

Page 96: ...requencies It is also useful in prototyping environments allowing you to sweep PLL output frequencies and adjust the output clock phase dynamically For instance a system generating test patterns is re...

Page 97: ...eps 1 The scanclkena signal is asserted at least one scanclk cycle prior to shifting in the first bit of scandata D0 2 Serial data scandata is shifted into the scan chain on the second rising edge of...

Page 98: ...ses the counter resulting in a divide by one When this bit is set to 0 the PLL computes the effective division of the VCO output frequency based on the high and low time counters For example if the po...

Page 99: ...he scan chain order of the PLL components Table 5 7 Cyclone IV PLL Reprogramming Bits Block Name Number of Bits Counter Other Total C4 1 16 2 2 18 C3 16 2 2 18 C2 16 2 2 18 C1 16 2 2 18 C0 16 2 2 18 M...

Page 100: ...ist the possible settings for charge pump current ICP loop filter resistor R and capacitor C values for PLLs of Cyclone IV devices Figure 5 25 Scan Chain Bit Order DATAIN rbypass HB 7 HB 6 HB 5 HB 4 H...

Page 101: ...ted by 1 8 the VCO frequency at a time The output clocks are active during this phase reconfiguration process Table 5 12 lists the control signals that are used for dynamic phase shifting Table 5 10 L...

Page 102: ...here the VCO frequency is set to 1 000 MHz and the output clock frequency is set to 100 MHz performing 40 dynamic phase shifts each one yields 125 ps phase shift results in shifting the output clock b...

Page 103: ...ONE signal goes from low to high Each PHASESTEP pulse enables one phase shift PHASESTEP pulses must be at least one SCANCLK cycle apart f For information about the ALTPLL_RECONFIG MegaWizard Plug In M...

Page 104: ...2010 2 2 Updated for the Quartus II software version 10 1 release Updated Figure 5 3 and Figure 5 10 Updated GCLK Network Clock Source Generation PLLs in Cyclone IV Devices and Manual Override sectio...

Page 105: ...al and external memory interfaces This section includes the following chapters Chapter 6 I O Features in Cyclone IV Devices Chapter 7 External Memory Interfaces in Cyclone IV Devices Revision History...

Page 106: ...II 2 Section II I O Interfaces Cyclone IV Device Handbook March 2016 Altera Corporation Volume 1...

Page 107: ...e I O capabilities of Cyclone IV devices are driven by the diversification of I O standards in many low cost applications and the significant increase in required I O performance Altera s objective is...

Page 108: ...nts Cyclone IV I O elements IOEs contain a bidirectional I O buffer and five registers for registering input output output enable signals and complete embedded bidirectional single data rate transfer...

Page 109: ...he LVTTL LVCMOS SSTL 2 Class I and II SSTL 18 Class I and II HSTL 18 Class I and II HSTL 15 Class I and II and HSTL 12 Class I and II I O standards have several levels of current strength that you can...

Page 110: ...with calibration 1 You cannot use the programmable slew rate feature when using the 3 0 V PCI 3 0 V PCI X 3 3 V LVTTL or 3 3 V LVCMOS I O standards Only the fast slew rate default setting is available...

Page 111: ...pin drives a register through combinational logic may not require the delay Programmable delays minimize setup time The Quartus II Compiler can program these delays to automatically minimize setup tim...

Page 112: ...V devices provide an optional PCI clamp diode enabled input and output for each I O pin Dual purpose configuration pins support the diode in user mode if the specific pins are not used as configuratio...

Page 113: ...OS 4 8 12 16 4 8 12 16 50 25 50 25 50 25 50 25 0 1 2 v 1 8 V LVTTL LVCMOS 2 4 6 8 10 12 1 6 2 4 6 8 10 12 1 6 50 25 50 25 50 25 50 25 1 5 V LVCMOS 2 4 6 8 10 12 1 6 2 4 6 8 10 12 1 6 50 25 50 25 50 25...

Page 114: ...TL 2 differential HSTL 18 HSTL 15 and HSTL 12 I O standards are supported only on clock input pins and PLL output clock pins 3 True differential PPDS LVDS mini LVDS and RSDS I O standards outputs are...

Page 115: ...bank in which the calibration block resides can enable OCT calibration Figure 6 10 on page 6 18 shows the top level view of the OCT calibration blocks placement Each calibration block comes with a pai...

Page 116: ...not use the calibration circuit On Chip Series Termination Without Calibration Cyclone IV devices support driver impedance matching to match the impedance of the transmission line which is typically...

Page 117: ...bject to a certain degree of variation depending on the process voltage and temperature f For more information about tolerance specification refer to the Cyclone IV Device Datasheet chapter I O Standa...

Page 118: ...d JESD8 16A 1 2 1 2 v v v v v HSTL 12 Class II 9 voltage referenced JESD8 16A 1 2 1 2 v v v PCI and PCI X Single ended 3 0 3 0 v v v v v Differential SSTL 2 Class I or Class II Differential 5 JESD8 9A...

Page 119: ...ultiVolt I O interface feature that allows Cyclone IV devices in all packages to interface with I O systems that have different supply voltages 4 Cyclone IV GX devices do not support 1 2 V VCCIO in ba...

Page 120: ...ass II External On Board Termination OCT with and without Calibration VTT 50 50 VTT 50 VTT 50 Transmitter Transmitter Receiver Receiver VTT 50 Transmitter Receiver VTT 50 VTT 50 Transmitter Receiver C...

Page 121: ...ansmitter Receiver VTT VTT Transmitter Receiver VTT VTT Cyclone IV Device Family Series OCT 50 Differential HSTL Class I Termination Differential HSTL Class II Transmitter Receiver 50 50 50 50 VTTVTT...

Page 122: ...on page 6 18 and Figure 6 11 on page 6 19 The Cyclone IV GX configuration I O bank contains three user I O pins that can be used as normal user I O pins if they are not used in configuration modes Eac...

Page 123: ...orted only on clock input pins and phase locked loops PLLs output clock pins Differential SSTL 18 differential HSTL 18 and HSTL 15 I O standards do not support Class II output 6 The differential HSTL...

Page 124: ...VDS input buffer 8 The PCI X I O standard does not meet the IV curve requirement at the linear region 9 The OCT block is located in the shaded banks 4 5 and 7 10 There are two dedicated clock input I...

Page 125: ...banks 4 7 and 8 7 BLVDS output uses two single ended outputs with the second output programmed as inverted BLVDS input uses the LVDS input buffer 8 The PCI X I O standard does not meet the IV curve r...

Page 126: ...n the timing if the pins are used as inputs and outputs f For more information about VREF pin capacitance refer to the pin capacitance section in the Cyclone IV Device Datasheet chapter f For informat...

Page 127: ...40 EP4CE55 EP4CE75 EP4CE115 I O Bank 1 144 EQPF 256 UBGA 256 FBGA 144 EQPF 256 UBGA 256 FBGA 144 EQPF 164 MBGA 256 MBGA 256 UBGA 256 FBGA 484 FBGA 144 EQPF 256 UBGA 256 FBGA 324 FBGA 484 FBGA 780 FBGA...

Page 128: ...abled by default in the Quartus II software for input signals with bank VCCIO at 2 5 3 0 or 3 3 V High Speed Differential Interfaces Cyclone IV devices can send and receive data through LVDS signals F...

Page 129: ...the I O Management chapter in volume 2 of the Quartus II Handbook DC Guidelines For the Quartus II software to automatically check for illegally placed pads according to the DC guidelines set the DC c...

Page 130: ...ependent power supply True output drivers for LVDS RSDS mini LVDS and PPDS are on the right I O banks On the Cyclone IV E row I O banks and the Cyclone IV GX right I O banks some of the differential p...

Page 131: ...v All Three Resistors PPDS 1 2 5 6 Not Required v All Three Resistors BLVDS 1 All Single Resistor v v LVPECL 2 All v Differential SSTL 2 3 All v v Differential SSTL 18 3 All v v Differential HSTL 18 3...

Page 132: ...k Location External Resistor Network at Transmitter Transmitter TX Receiver RX LVDS 5 6 Not Required v v 3 4 5 6 7 8 Three Resistors RSDS 5 6 Not Required v 3 4 7 8 Three Resistors 3 4 5 6 7 8 Single...

Page 133: ...ks 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 LVDS 4 6 8 23 23 8 23 23 6 8 21 21 21 67 7 20 20 30 60 112 30 60 60 112 62 62 70 54 54 79 50 103 Emulated LVDS 5 6 13 43 43 13 43 43 12 1...

Page 134: ...FBGA 169 FBGA 324 FBGA 484 FBGA 484 FBGA 672 FBGA 484 FBGA 672 FBGA 484 FBGA 672 FBGA 896 FBGA 484 FBGA 672 FBGA 896 FBGA User I O 3 72 72 150 72 150 290 290 310 290 310 270 393 475 270 393 475 User I...

Page 135: ...44 specification supports an input voltage range of 0 V to 2 4 V f For LVDS I O standard electrical specifications in Cyclone IV devices refer to the Cyclone IV Device Datasheet chapter Table 6 10 Cyc...

Page 136: ...S interface with Cyclone IV devices LVDS using two single ended output buffers and external resistors BLVDS I O Standard Support in Cyclone IV Devices The BLVDS I O standard is a high speed differenti...

Page 137: ...ncreasing the load decreases the bus differential impedance With termination at both ends of the bus termination is not required between the two signals at the input buffer A single series resistor RS...

Page 138: ...on from the National Semiconductor website www national com Designing with RSDS Mini LVDS and PPDS Cyclone IV I O banks support RSDS mini LVDS and PPDS output standards The right I O banks support tru...

Page 139: ...n the resistor network for an RSDS interface as shown in Figure 6 17 The external single resistor solution reduces the external resistor count while still achieving the required signaling level for RS...

Page 140: ...uired when the LVPECL common mode voltage of the output buffer is higher than the Cyclone IV devices LVPECL input common mode voltage Figure 6 18 shows the AC coupled termination scheme The 50 resisto...

Page 141: ...0 V to 1 2 V 0 V to 1 5 V or 0 V to 1 8 V HSTL logic switching range Cyclone IV devices support differential HSTL 18 HSTL 15 and HSTL 12 I O standards The differential HSTL input standard is availabl...

Page 142: ...evices Timing for source synchronous signaling is based on skew between the data and clock signals High speed differential data transmission requires timing parameters provided by IC vendors and requi...

Page 143: ...ent and DC Guidelines on page 6 23 Input jitter tolerance peak to peak Allowed input jitter on the input clock to the PLL that is tolerable while maintaining PLL lock Output jitter peak to peak Peak t...

Page 144: ...ors as close to receiver input pins as possible Use surface mount components Avoid 90 corners on board traces Use high performance connectors Design backplane and card traces so that trace impedance m...

Page 145: ...Part 1 of 2 Date Version Changes March 2016 2 7 Updated Table 6 5 and Table 6 9 to remove support for the N148 package May 2013 2 6 Updated Table 6 2 by adding Note 9 Updated Table 6 4 and Table 6 8 t...

Page 146: ...0 Added Cyclone IV E devices information for the Quartus II software version 9 1 SP1 release Updated Table 6 2 Table 6 3 and Table 6 10 Updated I O Banks section Added Figure 6 9 Updated Figure 6 10 a...

Page 147: ...Memory Interfaces in Cyclone IV Devices This chapter describes the memory interface pin support and the external memory interface features of Cyclone IV devices In addition to an abundant supply of o...

Page 148: ...data pins for external memory interfaces are called D for write data Q for read data or DQ for shared read and write data pins The read data strobes or read clocks are called DQS pins Cyclone IV devi...

Page 149: ...on the global clock resources in Cyclone IV devices through the ALTMEMPHY megafunction because you are not required to route the DQS signals on the global clock buses because DQS is ignored for read c...

Page 150: ...1 1 Top 2 2 1 1 Bottom 2 2 1 1 484 pin FBGA 3 Right 4 2 2 2 1 1 Top 4 2 2 2 1 1 Bottom 4 2 2 2 1 1 EP4CGX50 EP4CGX75 484 pin FBGA Right 4 2 2 2 1 1 Top 4 2 2 2 1 1 Bottom 4 2 2 2 1 1 672 pin FBGA Rig...

Page 151: ...s EP4CE6 EP4CE10 144 pin EQFP Left 0 0 0 0 Right 0 0 0 0 Bottom 1 3 1 0 0 0 Top 1 4 1 0 0 0 256 pin UBGA Left 1 1 1 0 0 Right 2 1 1 0 0 Bottom 2 2 1 1 Top 2 2 1 1 256 pin FBGA Left 1 1 1 0 0 Right 2 1...

Page 152: ...2 2 1 1 EP4CE30 324 pin FBGA Left 1 2 2 1 1 0 0 Right 2 2 2 1 1 0 0 Bottom 2 2 1 1 0 0 Top 2 2 1 1 0 0 EP4CE30 EP4CE115 484 pin FBGA Left 4 4 2 2 1 1 Right 4 4 2 2 1 1 Bottom 4 4 2 2 1 1 Top 4 4 2 2 1...

Page 153: ...II SRAM 9 Q read data group DQ3T 8 0 pins are associated with DQS0T CQ0T and DQS1T CQ0T pins same 0T group index The Quartus II software issues an error message if a DQ group is not placed properly wi...

Page 154: ...Figure 7 2 1 The DQS CQ or CQ pin locations in this diagram apply to all packages in Cyclone IV GX devices except devices in 169 pin FBGA and 324 pin FBGA I O Bank 8B I O Bank 3B I O Bank 3 I O Bank...

Page 155: ...or CQ Pins for Cyclone IV GX Devices in the 324 Pin FBGA Package Figure 7 4 DQS CQ or CQ Pins for Cyclone IV GX Devices in the 169 Pin FBGA Package I O Bank 9 I O Bank 3 I O Bank 3A I O Bank 4 I O Ba...

Page 156: ...Q Pins in Cyclone IV E I O Banks 1 Note to Figure 7 5 1 The DQS CQ or CQ pin locations in this diagram apply to all packages in Cyclone IV E devices except devices in 144 pin EQFP I O Bank 8 I O Bank...

Page 157: ...tional Parity DM and Error Correction Coding Pins Cyclone IV devices support parity in 9 18 and 36 modes One parity bit is available per eight bits of data pins You can use any of the DQ pins for pari...

Page 158: ...port QDR II SRAM in the burst length of two Memory Clock Pins In DDR2 and DDR SDRAM memory interfaces the memory clock signals CK and CK are used to capture the address signals and the control or comm...

Page 159: ...g edge of the clock Register CI aligns the data before it is synchronized with the system clock The data from the DDR input register is fed to two registers sync_reg_h and sync_reg_l then the data is...

Page 160: ...tured on the rising edge of the clock The registered outputs are multiplexed by the common clock to drive the DDR output pin at twice the data rate The DDR output enable path has a similar structure t...

Page 161: ...by 90 from the system clock and generates the DQ signals during writes You can use the PLL reconfiguration feature to calibrate the read capture phase shift to balance the setup and hold margins 1 Th...

Page 162: ...support for the N148 package Updated Figure 7 4 to remove support for the N148 package May 2013 2 5 Updated Table 7 2 to add new device options and packages February 2013 2 4 Updated Table 7 2 to add...

Page 163: ...in Cyclone IV Devices Chapter 9 SEU Mitigation in Cyclone IV Devices Chapter 10 JTAG Boundary Scan Testing for Cyclone IV Devices Chapter 11 Power Requirements for Cyclone IV Devices Revision History...

Page 164: ...III 2 Section III System Integration Cyclone IV Device Handbook March 2016 Altera Corporation Volume 1...

Page 165: ...devices use SRAM cells to store configuration data You must download the configuration data to Cyclone IV devices each time the device powers up because SRAM memory is volatile Cyclone IV devices are...

Page 166: ...on file is less than the time required to send the configuration data to the device There are two methods for enabling compression for the Cyclone IV device bitstreams in the Quartus II software Befor...

Page 167: ...the pof you added to SOF Data and click Properties 7 In the SOF File Properties dialog box turn on the Compression option When multiple Cyclone IV devices are cascaded you can selectively enable the...

Page 168: ...has stricter power up requirements when compared with the standard POR time option You can select either the fast option or the standard POR option with the MSEL pin settings 1 If your system exceeds...

Page 169: ...0 and 3 3 V configuration voltage standards by following specific requirements All I O inputs must maintain a maximum AC voltage of 4 1 V When using a serial configuration device in an AS configuratio...

Page 170: ...emes only 1 To tri state the configuration bus for AS and AP configuration schemes you must tie nCE high and nCONFIG low The user I O pins and dual purpose I O pins have weak pull up resistors which a...

Page 171: ...the CLKUSR pin as a user I O pin You also have the flexibility to synchronize initialization of multiple devices or to delay initialization with the CLKUSR option The CLKUSR pin allows you to control...

Page 172: ...0 0 0 Standard 3 3 3 0 2 5 JTAG based configuration 2 3 3 3 Notes to Table 8 3 1 Configuration voltage standard applied to the VCCIO supply of the bank in which the configuration pins reside 2 JTAG ba...

Page 173: ...f your device is only using JTAG configuration Table 8 4 Configuration Schemes for Cyclone IV GX Devices EP4CGX30 only for F484 package EP4CGX50 EP4CGX75 EP4CGX110 and EP4CGX150 Part 2 of 2 Configurat...

Page 174: ...s make serial configuration devices the ideal low cost configuration solution f For more information about serial configuration devices refer to the Serial Configuration Devices EPCS1 EPCS4 EPCS16 EPC...

Page 175: ...t clock 40 MHz maximum from the internal oscillator or an external clock from CLKUSR to generate the DCLK There are some variations in the internal oscillator frequency because of the process voltage...

Page 176: ...riving the nCSO output pin low which connects to the nCS pin of the configuration device The Cyclone IV device uses the DCLK and DATA 1 pins to send operation commands and read address signals to the...

Page 177: ...to Table 8 3 on page 8 8 Table 8 4 on page 8 8 and Table 8 5 on page 8 9 Connect the MSEL pins directly to VCCA or GND 5 Connect the series resistor at the near end of the serial configuration device...

Page 178: ...chained together If the configuration bitstream size exceeds the capacity of a serial configuration device you must select a larger configuration device enable the compression feature or both When con...

Page 179: ...gh After completing its configuration cycle the master device drives nCE low and sends the second copy of the configuration data to all three slave devices configuring them simultaneously The advantag...

Page 180: ...imum AC voltage of 4 1 V The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in Configuration and JTAG Pin I O Requirements on page 8 5 7 The 50 series resis...

Page 181: ...for the master device in AS mode and slave devices in PS mode refer to Table 8 3 on page 8 8 Table 8 4 on page 8 8 and Table 8 5 on page 8 9 Connect the MSEL pins directly to VCCA or GND 4 Connect th...

Page 182: ...etween the supported serial configuration device and Cyclone IV device must follow the recommendations listed in Table 8 7 Estimating AS Configuration Time AS configuration time is dominated by the ti...

Page 183: ...amming of a serial configuration device through the AS programming interface you must place the diodes and capacitors as close as possible to the Cyclone IV device You must ensure that the diodes and...

Page 184: ...and capacitors maintain a maximum AC voltage of 4 1 V The external diodes and capacitors are required to prevent damage to the Cyclone IV device AS configuration input pins due to possible overshoot...

Page 185: ...ead a Raw Programming Data rpd file and write to serial configuration devices The serial configuration device programming time using the SRunner software driver is comparable to the programming time w...

Page 186: ...ng data from the flash Additionally the Micron P30 and P33 flash families have identical pin out and adopt similar protocols for data access 1 Cyclone IV E devices use a 40 MHz oscillator for the AP c...

Page 187: ...active low chip enable CE active low output enable OE active low address valid ADV active low write enable WE The supported parallel flash memories output a control signal WAIT to Cyclone IV E devices...

Page 188: ...the Cyclone IV E device in the AP configuration scheme Figure 8 7 Single Device AP Configuration Using Micron P30 and P33 Flash Memory Notes to Figure 8 7 1 Connect the pull up resistors to the VCCIO...

Page 189: ...EO pins The first device in the chain must have its nCE pin connected to GND You must connect its nCEO pin to the nCE pin of the next device in the chain Use an external 10 k pull up resistor to pull...

Page 190: ...unconnected or used as a user I O pin when it does not feed the nCE pin of another device 4 The MSEL pin settings vary for different configuration voltage standards and POR time You must set the maste...

Page 191: ...configuration ignores the WAIT signal during configuration mode However if you are accessing flash during user mode with user logic you can optionally use the normal I O pin to monitor the WAIT signal...

Page 192: ...ltiple Bus Masters Similar to the AS configuration scheme the AP configuration scheme supports multiple bus masters for the parallel flash For another master to take control of the AP configuration bu...

Page 193: ...he Micron P30 or P33 flash 5 When cascading Cyclone IV E devices in a multi device AP configuration connect the repeater buffers between the master device and slave devices for DATA 15 0 and DCLK All...

Page 194: ...z 50 ns In word wide cascade programming the DATA 15 0 bus transfers a 16 bit word and essentially cuts configuration time to approximately 1 16 of the AS configuration time Equation 8 4 and Equation...

Page 195: ...IV E devices to program the parallel flash in system even if the host or download cable cannot access the configuration pins of the parallel flash f For more information about using the JTAG pins on C...

Page 196: ...IV device through DATA 0 at each rising edge of DCLK If your system already contains a common flash interface CFI flash memory you can use it for Cyclone IV device configuration storage as well The MA...

Page 197: ...rget device until CONF_DONE goes high and the device enters initialization state 1 Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device INIT_DONE is...

Page 198: ...Figure 8 14 shows how to configure multiple devices using an external host device This circuit is similar to the PS configuration circuit for a single device except that Cyclone IV devices are cascad...

Page 199: ...ONFIG nSTATUS DCLK DATA 0 and CONF_DONE configuration pins are connected to every device in the chain To ensure signal integrity and prevent clock skew problems configuration signals may require buffe...

Page 200: ...er up the Cyclone IV device holds nSTATUS low during POR delay 3 After power up before and during configuration CONF_DONE is low 4 In user mode drive DCLK either high or low when using the PS configur...

Page 201: ...F_DONE high to CLKUSR enabled 4 maximum DCLK period tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU 3 192 CLKUSR period tDSU Data setup time before rising edge on DCLK 5 8 ns tCH DCLK...

Page 202: ...ad cable is the only configuration scheme used on your board This is to ensure that DATA 0 and DCLK are not left floating after configuration For example if you also use a configuration device the pul...

Page 203: ...vice For this value refer to the MasterBlaster Serial USB Communications Cable User Guide When using the ByteBlasterMV download cable this pin is a no connect When using USB Blaster ByteBlaster II and...

Page 204: ...rol configuration from the flash memory device to the Cyclone IV device f For more information about the PFL refer to AN 386 Using the Parallel Flash Loader with the Quartus II Software 1 FPP configur...

Page 205: ...2 clock cycles to initialize properly and enter user mode For more information about the supported CLKUSR fMAX value for Cyclone IV devices refer to Table 8 13 on page 8 44 The INIT_DONE pin is releas...

Page 206: ...ices are cascaded for multi device configuration After the first device completes configuration in a multi device configuration chain its nCEO pin drives low to activate the nCE pin of the second devi...

Page 207: ...th other Altera devices that support FPP configuration To ensure that all devices in the chain complete configuration at the same time or that an error flagged by one device starts reconfiguration in...

Page 208: ...NF_DONE is low 4 Do not leave DCLK floating after configuration It must be driven high or low whichever is more convenient 5 DATA 7 0 is available as a user I O pin after configuration the state of th...

Page 209: ...CD2UM CONF_DONE high to user mode 5 300 650 s tCD2CU CONF_DONE high to CLKUSR enabled 4 maximum DCLK period tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU 3 192 CLKUSR period tDSU Da...

Page 210: ...14 Dedicated JTAG Pins Pin Name Pin Type Description TDI Test data input Serial input pin for instructions as well as test and programming data Data shifts in on the rising edge of TCK If the JTAG int...

Page 211: ...r high or low whichever is convenient on your board 3 Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver VIO must match the device s VCCA For this value refer to the Ma...

Page 212: ...Single Device Using a Download Cable 1 5 V or 1 8 V VCCIO Powering the JTAG Pins Notes to Figure 8 24 1 Connect these pull up resistors to the VCCIO supply of the bank in which the pin resides 2 Conne...

Page 213: ...or programming operations Toggling these pins do not affect JTAG operations other than the usual boundary scan operation When designing a board for JTAG configuration of Cyclone IV devices consider th...

Page 214: ...to support a non JTAG configuration scheme If you only use a JTAG configuration connect the nCONFIG pin to logic high and the MSEL pins to GND In addition pull DCLK and DATA 0 to either high or low w...

Page 215: ...t device low when it has successfully been JTAG configured You can place other Altera devices that have JTAG support in the same JTAG chain for device programming and configuration Figure 8 26 JTAG Co...

Page 216: ...nner Software Driver The JRunner software driver allows you to configure Cyclone IV devices through the ByteBlaster II or ByteBlasterMV cables in JTAG mode The supported programming input file is in r...

Page 217: ...bedded Solution for PLD JTAG Configuration and the source files on the Altera website at www altera com Combining JTAG and AS Configuration Schemes You can combine the AS configuration scheme with the...

Page 218: ...B Blaster or ByteBlasterMV cable with a 2 5 V VCCA supply Third party programmers must switch to 2 5 V Pin 4 of the header is a VCC power supply for the MasterBlaster cable The MasterBlaster cable can...

Page 219: ...n In a multiple device chain you must only configure the master device that controls the serial configuration device Slave devices in the multiple device chain that are configured by the serial config...

Page 220: ...ter output driver The VIO must match the VCCA of the device For this value refer to the MasterBlaster Serial USB Communications Cable User Guide When using the ByteBlasterMV download cable this pin is...

Page 221: ...for Cyclone IV Devices chapter I O Reconfiguration Use the CONFIG_IO instruction to reconfigure the I O configuration shift register IOCSR chain This instruction allows you to perform board level test...

Page 222: ...IO You can start reconfiguration by either pulling nCONFIG low for at least 500 ns or issuing the PULSE_NCONFIG instruction If the ACTIVE_DISENGAGE instruction was issued and the JTAG_PROGRAM instruct...

Page 223: ...AS or AP configuration scheme the ACTIVE_DISENGAGE instruction puts the active configuration controller into idle state If a successful JTAG programming is executed the active controller is automatic...

Page 224: ...ctions toggle on or off whether or not the active clock is sourced from the CLKUSR pin or the internal configuration oscillator To source the active clock from the CLKUSR pin issue the EN_ACTIVE_CLK i...

Page 225: ..._BOOT_ADDR instruction is for Cyclone IV E devices only and allows you to define a start boot address for the parallel flash memory in the AP configuration scheme This instruction shifts in a start bo...

Page 226: ...t Yes VCCINT All modes 9 TDO Output Yes VCCIO JTAG 6 DEV_OE Input VCCIO Optional 6 DEV_CLRn Input VCCIO Optional Notes to Table 8 18 1 The CRC_ERROR pin is a dedicated open drain output or an optional...

Page 227: ...DCLK 1 2 Input Yes VCCIO PS FPP Output VCCIO AS AP 6 CONF_DONE Bidirectional Yes Pull up All modes 1 TDI Input Yes VCCIO JTAG 1 TMS Input Yes VCCIO JTAG 1 TCK Input Yes VCCIO JTAG 1 nCONFIG Input Yes...

Page 228: ...in is optional and is used when the CRC error detection circuit is enabled in the Quartus II software from the Error Detection CRC tab of the Device and Pin Options dialog box When using this pin conn...

Page 229: ...ust hold the nCE pin low for successful JTAG programming of the device nCEO N A if option is on I O if option is off All Output open drain Output that drives low when configuration is complete In a si...

Page 230: ...clone IV device on the DATA 0 pin In AS mode DATA 0 has an internal pull up resistor that is always active After AS configuration DATA 0 is a dedicated input pin with optional user control After PS or...

Page 231: ...lel flash Connects to the A 24 1 bus on the Micron P30 or P33 flash nRESET I O AP 2 Output Active low reset output Driving the nRESET pin low resets the parallel flash Connects to the RST pin on the M...

Page 232: ...ning of configuration After the option bit to enable INIT_DONE is programmed into the device during the first frame of configuration data the INIT_DONE pin goes low When initialization is complete the...

Page 233: ...hat is used The remote system upgrade process of the Cyclone IV device consists of the following steps 1 A Nios II processor or user logic implemented in the Cyclone IV device logic array receives new...

Page 234: ...vice and Pin Options The Device and Pin Options dialog box appears 3 Click the Configuration tab 4 From the Configuration Mode list select Remote 5 Click OK 6 In the Settings dialog box click OK Confi...

Page 235: ...ever updated or modified using remote access When you use the AP configuration in Cyclone IV E devices the Cyclone IV E device loads the default factory configuration located at the following address...

Page 236: ...is written by the dedicated remote system upgrade circuitry of the Cyclone IV device to specify the cause of the reconfiguration The following actions cause the remote system upgrade status register...

Page 237: ...the remote communication interface assists the Cyclone IV device in determining when a remote system update is arriving When a remote system update arrives the soft logic receives the incoming data w...

Page 238: ...shows the data path of the remote system upgrade block Figure 8 33 Remote System Upgrade Circuit Data Path 1 Notes to Figure 8 33 1 The RU_DOUT RU_SHIFTnLD RU_CAPTnUPDT RU_CLK RU_DIN RU_nCONFIG and RU...

Page 239: ...remote update mode has write access to this register Table 8 22 Remote System Upgrade Registers Register Description Shift register This register is accessible by the logic array and allows the update...

Page 240: ...arly and Osc_int option bits for the application configuration must be turned on by the factory configuration Remote System Upgrade Status Register The remote system upgrade status register specifies...

Page 241: ...mation 1 31 30 Master state machine current state The current state of the remote system upgrade master state machine 29 24 Reserved bits Padding bits that are set to all 0 s 23 0 Boot address The cur...

Page 242: ...FIG goes high the remote system upgrade state machine updates the control register with the contents of the update register and starts system reconfiguration from the new application page 1 To ensure...

Page 243: ...ting after the application configuration enters device user mode This timer must be periodically reloaded or reset by the application configuration before the timer expires by asserting RU_nRSTIMER If...

Page 244: ...uitry ALTREMOTE_UPDATE Megafunction User Guide Document Revision History Table 8 28 lists the revision history for this chapter Table 8 28 Document Revision History Part 1 of 2 Date Version Changes Ma...

Page 245: ...1 Updated for the Quartus II software 9 1 SP1 release Added Overriding the Internal Oscillator and AP Configuration Supported Flash Memories sections Updated JTAG Instructions section Added Table 8 6...

Page 246: ...8 82 Chapter 8 Configuration and Remote System Upgrades in Cyclone IV Devices Document Revision History Cyclone IV Device Handbook May 2013 Altera Corporation Volume 1...

Page 247: ...rors 1 Configuration error detection is supported in all Cyclone IV devices including Cyclone IV GX devices Cyclone IV E devices with 1 0 V core voltage and Cyclone IV E devices with 1 2 V core voltag...

Page 248: ...uitry to detect data corruption by soft errors in the CRAM cells This error detection capability continuously computes the CRC of the configured CRAM bits based on the contents of the device and compa...

Page 249: ...g circuitry in Cyclone IV devices eliminating the need for external logic The CRC is computed by the device during configuration and checked against an automatically computed CRC during normal operati...

Page 250: ...e signature register and the storage register Table 9 3 Types of CRC Detection to Check the Configuration Bits First Type of CRC Detection Second Type of CRC Detection CRAM error checking ability 32 b...

Page 251: ...device and the error detection clock frequency Table 9 4 Error Detection Registers Register Function 32 bit signature register This register contains the CRC signature The signature register contains...

Page 252: ...9 2 5 In the Device and Pin Options dialog box click the Error Detection CRC tab 6 Turn on Enable error detection CRC 7 In the Divide error check frequency by box enter a valid divisor as documented...

Page 253: ...The error detection circuit stores the computed 32 bit CRC signature in a 32 bit register which is read out by user logic from the core The cycloneiv_crcblock primitive is a WYSIWYG component used to...

Page 254: ...t be affected by a soft error To enable the cycloneiv_crcblock WYSIWYG atom you must name the atom for each Cyclone IV device accordingly Example 9 1 shows an example of how to define the input and ou...

Page 255: ...hift register parallel loads either the pre calculated CRC value or the update register contents depending on the ldsrc port input To do this the shiftnld must be driven low for at least two clock cyc...

Page 256: ...ision history for this chapter Table 9 8 Document Revision History Date Version Changes May 2013 1 3 Updated CRC_ERROR Pin Type in Table 9 2 October 2012 1 2 Updated Table 9 2 February 2010 1 1 Update...

Page 257: ...d 10 JTAG Boundary Scan Testing for Cyclone IV Devices This chapter describes the boundary scan test BST features that are supported in Cyclone IV devices The features are similar to Cyclone III devic...

Page 258: ...clone IV GX devices are different from the BSCs for I O pins Figure 10 1 shows the Cyclone IV GX HSSI transmitter boundary scan cell Figure 10 1 HSSI Transmitter BSC with IEEE Std 1149 6 BST Circuitry...

Page 259: ...ure 10 2 HSSI Receiver BSC with IEEE Std 1149 6 BST Circuitry for the Cyclone IV GX Devices HIGHZ SDIN SHIFT 0 1 0 1 D Q D Q CLK SDOUT UPDATE MODE AC_TEST Capture Update Registers BSRX1 BSOUT1 BSRX0 B...

Page 260: ...0000 0010 0000 1111 0001 000 0110 1110 1 EP4CE10 0000 0010 0000 1111 0001 000 0110 1110 1 EP4CE15 0000 0010 0000 1111 0010 000 0110 1110 1 EP4CE22 0000 0010 0000 1111 0011 000 0110 1110 1 EP4CE30 000...

Page 261: ...guration mode for Cyclone IV GX devices 1 When you perform JTAG boundary scan testing before configuration the nCONFIG pin must be held low I O Voltage Support in a JTAG Chain A Cyclone IV device oper...

Page 262: ...49 1 compliant Cyclone IV E devices refer to IEEE Std 1149 1 BSDL Files f For more information about how to download BSDL files for IEEE Std 1149 6 compliant Cyclone IV GX devices refer to IEEE Std 11...

Page 263: ...ory for this chapter Table 10 3 Document Revision History Date Version Changes December 2013 1 3 Updated the EXTEST_PULSE section November 2011 1 2 Updated the BST Operation Control section Updated Ta...

Page 264: ...10 8 Chapter 10 JTAG Boundary Scan Testing for Cyclone IV Devices Document Revision History Cyclone IV Device Handbook December 2013 Altera Corporation Volume 1...

Page 265: ...ations power on reset POR requirements and their implementation in Cyclone IV devices This chapter includes the following sections External Power Supply Requirements on page 11 1 Hot Socketing Specifi...

Page 266: ...e 11 1 1 You must power up VCCA even if the phase locked loop PLL is not used 2 I O banks 3 8 and 9 contain configuration pins You can only power up the VCCIO level of I O banks 3 and 9 to 1 5 V 1 8 V...

Page 267: ...er up and power down sequences 1 Altera uses GND as reference for hot socketing operation and I O buffer designs To ensure proper operation Altera recommends connecting the GND between boards before c...

Page 268: ...to the Configuration and Remote System Upgrades in Cyclone IV Devices chapter f For more information about the POR specifications refer to the Cyclone IV Device Datasheet chapter Document Revision Hi...

Page 269: ...101 Innovation Drive San Jose CA 95134 www altera com CYIV 5V2 1 9 Volume 2 Cyclone IV Device Handbook Cyclone IV Device Handbook Volume 2...

Page 270: ...nductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes n...

Page 271: ...15 Automatic Lock Mode 1 15 Manual Lock Mode 1 16 Deserializer 1 16 Word Aligner 1 17 Deskew FIFO 1 22 Rate Match FIFO 1 23 8B 10B Decoder 1 23 Byte Deserializer 1 24 Byte Ordering 1 24 RX Phase Compe...

Page 272: ...ion 1 76 Transmit Bit Slip Control 1 76 PLL PFD feedback 1 76 SDI Mode 1 76 Loopback 1 78 Reverse Parallel Loopback 1 79 Serial Loopback 1 79 Reverse Serial Loopback 1 80 Self Test Modes 1 81 BIST 1 8...

Page 273: ...1 Using logical_channel_address to Reconfigure Specific Transceiver Channels 3 14 Method 2 Writing the Same Control Signals to Control All the Transceiver Channels 3 16 Method 3 Writing Different Cont...

Page 274: ...vi Contents Cyclone IV Device Handbook February 2015 Altera Corporation Volume 2...

Page 275: ...ates Where chapters or groups of chapters are available separately part numbers are listed Chapter 1 Cyclone IV Transceivers Architecture Revised February 2015 Part Number CYIV 52001 3 7 Chapter 2 Cyc...

Page 276: ...viii Chapter Revision Dates Cyclone IV Device Handbook February 2015 Altera Corporation Volume 2...

Page 277: ...to Table 1 You can also contact your local Altera sales office or sales representative Visual Cue Meaning Bold Type with Initial Capital Letters Indicate command names dialog box titles dialog box opt...

Page 278: ...steps indicate a list of items when the sequence of the items is important such as the steps listed in a procedure Bullets indicate a list of items when the sequence of the items is not important 1 Th...

Page 279: ...This section includes the following chapters Chapter 1 Cyclone IV Transceivers Architecture Chapter 2 Cyclone IV Reset Control and Power Down Chapter 3 Cyclone IV Dynamic Reconfiguration Revision Hist...

Page 280: ...I 2 Section I Transceivers Cyclone IV Device Handbook February 2015 Altera Corporation Volume 2...

Page 281: ...tocols You can implement these protocols through the ALTGX MegaWizard Plug In Manager which also offers the highly flexible Basic functional mode to implement proprietary serial protocols at the follo...

Page 282: ...s offer either one or two transceiver blocks per device depending on the package Each block consists of four full duplex transmitter and receiver channels located on the left side of the device in a d...

Page 283: ...r Clocking Architecture on page 1 26 Transceiver Channel Datapath Clocking on page 1 29 FPGA Fabric Transceiver Interface Clocking on page 1 43 Calibration Block on page 1 45 PCI Express Hard IP Block...

Page 284: ...e FPGA fabric flows through the transmitter PCS and PMA is transmitted as serial data Received inbound serial data flows through the receiver PMA and PCS into the FPGA fabric The transceiver supports...

Page 285: ...tered mode contributing to only one parallel clock cycle of latency in Deterministic Latency functional mode For more information refer to Deterministic Latency Mode on page 1 73 f For more informatio...

Page 286: ...Dx y or a 10 bit control word Kx y Figure 1 6 shows the 8B 10B encoding operation with the tx_ctrlenable port where the second 8 hBC data is encoded as a control word when tx_ctrlenable port is asser...

Page 287: ...ng the running disparity to either positive or negative disparity with tx_forcedisp and tx_dispval ports Figure 1 8 shows an example of tx_forcedisp and tx_dispval port use where data is shown in hexa...

Page 288: ...rity inversion corrects accidentally swapped positive and negative signals from the serial differential link during board layout by inverting the polarity of each bit An optional tx_invpolarity port i...

Page 289: ...on reverses the input data to the transmitter phase compensation FIFO to 00111101 10110101 16 h3DB5 Bit slip control delays the data transmission by a number of specified bits to the serializer with t...

Page 290: ...mission media due to data dependent jitter and intersymbol interference ISI effects The requirement for pre emphasis increases as the data rates through legacy backplanes increase Programmable differe...

Page 291: ...eskew FIFO on page 1 22 Rate Match FIFO on page 1 23 8B 10B Decoder on page 1 23 Byte Deserializer on page 1 24 Byte Ordering on page 1 24 RX Phase Compensation FIFO on page 1 25 Receiver Input Buffer...

Page 292: ...ge as shown in Figure 1 12 Receiver OCT and on chip biasing circuitry automatically restores the common mode voltage The biasing circuitry is also enabled by enabling OCT If you disable the OCT then y...

Page 293: ...smitter common mode voltage is compatible with the receiver common mode requirements If you disable the OCT you must terminate and bias the receiver externally and ensure compatibility between the tra...

Page 294: ...set voltages that might exist from process variations between the positive and negative differential signals in the equalizer stage and CDR circuit Signal detection detects if the signal level present...

Page 295: ...pon receiver power up and reset cycle the CDR is put into LTR state Transition to the LTD state is performed automatically when both of the following conditions are met Signal detection circuitry indi...

Page 296: ...gic level on the rx_locktorefclk and rx_locktodata ports This mode provides the flexibility to control the CDR for a reduced lock time compared to the automatic lock mode In automatic lock mode the LT...

Page 297: ...ord aligner to re align to the new word boundary only if there is a rising edge in the rx_enapatternalign signal The 10 bit word aligner is level sensitive to the rx_enapatternalign signal The word al...

Page 298: ...l also goes high for one clock cycle to indicate initial word alignment At time n 1 the rx_enapatternalign signal is deasserted to instruct the word aligner to lock the current word boundary The align...

Page 299: ...dataout to 8 b01111000 Another rising edge on the rx_bitslip signal at time n 5 forces rx_dataout to 8 b00111100 Another rising edge on the rx_bitslip signal at time n 9 forces rx_dataout to 8 b000111...

Page 300: ...alid synchronization code groups are received again In addition to restoring word boundaries the word aligner supports the following features Programmable run length violation detection detects consec...

Page 301: ...he data bits at the input of the word aligner and is not available in PCI Express PIPE mode The PCI Express PIPE 8B 10B polarity inversion feature inverts the polarity of the data bits at the input of...

Page 302: ...This module is only available when used for the XAUI protocol and is used to align all four channels to meet the maximum skew requirement of 40 UI 12 8 ns as seen at the receiver of the four lanes The...

Page 303: ...ater than the upstream transmitter reference clock frequency Delete skip symbols when the local receiver reference clock frequency is less than the upstream transmitter reference clock frequency The 2...

Page 304: ...te and the least significant byte of the two byte transmitter data appears straddled across two word boundaries after the data is deserialized at the receiver The byte ordering block restores the prop...

Page 305: ...nsertion is necessary RX Phase Compensation FIFO The RX phase compensation FIFO compensates for the phase difference between the parallel receiver clock and the FPGA fabric interface clock when interf...

Page 306: ...tecture The multipurpose PLLs and general purpose PLLs located on the left side of the device generate the clocks required for the transceiver operation The following sections describe the Cyclone IV...

Page 307: ...ks for PLLs used in the transceiver operation 1 Clock output from PLLs in the FPGA core cannot feed into PLLs used by the transceiver as input reference clock Figure 1 25 PLL Input Reference Clocks in...

Page 308: ...ly These clock input pins do not have access to the clock control blocks and GCLK networks For more details refer to the Clock Networks and PLLs in Cyclone IV Devices chapter 3 Using any clock input p...

Page 309: ...transceiver datapath Figure 1 27 AC Coupled Termination Scheme for a Reference Clock Note to Figure 1 27 1 For more information about the VICM value refer to the Cyclone IV Device Datasheet chapter F...

Page 310: ...he two multipurpose PLLs is not supported For example based on Figure 1 29 a combination of MPLL_1 driving receiver channels 0 1 and 3 while MPLL_2 driving receiver channel 2 is not supported In this...

Page 311: ...el configuration 2 or 4 when implementing multi channel serial interface for a lower channel to channel skew In a transceiver block the high and low speed clocks for each channel are distributed prima...

Page 312: ...rces for Each Channel in Non Bonded Channel Configuration Package Transceiver Block Transceiver Channel High and Low Speed Clocks Sources Option 1 Option 2 F324 and smaller GXBL0 All channels MPLL_1 M...

Page 313: ...in F324 and smaller packages and in F484 and larger packages in non bonded channel configuration Figure 1 31 Clock Distribution in Non Bonded Channel Configuration for Transceivers in F324 and Smaller...

Page 314: ...operation The low speed clock feeds to the following blocks in the transmitter PCS 8B 10B encoder read clock of the byte serializer read clock of the TX phase compensation FIFO Figure 1 32 Clock Dist...

Page 315: ...of the RX phase compensation FIFO The low speed recovered clock is available in the FPGA fabric as rx_clkout port which can be used in the FPGA fabric to capture receiver data and status signals When...

Page 316: ...decoder write clock of byte deserializer byte ordering write clock of RX phase compensation FIFO When the byte deserializer is enabled the low speed clock frequency is halved before feeding into the w...

Page 317: ...m one of the two multipurpose PLLs directly adjacent to the block Transceiver channels for devices in F484 and larger packages support additional clocking flexibility for 2 bonded channels In these pa...

Page 318: ...l configuration Figure 1 36 Clock Distribution in Bonded 2 and 4 Channel Configuration for Transceivers in F324 and Smaller Packages Notes to Figure 1 36 1 Transceiver channels 2 and 3 are not availab...

Page 319: ...er read clock of byte serializer read clock of TX phase compensation FIFO Figure 1 37 Clock Distribution in Bonded 2 and 4 Channel Configuration for Transceivers in F484 and Larger Packages Notes to F...

Page 320: ...ed Channel Configuration Byte Serializer 8B 10B Encoder Transmitter Channel PCS 3 Transmitter Channel PMA 3 Serializer PCIe Hard IP FPGA Fabric PIPE Interface Tx Phase Comp FIFO wr_clk rd_clk wr_clk r...

Page 321: ...configuration with rate match FIFO and configuration without rate match FIFO Figure 1 39 shows the datapath clocking in Transmitter and Receiver operation with rate match FIFO in 2 and 4 bonded channe...

Page 322: ...p FIFO tx_dataout 2 wr_clk rd_clk wr_clk rd_clk high speed clock tx_coreclk 2 2 rx_coreclk 2 Receiver Channel PCS 2 Receiver Channel PMA 2 rx_datain 2 Deserial izer CDR Byte De serializer Byte Order i...

Page 323: ...ved before feeding to the write clock of RX phase compensation FIFO The common bonded low speed clock is available in FPGA fabric as coreclkout port which can be used in FPGA fabric to send transmitte...

Page 324: ...utomatic clock selection for RX phase compensation FIFO read clock if you do not enable the rx_coreclk port cal_blk_clk 2 Transceiver calibration block clock FPGA fabric to transceiver Notes to Table...

Page 325: ...ut clock feeds the FIFO read clock for the bonded channels coreclkout clock is the common bonded low speed clock which also feeds the FIFO read clock and transmitter PCS in the bonded channels Without...

Page 326: ...the Calibration Blocks 1 Notes to Figure 1 41 1 All transceiver channels use the same calibration block clock and power down signals 2 Connect a 2 k tolerance max 1 external resistor to the RREF pin t...

Page 327: ...tocol implementation Figure 1 43 PCIe with Hard IP Block Lane Placement Requirements 1 Note to Figure 1 43 1 Applicable for PCIe 1 2 and 4 implementations with hard IP blocks only Channel 3 Channel 2...

Page 328: ...hase frequency detector PFD feedback registered mode FIFO TX bit slip control Deterministic Latency Mode on page 1 73 SDI SDI High speed SERDES CDR SDI Mode on page 1 76 Table 1 14 Transceiver Functio...

Page 329: ...to Transceiver Interface Width FPGA Fabric to Transceiver Interface Frequency MHz 8 Bit Disabled Enabled 0 6 1 0 0 6 1 25 0 6 2 0 0 6 2 5 0 6 1 0 0 6 1 25 0 6 1 0 0 6 2 5 0 6 1 0 0 6 1 25 0 6 1 0 0 6...

Page 330: ...nterface Fredquency MHz Disabled Enabled Manual Alignment 7 Bit 10 Bit Disabled 8 Bit 16 Bit Disabled Disabled Disabled Enabled Bit Slip 7 Bit 10 Bit Disabled Enabled Disabled 10 Bit 20 Bit Basic 10 B...

Page 331: ...g electrical idle the output buffer assumes the common mode output voltage levels For details about the electrical idle features refer to PCI Express PIPE Mode on page 1 52 1 The transmitter in electr...

Page 332: ...ate compensation with rate match FIFO Low Latency Synchronous PCIe fast recovery from P0s state electrical idle inference compliance pattern transmission reset requirement Figure 1 48 shows the transc...

Page 333: ...Compiler User Guide Figure 1 49 shows the transceiver configuration in PIPE mode 1 When configuring the transceiver into PIPE mode using ALTGX megafunction for PCIe implementation the PHY MAC data lin...

Page 334: ...ter output buffer to be tri stated have OCT utilization 125 MHz clock on the fixedclk port The circuit works by sending a pulse on the common mode of the transmitter If an active PCIe receiver is pres...

Page 335: ...dle port During electrical idle the transmitter buffer differential and common mode output voltage levels are compliant to the PCIe Base Specification 2 0 for Gen1 signaling rate Figure 1 52 shows the...

Page 336: ...KP ordered set is a K28 5 comma COM symbol followed by one to five consecutive K28 0 SKP symbols which are sent by transmitter during the inter packet gap The rate match operation begins after the syn...

Page 337: ...module cannot detect electrical idle exit condition based on the reception of the electrical idle exit ordered set as specified in the PCI Express PIPE Base Specification 1 When enabled the electrical...

Page 338: ...ndard protocol implementation The Cyclone IV GX transceiver provides the PMA and the following PCS functions as defined in the IEEE 802 3 specification for 1000 Base X PHY 8B 10B encoding and decoding...

Page 339: ...mediate or transition layer that interfaces various physical media with the media access control MAC in a GbE system The 1000 Base X PHY which has a physical interface data rate of 1 25 Gbps consists...

Page 340: ...Optional rx_recovclkout port from CDR low speed recovered clock is available for applications such as Synchronous Ethernet 1 Byte Serializer 8B 10B Encoder Transmitter Channel PCS Transmitter Channel...

Page 341: ...f the three automatically sent K28 5 code groups and the first K28 5 code group of the synchronization sequence If there is an even number of Dx y code groups received between these two K28 5 code gro...

Page 342: ...th either of the following A D5 6 I1 ordered set if the running disparity before K28 5 is positive A D16 2 I2 ordered set if the running disparity before K28 5 is negative Lane Synchronization In GIGE...

Page 343: ...h operation 1 If you have the auto negotiation state machine in the FPGA note that the rate match FIFO is capable of inserting or deleting the first two bytes K28 5 D2 2 of C2 ordered sets during auto...

Page 344: ...ization state machine 1 Cyclone IV GX transceivers do not have built in support for some PCS functions such as pseudo random idle sequence generation and lane alignment in 4 bonded channel configurati...

Page 345: ...1 60 1 Optional rate match FIFO 2 High speed recovered clock 3 Low speed recovered clock 3 Byte Serializer 8B 10B Encoder Transmitter Channel PCS Transmitter Channel PMA Serializer PCIe Hard IP FPGA F...

Page 346: ...Number of valid synchronization K28 5 code groups received to achieve synchronization 127 Number of erroneous code groups received to lose synchronization 3 Number of continuous good code groups rece...

Page 347: ...tes the 10 bit skip pattern as necessary to avoid the rate match FIFO from overflowing or under running The rate match FIFO can delete insert a maximum of one skip pattern from a cluster 1 The rate ma...

Page 348: ...sparent extension of the physical reach of the XGMII and also reduces the interface pin count XAUI functions as a self managed interface because code group synchronization channel deskew and clock dom...

Page 349: ...2 Transmitter Channel PMA 2 Serializer Tx Phase Comp FIFO tx_dataout 2 wr_clk rd_clk wr_clk rd_clk high speed clock rx_coreclk 2 tx_coreclk 2 Receiver Channel PCS 2 Receiver Channel PMA 2 rx_datain 2...

Page 350: ...ing Low Latency PCS Word Aligner Pattern Length 8B 10B Encoder Decoder Deskew FIFO Rate Match FIFO Byte SERDES Byte Ordering FPGA Fabric to Transceiver Interface Width FPGA Fabric to Transceiver Inter...

Page 351: ...kew FIFO read and write pointers in each channel are not incremented After the first A code group is received the write pointer starts incrementing for each word received but the read pointer is froze...

Page 352: ...on state machine mode that is compliant to the PCS synchronization state diagram specified in clause 48 of the IEEE P802 3ae specification Table 1 23 lists the synchronization state machine parameters...

Page 353: ...d flags that indicate rate match FIFO deletion and insertion events respectively are forwarded to the FPGA fabric If an R column is deleted the rx_rmfifodeleted flag from each of the four channels goe...

Page 354: ...Latency Mode Note to Figure 1 66 1 High speed recovered clock Byte Serializer 8B 10B Encoder Transmitter Channel PCS Transmitter Channel PMA Serializer PCIe Hard IP FPGA Fabric PIPE Interface Tx Phas...

Page 355: ...e RX phase compensation FIFO is set to registered mode while the TX phase compensation FIFO supports optional registered mode When set into registered mode the phase compensation FIFO acts as a regist...

Page 356: ...lect 4 0 port based on values on rx_bitslipboundaryselectout 4 0 signal PLL PFD feedback In Deterministic Latency mode when transmitter input reference clock frequency is the same as the low speed clo...

Page 357: ...1 68 1 High speed recovered clock Byte Serializer 8B 10B Encoder Transmitter Channel PCS Transmitter Channel PMA Serializer PCIe Hard IP FPGA Fabric PIPE Interface Tx Phase Comp FIFO tx_datain tx_data...

Page 358: ...k available only for PIPE mode serial loopback available for all modes except PIPE mode reverse serial loopback available for all modes except XAUI mode 1 In each loopback mode all transmitter buffer...

Page 359: ...abric passes through the transmitter channel and looped back to the receiver channel bypassing the receiver buffer as shown in Figure 1 71 The received data is available to the FPGA logic for verifica...

Page 360: ...al loopback pre CDR option Post CDR mode where retimed data through the receiver CDR from the RX input buffer is looped back to the TX output buffer using the Reverse serial loopback option The receiv...

Page 361: ...udo random binary sequence PRBS generator and verifier the PRBS generator and verifier interface with the serializer and deserializer in the PMA blocks The advantage of using a PRBS data stream is tha...

Page 362: ...ion settings in this mode PCS FPGA fabric channel width 16 bit 8B 10B blocks Enabled Byte serializer deserializer Enabled Word aligner Automatic synchronization state machine mode Byte ordering Enable...

Page 363: ...annel PMA Transmitter Channel PMA Receiver Channel PCS Transmitter Channel PCS Tx Phase Compensation FIFO PRBS High Freq Low Freq Pattern Generator 8B 10B Encoder Byte Serializer Rx Compensation FIFO...

Page 364: ...e contains no error You can reset the PRBS pattern generator and verifier by asserting the tx_digitalreset and rx_digitalreset ports respectively Low Frequency 2 1111100000 N Y 2 5 3 125 Notes to Tabl...

Page 365: ...r Top Level Port Lists Table 1 26 through Table 1 29 provide descriptions of the ports available when instantiating a transceiver using the ALTGX megafunction The ALTGX megafunction requires a relativ...

Page 366: ...group A low level to encode data as a Dx y data code group tx_forcedisp Input Synchronous to tx_clkout non bonded modes or coreclkout bonded modes 8B 10B encoder forcing disparity control This signal...

Page 367: ...m effectively shifting the word boundary by one bit rx_rlv Output Asynchronous signal Driven for a minimum of two recovered clock cycles in configurations without byte serializer and a minimum of thre...

Page 368: ...ted received code group Use with the rx_disperr signal to differentiate between a code group violation or a disparity error as follows rx_errdetect rx_disperr 2 b00 no error 2 b10 code group violation...

Page 369: ...ignal Receiver CDR LTD state control signal A high level forces the CDR to LTD state When deasserted the receiver CDR lock state depends on the rx_locktorefclk signal level rx_locktorefclk Input Async...

Page 370: ...with negative running disparity Assert only when transmitting the first byte of the PIPE compliance pattern to force the 8B 10B encoder with a negative running disparity pipe8b10binvpolarity Input As...

Page 371: ...2 Block Port Name Input Output Clock Domain Description PLL pll_inclk Input Clock signal Input reference clock for the PLL multipurpose PLL or general purpose PLL used by the transceiver instance When...

Page 372: ...e Data Sheet chapter reconfig_togxb Input Asynchronous signal From the dynamic reconfiguration controller reconfig_fromgxb Output Asynchronous signal To the dynamic reconfiguration controller Calibrat...

Page 373: ...ns Updated Figure 1 37 December 2010 3 2 Updated for the Quartus II software version 10 1 release Updated Table 1 1 Table 1 5 Table 1 11 Table 1 14 Table 1 24 Table 1 25 Table 1 26 Table 1 27 Table 1...

Page 374: ...1 94 Chapter 1 Cyclone IV Transceivers Architecture Document Revision History Cyclone IV Device Handbook February 2015 Altera Corporation Volume 2...

Page 375: ...version of device specifications before relying on any published information and before placing orders for products or services Cyclone IV Device Handbook Volume 2 September 2014 Feedback Subscribe IS...

Page 376: ...italreset 1 Transmitter Only Receiver and Transmitter Provides asynchronous reset to all digital logic in the transmitter PCS including the XAUI transmit state machine The minimum pulse width for this...

Page 377: ...ently from the other reset signals This signal is common to the transceiver block pll_locked A status signal Indicates the status of the transmitter multipurpose PLLs or general purpose PLLs A high le...

Page 378: ...are All Supported Functional Modes Except the PCIe Functional Mode on page 2 6 describes the reset sequences in bonded and non bonded configurations PCIe Functional Mode on page 2 17 describes the res...

Page 379: ...hart Notes to Figure 2 2 1 Refer to the Timing Diagram in Figure 2 10 2 Refer to the Timing Diagram in Figure 2 3 3 Refer to the Timing Diagram in Figure 2 4 4 Refer to the Timing Diagram in Figure 2...

Page 380: ..._locktodata signals Bonded Channel Configuration In a bonded channel configuration you can reset all the bonded channels simultaneously Examples of bonded channel configurations are the XAUI PCIe Gen1...

Page 381: ...ration 1 After power up assert pll_areset for a minimum period of 1 s the time between markers 1 and 2 2 Keep the tx_digitalreset signal asserted during this time period After you de assert the pll_ar...

Page 382: ...nput reference clock 3 After the multipurpose PLL locks as indicated by the pll_locked signal going high deassert the tx_digitalreset signal At this point the transmitter is ready for data traffic Fig...

Page 383: ...r channel When the receiver CDR is in manual lock mode use the reset sequence shown in Figure 2 5 Figure 2 5 Sample Reset Sequence for Bonded Configuration Receiver and Transmitter Channels Receiver C...

Page 384: ...easserting rx_digitalreset the time between markers 7 and 8 At this point the transmitter and receiver are ready for data traffic Non Bonded Channel Configuration In non bonded channels each channel i...

Page 385: ...p the rx_digitalreset and rx_analogreset signals asserted during this time period 3 After the busy signal is deasserted wait for another two parallel clock cycles then deassert the rx_analogreset sign...

Page 386: ...deassert rx_pll_locked will assert 4 Wait for at least tLTR_LTD_Manual then deassert the rx_locktorefclk signal At the same time assert the rx_locktodata signal marker 3 5 Deassert rx_digitalreset at...

Page 387: ...rpose PLL locks as indicated by the pll_locked signal going high marker 3 deassert tx_digitalreset For receiver operation after deassertion of busy signal wait for two parallel clock cycles to deasser...

Page 388: ...eference clock 3 After the multipurpose PLL locks as indicated by the pll_locked signal going high marker 3 deassert tx_digitalreset marker 4 For receiver operation after deassertion of busy signal ma...

Page 389: ...stable reference clock because TX PLL locks to the incoming clock You can follow appropriate reset sequence provided in the device handbook starting from pll_locked assertion Loss of Link Due To Unpl...

Page 390: ...DR lock option For Manual CDR lock mode rx_freqlocked signal is not available Upon detection of a dead link take the following steps a Switch to LTR mode b Assert rx_digitalreset c Wait for rx_pll_loc...

Page 391: ...is timing diagram is drawn based on the PCIe Gen 1 1 mode 2 For bonded PCIe Gen 1 2 and 4 modes there will be additional rx_freqlocked n signal n number of channels 3 For tLTD_Manual duration refer to...

Page 392: ...ert the rx_analogreset signal After rx_analogreset is deasserted the receiver CDR starts locking to the receiver input reference clock 3 Deassert both the rx_analogreset signal marker 6 and rx_digital...

Page 393: ...l 1 Assert the tx_digitalreset rx_analogreset and rx_digitalreset signals The pll_configupdate signal is asserted marker 1 by the ALTPLL_RECONFIG megafunction after the final data bit is sent out The...

Page 394: ...in Figure 2 12 when you are using the dynamic reconfiguration controller to change the PCS settings of the transceiver channel In this example the dynamic reconfiguration is used to dynamically reconf...

Page 395: ...de 5 Deassert the tx_digitalreset signal marker 5 This signal must be deasserted after assertion of the channel_reconfig_done signal marker 4 and before the deassertion of the rx_analogreset signal ma...

Page 396: ...not necessary to wait for tLTD_Auto as suggested in the actual reset sequence The busy signal is deasserted after about 20 parallel reconfig_clk clock cycles in order to reduce simulation run time For...

Page 397: ...e useful reference terms used in this chapter refer to the links listed in Table 2 7 Table 2 7 Reference Information Terms Used in this Chapter Useful Reference Points Automatic Lock Mode page 2 8 Bon...

Page 398: ...Channel Receiver CDR in Manual Lock Mode and Receiver and Transmitter Channel Receiver CDR in Manual Lock Mode November 2011 1 2 Updated the All Supported Functional Modes Except the PCIe Functional...

Page 399: ...ransceivers without powering down any part of the device This chapter describes and provides examples about the different modes available for dynamic reconfiguration You can use the ALTGX_RECONFIG and...

Page 400: ...information about the various ALTGX MegaWizard Plug In Manager options that you set Each word in the mif is 16 bits wide The dynamic reconfiguration controller writes information from the mif into th...

Page 401: ...instances to control one transceiver block Figure 3 1 Dynamic Reconfiguration Controller Note to Figure 3 1 1 The PMA control ports consist of the VOD pre emphasis DC gain and manual equalization con...

Page 402: ...lect in the What is the number of channels option in the General screen For example if you select the number of channels in the ALTGX instance as follows 1 Channels 4 then the output port reconfig_fro...

Page 403: ...icates the successful completion of the offset cancellation process PMA controls reconfiguration mode this signal is high when the dynamic reconfiguration controller performs a read or write transacti...

Page 404: ...one Number of channels controlled logical_channel_address by the reconfiguration controller input port width 2 logical_channel_address 0 3 4 logical_channel_address 1 0 5 8 logical_channel_address 2...

Page 405: ...Use logical_channel_address port for Analog controls reconfiguration option or the Use same control signal for all the channels option in the Analog controls screen Otherwise the width of this signal...

Page 406: ...responding ALTGX Corresponding pre instance settings emphasis setting mA 00000 0 Disabled 00001 1 0 5 00101 5 1 0 01001 9 1 5 01101 13 2 0 10000 16 2 375 10001 17 2 5 10010 18 2 625 10011 19 2 75 1010...

Page 407: ...gnal depends on the number of channels controlled by the dynamic reconfiguration controller and also the configuration of the Use logical_channel_address port for Analog controls reconfiguration optio...

Page 408: ...nal signal you can select in the Channel reconfiguration screen This signal is applicable only in dynamic reconfiguration modes grouped under the Channel reconfiguration option Enable this signal and...

Page 409: ...by disconnecting the receiver input pins from the receiver data path Subsequently the offset cancellation process goes through different states and culminates in the offset cancellation of the receiv...

Page 410: ...amically without powering down the other transceiver channels or the FPGA fabric of the device Analog PMA controls reconfiguration Channel reconfiguration PLL reconfiguration Table 3 3 lists the suppo...

Page 411: ...controls for all supported transceiver configurations channels as configured in the ALTGX instances Pre emphasis settings Equalization settings channel reconfiguration mode does not support equalizat...

Page 412: ...he corresponding value on the rx_tx_duplex_sel input port For more information refer to Table 3 2 on page 3 4 Connecting the PMA Control Ports The selected PMA control ports remain fixed in width rega...

Page 413: ...l is low before you start a read transaction 4 Assert the read signal for one reconfig_clk clock cycle This initiates the read transaction The busy output status signal is asserted high to indicate th...

Page 414: ...ls tab of the ALTGX_RECONFIG MegaWizard Plug In Manager If you enable this option the width of the PMA control ports are fixed as follows PMA Control Ports Used in a Write Transaction tx_vodctrl is fi...

Page 415: ...the VOD perform the following steps 1 Before you initiate a write transaction set the selected PMA control ports to the desired settings for example tx_vodctrl 3 b001 2 Set the rx_tx_duplex_sel port...

Page 416: ...low before you start a read transaction 3 Assert the read signal for one reconfig_clk clock cycle This initiates the read transaction 4 The busy output status signal is asserted high to indicate that...

Page 417: ...n Method 2 Writing the Same Control Signals to Control All the Transceiver Channels on page 3 16 Write Transaction Because the PMA controls of all the channels are written if you want to reconfigure a...

Page 418: ...nly of the transceiver channel For more information refer to Dynamic Reconfiguration Controller Port List on page 3 4 You can enable the rx_tx_duplex_sel port by selecting the Use rx_tx_duplex_sel por...

Page 419: ...ration modes The mif carries the reconfiguration information that will be used to reconfigure the transceivers channel dynamically on the fly The mif contents is generated automatically when you selec...

Page 420: ...ainfull the width of this input signal depends on the number of channels you set up in the ALTGX MegaWizard Plug In Manager It is 22 bits wide per channel This signal is available only for Transmitter...

Page 421: ...or PCIe tx_datainfull 10 Forced electrical idle tx_forceelecidle 10 bit FPGA fabric Transceiver Channel Interface tx_datainfull 9 0 10 bit data tx_datain 16 bit FPGA fabric Transceiver Channel Interfa...

Page 422: ...error status signal rx_disperr rx_dataoutfull 12 Pattern detect status signal rx_patterndetect rx_dataoutfull 13 Rate Match FIFO deletion status indicator rx_rmfifodatadeleted in non PCI Express PIPE...

Page 423: ...rx_disperr LSB and rx_dataoutfull 27 rx_disperr MSB Two Receiver Pattern Detect Bits rx_dataoutfull 12 rx_patterndetect LSB and rx_dataoutfull 28 rx_patterndetect MSB rx_dataoutfull 13 and rx_dataout...

Page 424: ...Cyclone IV GX Transceiver Architecture chapter 20 bit FPGA fabric Transceiver Channel Interface with PCS PMA set to 10 bits Two 10 bit Data rx_dataout rx_dataoutfull 9 0 rx_dataout LSByte and rx_datao...

Page 425: ...g_done busy The ALTGX_RECONFIG connection to the ALTGX instances when set in channel reconfiguration mode are as follows For the port information refer to Dynamic Reconfiguration Controller Port List...

Page 426: ...locks to write into the Transmit Phase Compensation FIFO tx_coreclk you can use a clock of the same frequency as tx_clkout from the FPGA fabric to provide the write clock to the Transmit Phase Compens...

Page 427: ...he remaining channels in the transceiver block This option is typically enabled when all the channels of a transceiver block have the same functional mode and data rate and are reconfigured to the ide...

Page 428: ...eiver core clocking refers to the clock that is used to read the parallel data from the Receiver Phase Compensation FIFO into the FPGA fabric You can use one of the following clocks to read from the R...

Page 429: ...els in the transceiver block This option is typically enabled when all the channels of a transceiver block are in a Basic or Protocol configuration with rate matching enabled and are reconfigured to a...

Page 430: ...data rates and are reconfigured to another Basic or Protocol functional mode with rate matching enabled Figure 3 14 shows the respective tx_clkout of each channel clocking the respective channels of...

Page 431: ...hout affecting the remaining blocks of the channel When you reconfigure the multipurpose PLL or general purpose PLL of a transceiver block to run at a different data rate all the transceiver channels...

Page 432: ...ne IV GX Devices Figure 3 16 shows the connection for PLL reconfiguration mode f For more information about connecting the ALTPLL_RECONFIG and ALTGX instances refer to the AN 609 Implementing Dynamic...

Page 433: ...ta n 0 Input Receives the scan data input from the ALTPLL_RECONFIG megafunction The reconfigurable transceiver PLL received the scan data input through this port for the dynamically reconfigurable bit...

Page 434: ...this option the dynamic reconfiguration controller checks whether an attempted operation falls under one of the conditions listed below The dynamic reconfiguration controller detects these conditions...

Page 435: ...d during the offset cancellation sequence for functional simulation and silicon Document Revision History Table 3 8 lists the revision history for this chapter Table 3 8 Document Revision History Date...

Page 436: ...3 38 Chapter 3 Cyclone IV Dynamic Reconfiguration Document Revision History Cyclone IV Device Handbook November 2011 Altera Corporation Volume 2...

Page 437: ...101 Innovation Drive San Jose CA 95134 www altera com CYIV 5V3 2 1 Volume 3 Cyclone IV Device Handbook Cyclone IV Device Handbook Volume 3...

Page 438: ...nductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes n...

Page 439: ...rnal Weak Pull Up and Weak Pull Down Resistor 1 11 Hot Socketing 1 11 Schmitt Trigger Input 1 12 I O Standard Specifications 1 12 Power Consumption 1 16 Switching Characteristics 1 16 Transceiver Perf...

Page 440: ...iv Contents Cyclone IV Device Handbook December 2016 Altera Corporation Volume 3...

Page 441: ...vision Dates The chapters in this document Cyclone IV Device Handbook were revised on the following dates Where chapters or groups of chapters are available separately part numbers are listed Chapter...

Page 442: ...vi Chapter Revision Dates Cyclone IV Device Handbook December 2016 Altera Corporation Volume 3...

Page 443: ...to Table 1 You can also contact your local Altera sales office or sales representative Visual Cue Meaning Bold Type with Initial Capital Letters Indicate command names dialog box titles dialog box opt...

Page 444: ...steps indicate a list of items when the sequence of the items is important such as the steps listed in a procedure Bullets indicate a list of items when the sequence of the items is not important 1 Th...

Page 445: ...the Cyclone IV device datasheet It includes the following chapter Chapter 1 Cyclone IV Device Datasheet Revision History Refer to each chapter for its own specific revision history For information ab...

Page 446: ......

Page 447: ...O element IOE delay and programmable output buffer delay This chapter includes the following sections Operating Conditions on page 1 1 Power Consumption on page 1 16 Switching Characteristics on page...

Page 448: ...or periods shorter than 20 ns Table 1 2 lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage over the lifetime of the device The maximum allowed...

Page 449: ...1 2 for an overshoot of 4 3 V the percentage of high time for the overshoot can be as high as 65 over a 10 year period Percentage of high time is calculated as delta T T 100 This 10 year period assum...

Page 450: ...03 V VCCIO 3 4 Supply voltage for output buffers 3 3 V operation 3 135 3 3 3 465 V Supply voltage for output buffers 3 0 V operation 2 85 3 3 15 V Supply voltage for output buffers 2 5 V operation 2 3...

Page 451: ...x Unit Table 1 4 Recommended Operating Conditions for Cyclone IV GX Devices Part 1 of 2 Symbol Parameter Conditions Min Typ Max Unit VCCINT 3 Core voltage PCIe hard IP block and transceiver PCS power...

Page 452: ...ring device operation Configurations pins are powered up by VCCIO of I O Banks 3 8 and 9 where I O Banks 3 and 9 only support VCCIO of 1 5 1 8 2 5 3 0 and 3 3 V For fast passive parallel FPP configura...

Page 453: ...disabled in configuration mode Table 1 7 lists bus hold specifications for Cyclone IV devices Table 1 6 I O Pin Leakage Current for Cyclone IV Devices 1 2 Symbol Parameter Conditions Device Min Typ Ma...

Page 454: ...V Devices Part 2 of 2 1 Parameter Condition VCCIO V Unit 1 2 1 5 1 8 2 5 3 0 3 3 Min Max Min Max Min Max Min Max Min Max Min Max Table 1 8 Series OCT Without Calibration Specifications for Cyclone IV...

Page 455: ...1 2 0 161 0 288 Note to Table 1 10 1 This specification is not applicable to EP4CGX15 EP4CGX22 and EP4CGX30 devices Equation 1 1 Final OCT Resistance 1 2 3 4 5 6 RV V2 V1 1000 dR dV 7 RT T2 T1 dR dT...

Page 456: ...all Grid Array BGA Unit CIOTB Input capacitance on top and bottom I O pins 7 7 6 pF CIOLR Input capacitance on right I O pins 7 7 5 pF CLVDSLR Input capacitance on right I O pins with dedicated LVDS o...

Page 457: ...0 k VCCIO 3 0 V 5 4 6 22 36 k VCCIO 2 5 V 5 4 6 25 43 k VCCIO 1 8 V 5 4 7 35 71 k VCCIO 1 5 V 5 4 8 50 112 k Notes to Table 1 12 1 All I O pins have an option to enable weak pull up except the configu...

Page 458: ...Min Max Min Max Max Min 3 3 V LVTTL 3 3 135 3 3 3 465 0 8 1 7 3 6 0 45 2 4 4 4 3 3 V LVCMOS 3 3 135 3 3 3 465 0 8 1 7 3 6 0 2 VCCIO 0 2 2 2 3 0 V LVTTL 3 2 85 3 0 3 15 0 3 0 8 1 7 VCCIO 0 3 0 45 2 4...

Page 459: ...VREF DC 4 Value shown refers to AC input reference voltage VREF AC Table 1 17 Single Ended SSTL and HSTL I O Standards Signal Specifications for Cyclone IV Devices I O Standard VIL DC V VIH DC V VIL...

Page 460: ...fications for Cyclone IV Devices 1 I O Standard VCCIO V VDIF DC V VX AC V VCM DC V VDIF AC V Min Typ Max Min Max Min Typ Max Min Typ Max Mi n Max HSTL 18 Class I II 1 71 1 8 1 89 0 2 0 85 0 95 0 85 0...

Page 461: ...1 2 1 5 PPDS Row I Os 5 2 375 2 5 2 625 100 200 600 0 5 1 2 1 4 PPDS Column I Os 5 2 375 2 5 2 625 100 200 600 0 5 1 2 1 4 Notes to Table 1 20 1 For an explanation of terms used in Table 1 20 refer t...

Page 462: ...ed circuit models can yield very accurate power estimates f For more information about power estimation tools refer to the Early Power Estimator User Guide and the PowerPlay Power Analysis chapter in...

Page 463: ...al interface for PCI Express PIPE mode 30 33 30 33 30 33 kHz Spread spectrum downspread PIPE mode 0 to 0 5 0 to 0 5 0 to 0 5 Peak to peak differential input voltage 0 1 1 6 0 1 1 6 0 1 1 6 V VICM AC c...

Page 464: ...CM 0 82 V setting 820 10 820 10 820 10 mV Differential on chip termination resistors 100 setting 100 100 100 150 setting 150 150 150 Differential and common mode return loss PIPE Serial Rapid I O SR S...

Page 465: ...ain Setting 2 6 6 6 dB Transmitter Supported I O Standards 1 5 V PCML Data rate F324 and smaller package 600 2500 600 2500 600 2500 Mbps Data rate F484 and larger package 600 3125 600 3125 600 2500 Mb...

Page 466: ...for the F484 F672 and F896 device packages only Pending device characterization 7 To support CDR ppm tolerance greater than 300 ppm implement ppm detector in user logic and configure CDR to Manual Loc...

Page 467: ...parameters in automatic mode Figure 1 2 Lock Time Parameters for Manual Mode rx _analogreset rx _ digitalreset Reset Signals Output Status Signals rx _ locktorefclk 2 3 4 CDR Control Signals rx _ loc...

Page 468: ...form Differential Waveform VID diff peak peak 2 x VID single ended Positive Channel p Negative Channel n Ground VID VID VID p n 0 V VCM Figure 1 5 Transmitter Output Waveform Single Ended Waveform Dif...

Page 469: ...neration 4 Deterministic jitter peak to peak Pattern CRPAT 0 14 0 14 0 14 UI Total jitter peak to peak Pattern CRPAT 0 279 0 279 0 279 UI GIGE Receiver Jitter Tolerance 4 Deterministic jitter toleranc...

Page 470: ...1 Cyclone IV E 1 0 V core voltage devices only support C8L C9L and I8L speed grades Table 1 24 Clock Tree Performance for Cyclone IV Devices Part 2 of 2 Device Performance Unit C6 C7 C8 C8L 1 C9L 1 I7...

Page 471: ...cable for general purpose PLLs and multipurpose PLLs 2 You must connect VCCD_PLL to VCCINT through the decoupling capacitor and ferrite bead 3 This parameter is limited in the Quartus II software by t...

Page 472: ...Memory C6 C7 I7 A7 C8 C8L I8L C9L M9K Block FIFO 256 36 47 1 315 274 238 200 157 MHz Single port 256 36 0 1 315 274 238 200 157 MHz Simple dual port 256 36 CLK 0 1 315 274 238 200 157 MHz True dual po...

Page 473: ...is only supported for Cyclone IV E devices Table 1 30 JTAG Timing Parameters for Cyclone IV Devices 1 Symbol Parameter Min Max Unit tJCP TCK clock period 40 ns tJCH TCK clock high time 19 ns tJCL TCK...

Page 474: ...Transmitter Timing Specifications for Cyclone IV Devices 1 2 4 Part 1 of 2 Symbol Modes C6 C7 I7 C8 A7 C8L I8L C9L Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max fHSCLK input clock...

Page 475: ...grades Table 1 31 RSDS Transmitter Timing Specifications for Cyclone IV Devices 1 2 4 Part 2 of 2 Symbol Modes C6 C7 I7 C8 A7 C8L I8L C9L Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ M...

Page 476: ...MHz 4 5 200 5 155 5 5 155 5 5 155 5 5 132 5 MHz 2 5 200 5 155 5 5 155 5 5 155 5 5 132 5 MHz 1 5 400 5 311 5 311 5 311 5 265 MHz Device operation in Mbps 10 100 400 100 311 100 311 100 311 100 265 Mbps...

Page 477: ...DS transmitter is only supported at the output pin of Row I O Banks 1 2 5 and 6 Cyclone IV GX true LVDS transmitter is only supported at the output pin of Row I O Banks 5 and 6 2 tLOCK is the time req...

Page 478: ...Max Min Max Min Max Table 1 36 LVDS Receiver Timing Specifications for Cyclone IV Devices 1 3 Symbol Modes C6 C7 I7 C8 A7 C8L I8L C9L Unit Min Max Min Max Min Max Min Max Min Max fHSCLK input clock fr...

Page 479: ...ecified in the JEDEC DDR2 standard 2 The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global clock GCLK network Tabl...

Page 480: ...tings are generally linear For the exact values for each setting use the latest version of the Quartus II software 2 The minimum and maximum offset timing numbers are in reference to setting 0 as avai...

Page 481: ...nerally linear For the exact values for each setting use the latest version of the Quartus II software 2 The minimum and maximum offset timing numbers are in reference to setting 0 as available in the...

Page 482: ...rally linear For exact values of each setting use the latest version of the Quartus II software 2 The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartu...

Page 483: ...es a more accurate and precise I O timing data based on the specifics of the design after place and route is complete f The Excel based I O Timing spreadsheet is downloadable from Cyclone IV Devices L...

Page 484: ...he PLL specification parameters Q Table 1 46 Glossary Part 2 of 5 Letter Term Definitions TDO TCK tJPZX tJPCO tJSCO tJSXZ tJPH tJSH tJPXZ tJCP tJPSU_TMS t JCL tJCH TDI TMS Signal to be Captured Signal...

Page 485: ...The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined After the receiver input crosses the AC value the receiver changes to the new logic st...

Page 486: ...val TUI High speed I O block The timing budget allowed for skew propagation delays and data sampling window TUI 1 Receiver Input Clock Frequency Multiplication Factor tC w tINJITTER Period jitter on t...

Page 487: ...en the positive and complementary conductors of a differential transmission at the transmitter VOD VOH VOL VOH Voltage output high The maximum positive voltage from an output that the device considers...

Page 488: ...able 1 35 November 2011 1 5 Updated Maximum Allowed Overshoot or Undershoot Voltage Operating Conditions and PLL Specifications sections Updated Table 1 2 Table 1 3 Table 1 4 Table 1 5 Table 1 8 Table...

Page 489: ...Device Handbook Volume 3 February 2010 1 1 Updated Table 1 3 through Table 1 44 to include information for Cyclone IV E devices and Cyclone IV GX devices for Quartus II software version 9 1 SP1 relea...

Page 490: ...1 44 Chapter 1 Cyclone IV Device Datasheet Document Revision History Cyclone IV Device Handbook December 2016 Altera Corporation Volume 3...

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