Altera Cyclone IV, Device Handbook

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Chapter 3: Memory Blocks in Cyclone IV Devices 3–15
Design Considerations
November 2011 Altera Corporation Cyclone IV Device Handbook,
Volume 1
Read or Write Clock Mode
Cyclone IV devices M9K memory blocks can implement read or write clock mode for
FIFO and simple dual-port memories. In this mode, a write clock controls the data
inputs, write address, and
wren
registers. Similarly, a read clock controls the data
outputs, read address, and
rden
registers. M9K memory blocks support independent
clock enables for both the read and write clocks.
When using read or write mode, if you perform a simultaneous read or write to the
same address location, the output read data is unknown. If you require the output
data to be a known value, use either single-clock mode, input clock mode, or output
clock mode and choose the appropriate read-during-write behavior in the
MegaWizard Plug-In Manager.
Single-Clock Mode
Cyclone IV devices M9K memory blocks can implement single-clock mode for FIFO,
ROM, true dual-port, simple dual-port, and single-port memories. In this mode, you
can control all registers of the M9K memory block with a single clock together with
clock enable.
Design Considerations
This section describes designing with M9K memory blocks.
Read-During-Write Operations
“Same-Port Read-During-Write Mode” on page 3–16 and “Mixed-Port Read-During-
Write Mode” on page 3–16 describe the functionality of the various RAM
configurations when reading from an address during a write operation at that same
address.
There are two read-during-write data flows: same-port and mixed-port. Figure 3–13
shows the difference between these flows.
Figure 3–13. Cyclone IV Devices Read-During-Write Data Flow
Port A
data in Port B
data in
Port A
data o
u t
Port B
data o
u t
Mixed-port
data flow
Same-port
data flow
write_a
read_a
read_b
write_b