Agilent Technologies 86100A, Programmer'S Manual, Page: 97 / 366

3-3
Common Commands
*CLS (Clear Status)
it will also block the execution of the remote script until all pending operations are finished. It
is particularly useful if the host computer is connected to two or more instruments. This com-
mand will not block the GPIB bus, allowing the computer to continue issuing commands to
the instrument not executing the *WAI command.
*CLS (Clear Status)
Command *CLS
The *CLS command clears all status and error registers. Refer to “Error Messages” on
page 1-45 for a complete discussion of status.
Example This example clears the status data structures of the analyzer.
10 OUTPUT 707;"*CLS"
*ESE (Event Status Enable)
Command *ESE <mask>
The *ESE command sets the Standard Event Status Enable Register bits.
<mask> An integer, 0 to 255, representing a mask value for the bits to be enabled in the Standard
Event Status Register as shown in
Table 3-2 on page 3-3 .
Example
This example enables the User Request (URQ) bit of the Standard Event Status Enable Reg-
ister. When this bit is enabled and a front-panel key is pressed, the Event Summary bit (ESB)
in the Status Byte Register is also set.
10 OUTPUT 707;"*ESE 64"
Query *ESE?
The *ESE? query returns the current contents of the Standard Event Status Enable Register.
Returned Format <mask><NL>
<mask> An integer, +0 to +255 (the plus sign is also returned), representing a mask value for the bits
enabled in the Standard Event Status Register as shown in
Table 3-2 on page 3-3 .
Example
This example places the current contents of the Standard Event Status Enable Register in
the numeric variable, Event.
10 OUTPUT 707;"*ESE?"
20 ENTER 707;Event
The Standard Event Status Enable Register contains a mask value for the bits to be enabled
in the Standard Event Status Register. A "1" in the Standard Event Status Enable Register
enables the corresponding bit in the Standard Event Status Register. A "0" in the enable reg-
ister disables the corresponding bit.
Table 3-2. Standard Event Status Enable Register Bits
Bit Weight Enables Definition
7 128 PON - Power On Indicates power is turned on.
6 64 URQ - User Request Not used. Permanently set to zero.
5 32 CME - Command Error Indicates whether the parser detected an error.