Agilent Technologies 86100A, Programmer'S Manual, Page: 20 / 366

1-16
Introduction
Status Reporting
This BASIC example uses the *STB? query to read the contents of the instrument’s Status
Byte Register when none of the register's summary bits are enabled to generate an SRQ inter-
rupt.
10 OUTPUT 707;":SYSTEM:HEADER OFF;*STB?"!Turn headers off
20 ENTER 707;Result!Place result in a numeric variable
30 PRINT Result!Print the result
40 End
The next program prints 132 and clears bit 6 (RQS) of the Status Byte Register. The differ-
ence in the decimal value between this example and the previous one is the value of bit 6
(weight = 64). Bit 6 is set when the first enabled summary bit is set, and is cleared when the
Status Byte Register is read by the serial poll command.
This example uses the BASIC serial poll (SPOLL) command to read the contents of the
instrument’s Status Byte Register.
10 Result = SPOLL(707)
20 PRINT Result
30 END
Use Serial Polling to Read the Status Byte Register. Serial polling is the preferred method to
read the contents of the Status Byte Register because it resets bit 6 and allows the next
enabled event that occurs to generate a new SRQ interrupt.
Service Request
Enable Register Setting the Service Request Enable Register bits enables corresponding bits in the Status
Byte Register. These enabled bits can then set RQS and MSS (bit 6) in the Status Byte Regis-
ter. Bits are set in the Service Request Enable Register using the *SRE command, and the
bits that are set are read with the *SRE? query. Bit 6 always returns 0. Refer to the Status
Reporting Data Structures shown in
Figure 1-4 This example sets bit 4 (MAV) and bit 5 (ESB)
in the Service Request Enable Register.
OUTPUT 707;"*SRE 48"
This example uses the parameter “48” to allow the instrument to generate an SRQ interrupt
under the following conditions:
• When one or more bytes in the Output Queue set bit 4 (MAV).
• When an enabled event in the Standard Event Status Register generates a summary bit that
sets bit 5 (ESB).
Trigger Event
Register (TRG)
This register sets the TRG bit in the status byte when a trigger event occurs. The TRG event
register stays set until it is cleared by reading the register or using the *CLS (clear status)
command. If your application needs to detect multiple triggers, the TRG event register must
be cleared after each one. If you are using the Service Request to interrupt a computer oper-
ation when the trigger bit is set, you must clear the event register after each time it is set.