ABB TPU2000, Technical Manual

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TPU2000/2000R Modbus/Modbus Plus/ Modbus TCP/IP Automation Guide
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installation. The two functionality’s are those in excess of the real time status access that Modbus function code
01 affords.
Momentary Change Detect status is incorporated using two bits to indicate present status and momentary
indication status. The odd bit is the status bit and the even bit is the momentary bit. The status bit indicates the
present state of the element accessed. The momentary bit indicates element transitioning more than once
between IED reads. The momentary bit is set to a “1” if the element has transitioned more than once. The bit is
reset upon a host access. Addresses 00513 through 01056 are allocated for momentary change bit detect status
detection. NOTE: MOMENTARY BITS MUST BE READ IN PAIRS.
An example of momentary change detect is illustrated in Figure 5-17. Suppose a host device monitors
TPU2000R physical output bit 1. Figure 5-17 illustrates the physical output transitions of output 1. At each output
rising edge/falling edge transition, the status of the Modbus coil 0x addresses are listed. The dotted line
arrows
indicate the poll received by the TPU2000R and the state of both the status bit and the momentary indication bit.
Note that the even bit (momentary change detect) resets itself to a zero state after a host read.
EC
OUTPUT 1 (ADDR 00270)
REAL TIME STATE
00271 OUTPUT 1
echo’s that of 01053 when read.
1
0
MOMENTARY STATE
01053 STATUS
OUTPUT 1
01054 MOMENTARY
OUTPUT 1
TIME = 0
0 1 1 0 0 1 0 0 1 0 1 1
0 0 0 0 0 0 1 0 0 1 1 0
HOST READS
DPU 2000R
01053 = 1
01054 = 0 HOST READS
DPU 2000R
01053 = 0
01054 = 0
HOST READS HOST READS
DPU 2000R DPU 2000R
01053 = 0 01053 = 1
01054 = 1 01054 = 1
01054 RESETS AFTER HOST
READ. OUTPUT 1
STATE TRANSITIONED
MORE THAN ONCE
BETWEEN HOST ACCESSES
Figure 5-17. Momentary Change Detect Example
Latched Element Retention is a method by which when an element has transitions from a 0 (inactive), to a 1
(active) status, the element is set to “1”. The element stays at a status of 1 until the operator executes a reset
sequence. The reset of latched points may occur:
The operator may depress the “SYSTEM RESET” pushbutton at the faceplate of the TPU2000R
Depress the “C”, “E”, and “ ↑ ” (UP ARROW), keys simultaneously on the membrane keypad
(TPU2000R and TPU2000)
Initiate a supervisory bit reset sequence for the individual bits requiring reset. Reference Section 5 of
this guide for a detailed explanation of the reset procedure.
Figure 5-18 illustrates the operation of a latched bit sequence. The LATCHED elements are denoted with the
symbol
(L) within the tables. Example latched elements are addresses 0050 through 0069 in Table 5-1 of this
document.