TPU2000/2000R Modbus/Modbus Plus/ Modbus TCP/IP Automation Guide
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10/3
Contact OUT2 least significant low byte
11/1
Contact OUT1 most significant high byte
11/2
Contact OUT1 most significant low byte
11/3
Contact OUT1 least significant high byte
12/1
Contact OUT1 least significant low byte
12/2-22/1
spare
22/2
Checksum high byte
22/3
Checksum low byte
Bit
Logical Output
---
--------------
0
TRIP
1
OUTPUT1
2
OUTPUT2
3
OUTPUT3
.
.
.
30
OUTPUT29
31
OUTPUT30
11.6 Receive Programmable Output AND/OR Index ( 3 11 6 )
Bit = 0, Selected outputs are ORed together.
Bit = 1, Selected outputs are ANDed together.
Index byte is the offset into the TPU's logical output structure.
Index
Output
Definition
00
DIFF
Fixed Diff Trip, 87T or 87H
01
ALARM
Fixed Self Check Alarm
02
87T
Percentage
Differential
Trip
03
87H
High
Set
Inst
Diff
Trip
04
2HROA
2nd Harm Restraint Output Alarm
05
5HROA
5th
Harm
Restraint
Alarm
06
AHROA
All
Harm
Restraint
Alarm
07
TCFA
Trip
Circuit
Failure
Alarm
08
TFA
Trip
Failure
Alarm
09
51P-1
Wdg 1 Phase Time OC Trip
10
51P-2
Wdg 2 Phase Time OC Trip
11
50P-1
1st Wdg 1 Phase Inst OC Trip
12
150P-1
2nd Wdg 1 Phase Inst OC Trip
13
50P-2
1st Wdg 2 Phase Inst OC Trip
14
150P-2
2nd Wdg 2 Phase Inst OC Trip
15
51N-1
Wdg 1 Neutral Time OC Trip
16
51G-2
Wdg 2 Ground Time OC Trip
17
50N-1
1st Wdg 1 Neutral Inst OC Trip
18
150N-1
2nd Wdg 1 Neutral Inst OC Trip
19
50G-2
1st Wdg 2 Ground Inst OC Trip
20
150G-2
2nd Wdg 2 Ground Inst OC Trip
21
46-1
Wdg 1 Neg Sequence Time OC Trip
22
46-2
Wdg 2 Neg Sequence Time OC Trip
23
87T-D
Percentage
Differential
Disabled
Alarm
24
87H-D
High Set Inst Diff Disabled Alarm
25
51P-1D
Wdg 1 Phase Time OC Disabled Alarm
26
51P-2D
Wdg 2 Phase Time OC Disabled Alarm
27
51N-1D
Wdg 1 Neutral Time OC Disabled Alarm
28
51G-2D
Wdg 2 Ground Time OC Disabled Alarm
29
50P-1D
1st Wdg 1 Phase Inst OC Disabled Alarm
30
50P-2D
1st Wdg 2 Phase Inst OC Disabled Alarm
Summary of Contents for TPU2000
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