14-4
IM 2560A-01EN
14.3 Standard Event Register
Standard Event Register Operation
The standard event register indicates eight types
of events that occur inside the instrument. When
one of the bits in this register becomes 1 (and the
corresponding bit of the standard event enable register
is also 1), bit 5 (ESB) in the status byte is set to 1.
Example
1. A query error occurs.
2. Bit 2 (QYE) is set to 1.
3. When bit 2 of the standard event enable register is 1,
bit 5 (ESB) in the status byte is set to 1.
You can also check what type of event occurred in the
2560A by reading the contents of the standard event
register.
Reading the Standard Event Register
You can use the
*ESR?
command to read the contents
of the standard event register. The register is cleared
after it is read.
Clearing the Standard Event Register
The standard event register is cleared in the following
three cases.
• When the contents of the standard event register
are read using the
*ESR
command.
• When a
*CLS
command is received.
• When the 2560A is restarted.
Standard Event Register
URQ
6
PON
7
5
4
3
2
1
0
CME EXE DDE QYE RQC OPC
• Bit 7 PON (Power ON)
This bit is set to 1 when the instrument is turned on.
• Bit 6 URQ (User Request)
Not used (always 0)
• Bit 5 CME (Command Error)
This bit is set to 1 when there is a command syntax
error.
Example
Command names are misspelled, or character
data that is not one of the available options has
been received.
• Bit 4 EXE (Execution Error)
This bit is set to 1 when the command syntax is
correct, but the command cannot be executed in the
current state.
Example
A command whose parameter is outside the
allowable range was received.
• Bit 3 DDE (Device Error)
This bit is set to 1 when a command cannot be
executed for internal reasons other than a command
syntax error or command execution error.
• Bit 2 QYE (Query Error)
This bit is set to 1 when a query command is
received, but the output queue is empty or the data
is lost.
Example
There is no response data, or data is lost due to
an overflow in the output queue.
• Bit 1 RQC (Request Control)
Not used (always 0)
• Bit 0 OPC (Operation Complete)
This bit is set to 1 upon the completion of the
operation designated by the
*OPC
command (see
chapter 13 for details).
Bit Masking
To mask a certain bit of the standard event register so
that it does not cause bit 5 (ESB) in the status byte to
change, set the corresponding bit of the standard event
enable register to 0.
For example, to mask bit 2 (QYE) so that ESB will not
be set to 1 even if a query error occurs, set bit 2 of
the standard event enable register to 0. Do this using
the
*ESE
command. To query whether each bit of the
standard event enable register is 1 or 0, use *ESE?.
For details on the *
ESE
command, see chapter 13.
