VeEX MPA, Руководство пользователя

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GUI System Tab
765
Chassis Clock
Options Description
Internal (No Output) The transmit signals derive their data's timing source from
the MPA system's Internal Stratum 3 clock source.
Chassis (Internal) option appears in the Transmit Clock
Reference menus, and CLK:INT displays in the Quick
LED Status area when selected.
There is no timing signal on the either clock output port.
Internal (CLK A 1.544
Mbps/CLK B 1.544
MHz Out) The transmit signals derive their data's timing source from
the MPA system's Internal Stratum 3 clock source.
Chassis (Internal) option appears in the Transmit Clock
Reference menus, and CLK:INT displays in the Quick
LED Status area when selected.
The RJ-48 CLK-A Out port is a 1.544 Mbps BITS
clock.
The SMA CLB-B Out port is a 1.544 MHz 75 ohm TTL
clock.
Internal (CLK A 2.048
Mbps/CLK B 2.048
MHz Out) The transmit signals derive their data's timing source from
the MPA system's Internal Stratum 3 clock source.
Chassis (Internal) option appears in the Transmit Clock
Reference menus, and CLK:INT displays in the Quick
LED Status area when selected.
The RJ-48 CLK-A Out port is a 2.048 Mbps SETS
clock.
The SMA CLB-B Out port is a 2.048 MHz 75 ohm TTL
clock.
Internal (CLK A No
Output/CLK B 10 MHz
Out) The transmit signals derive their data's timing source from
the MPA system's Internal Stratum 3 clock source.
Chassis (Internal) option appears in the Transmit Clock
Reference menus, and CLK:INT displays in the Quick
MPA_e_manual_D07-00-129P_RevA00