EMIF Registers
9-19
External Memory Interface
Table 9–7. TMS320C6211/C6711 SDRAM Extension Register Field Descriptions
Field
Description
TCL
Specified Cas latency of the SDRAM in ECLKOUT cycles
TCL = 0: CAS latency = 2 ECLKOUT cycles
TCL = 1: CAS latency = 3 ECLKOUT cycles
TRAS
Specifies tRAS value of the SDRAM in ECLKOUT cycles
TRAS = tRAS – 1
TRRD
Specifies tRRD value of the SDRAM in ECLKOUT cycles
TRRD = 0, then T
RRD
= 2 ECLKOUT cycles
TRRD = 1, then T
RRD
= 3 ECLKOUT cycles
TWR
Specifies tWR value of the SDRAM in ECLKOUT cycles
TWR = tWR – 1
THZP
Specifies tHZP value of the SDRAM in ECLKOUT cycles
THZP = tHZP – 1
RD2RD
Specifies number of cycles between READ to READ command (same CE space) of the
SDRAM in ECLKOUT cycles
RD2RD = 0: READ to READ = 1 ECLKOUT cycle
RD2RD = 1: READ to READ = 2 ECLKOUT cycle
RD2DEAC
Specifies number of cycles between READ to DEAC/DCAB of the SDRAM in ECLKOUT cycles
RD2DEAC = (# of cycles READ to DEAC/DCAB) – 1
RD2WR
Specifies number of cycles between READ to WRITE command of the SDRAM in ECLKOUT
cycles
RD2WR = (# of cycles READ to WRITE) – 1
R2WDQM
Specifies number of of cycles that BEx signals must be high preceding a WRITE interrupting
a READ
R2WDQM = (# of cycles BEx high) – 1
WR2WR
Specifies minimum number of cycles between WRITE to WRITE command of the SDRAM in
ECLKOUT cycles
WR2WR = (# of cycles WRITE to WRITE) – 1
WR2DEAC
Specifies minimum number of cycles between WRITE to DEAC/DCAB command of the
SDRAM in ECLKOUT cycles
WR2DEAC = (# of cycles WRITE to DEAC/DCAB) – 1
WR2RD
Specifies minimum number of cycles between WRITE to READ command of the SDRAM in
ECLKOUT cycles
WR2RD = (# of cycles WRITE to READ) – 1