Tektronix DM 5010, Инструкция по эксплуатации

Страница: 95 / 347

Theory of Operation —DM 5010
Counter U1235, set to binary zero by the CLR pulse at
the end of the measurement period, selects the least signifi­
cant bit of data (at the Eo input of U1125) to be output to the
data bus
via U1030A, U1030B, and the Miscellaneous buff­
er (diagram 9). As the processor beings its reading se­
quence, it reads this bit of data, and then generates an
ADVANCE pulse via the Address Decode circuitry (diagram
7) to increment the counter U1235. The next LSB of data
(Ej) is now selected by U1125 and is applied to the data
bus. The processor continues reading data and advancing
counter U1235 in this fashion until all 16 bits of data
selectable by U1125 have been read. The next ADVANCE
pulse generated by the processor causes a ripple-carry at
pin 15 of U1235, and U1320 changes state. U1030A is dis­
abled and the 17th bit of conversion data stored in the dis­
crete flip-flop (U1135C and K1030C) is passed on to the
data
bus via U1030D, U1030B and the Miscellaneous
buffer.
MICROPROCESSOR <$>
The Microprocessor is the control center for all instru­
ment operations. Operating under firmware control, the var­
ious types of data in the System are moved about and
manipulated by the microprocessor. By addressing (select­
ing) the various devices or memory locations in the proper
sequence (firmware control) and by properly manipulating
and transferring the data associated with these addresses,
each portion of the instrument performs its correct function
at the correct time.
The DM5010, as do all microprocessor systems, re­
quires a system clock. The 4 MHz crystal, Y1221, provides
a stable and accurate timing element for the
microprocessor ’s internal clock oscillator. All other critical
timing signals in the instrument are derived from the inter­
nally-divided 02 (1 MHz) clock.
The
VMA (Valid Memory Access) and R/W (read/write)
lines control the enabling of devices o n the data bus as well
as the flow of data on the bus. The IRQ line (interrupt re
quest) is used in conjunction with GPIB data transfers,
which are explained in the Handshake Process. The remain­
ing
processor control lines, with the exception of the
RESET, are not used. The function of the RESET line is
explained in the following description.
POWER-ON LOGIC <?>
The Power-On Logic holds the DM 5010 circuitry in a
reset condition for a short time after power up, or when a
momentary power supply fault occurs. This ensures that the
+ 5V supply has settled and that all instrument functions
begin from a known state.
As instrument power is turned on, the + 5V supply
comes up from 0 V to +5 V over some finite time period.
During most of this time, the inverting input of U1230B is
more positive than the noninverting input, keeping the out­
put, at pin 7 low, and thus the system reset (PON at pin 1 of
U1230A) at ground potential. As the supply voltage reaches
approximately +4.7 V, the noninverting input at pin 5 goes
more positive than the input at pin 6. As this occurs, the
output transistor of comparator U1230B (an open collector
device) is turned off.
Capacitor C1223 now charges 5 V through
R1227, As the voltage across C1223 charges beyond
+ 2.75 V, the inputs to comparator U1230A change relative
polarity and the system reset (PON) level at output pin 1
goes high. As previously mentioned, the time delay incorpo­
rated in this circuitry ensures that the +5 V supply has had
time to settle before any operation is attempted.
ADDRESS BUS BUFFER <7>
The Address Buffer stage consists of U1235 and
U1420A. This stage provides the increased current drive re­
quired to address the many devices on the Address Bus.
ADDRESS DECODE <j>
The Address Decode circuitry may be thought of as an
extension of the address bus. This stage looks at the six
most-significant bits of the address bus along with two
function-dependent signals produced by the microprocesor
to generate many of the required enable and control signals
for specific devices within the instrument.
A high VMA (Valid Memory Access) signal, as does its
inverted counterpart (low BVMA), indicates that the infor­
mation on the address bus is pointing to a valid memory
location. When these signals are present, decoders U1510,
U1520, and U1620 along with U1720A, U1720B, U1730A,
and U1730B in the logic state, generate the enable and con­
trol signals as shown in Table 4-4. The memory map shown
in Table 4-5 further illustrates address decoding. Those sig­
nals associated with U1620 are all
synchronized to the
microprocessor by the <t>2 clock.
ADD JAN 1982
4-21