Tektronix DM 5010, Инструкция по эксплуатации

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Theory of Operation—DM 5010
At the end of the measurement and override periods,
U1420C
generates a CLR2 pulse to reset trigger latch
U1530A and U1530B. This sets the IN PROGRESS line low
and tells the microprocessor that the A/D conversion is over
and valid data is available. It also sets the Data stage to
address the first bit (LSB) of data for transfer onto the Data
Bus.
During the time the data is read, the Control Logic auto­
matically initiates an Auto-Zero period after the end of over­
ride. Then U1420A clears the interval timer and Auto-Zero
intervals are counted.
At the end of the Auto-Zero period,
the Timing Logic generates an EDAZ (End Of Auto-Zero) to
U1425B. This enables further measurement sequences to
be initiated by the microprocessor TRIG line from the Ad­
dress Decode block.
As the next measurement cycle is initiated, U1420D
resets the contents of the data counter to zero, and U1420A
resets the Timing Logic's interval counter so measurement
intervals may be counted. The cycle repeats itself as often
as initiated by the microprocessor.
OPTO-ISOLATORS <5>
The opto-isolators couple digital control and data signals
between the Grounded and Isolated Sections of the
DM 5010 while maintaining electrical isolation between the
two. Each isolator consists of a light-emitting diode that is
turned either on or off by the drive circuitry, and a photo­
detector diode and buffer to sense and buffer the transmit­
ted signal. Each isolator buffer has an open collector output
and pullup resistors are required. Integrated circuits U1605
and U1613 are three-terminal regulators used to provide the
correct output levels for the various isolators. Transistor
Q1615 and R1615 set the ON current for U1510’s LED.
TIMING LOGIC <6>
The Timing Logic stage generates the time-dependent
signals for the A/D conversion process as well as the timing
signals to sync the Transformer Drive circuitry to the con­
version process (to minimize error caused by power supply
noise). The stage is essentially a series of counters and
some decoding logic that determines when certain phases
of the mode-dependent conversion process should be initi­
ated or have been completed.
Flip-flops U1535A and U1535B comprise a -?4 counter
that divides the 1 MHz microprocessor clock down to a
250 kHz rate. From there, the 250 kHz clock is divided by
18 to generate the intervals for the charge-balancing con­
version by U1730, U1630A, U1630B, U1320B, U1635B,
U1635C, and U1530B. Refer to the timing diagram in Fig.
4-12 for the following description.
Fig. 4-12. Timing of the divide by eighteen counter.
4-18
ADD JAN 1982