Sony HDCAM HDW-730, Руководство по обслуживанию

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1-70
HDW-750/750CE V1
Fig. 2 IN/OUT signal diagram of IC103 (APR-59 board)
15 19
0
0
19
0
CA
OUT
(16 bit)
A/D OUT
CH3&4 (20 bit)
A/D OUT
CH1&2 (20 bit)
REC DA
T
A
CH1&2 (20 bit)
REC DA
T
A
CH3&4 (20 bit)
REC DA
T
A
CH3&4 (16 bit)
PB DA
T
A
CH1&2 (20 bit)
PB DA
T
A
CH3&4 (20 bit)
PB DA
T
A
CH3&4 (16 bit)
CA
IN (16 bit)
D/A
IN CH3&4 (16 bit)
D/A
IN CH1&2 (16 bit)
CH3
CH4
CH2 CH4 CH4
CH1 CH3 CH3
CH2 CH4 CH4
CH3 CH1
(Right Justified, 16 bit Data) (Left Justified, 20 bit Data)
MSB MSB
15 19
0
0
MSB MSB
MSB
19
0
MSB
MSB
Z
0
1
9
V U C P
Z
MSB
Z
0
1
9
V U C P
Z
MSB
Z
0
1
5
V U C P
Z
CH4 CH4 CH2
MSB
ZMJ
0
1
9
VUCPZMJ
MSB
ZMJ
0
1
9
VUCPZMJ
CH4
MSB
MSB
ZMJ
0
1
5
0
15
MSB
0
15
MSB
0
15
MSB
0
15
MSB
0
15
MSB
0
15
VUCPZMJ
MSB
0
1
9
VUCP
MSB
0
1
9
VUCP
MSB
0
1
5
VUCP
CH2
CH3 CH3 CH1
MSB
0
1
9
VUCP
MSB
0
1
9
VUCP
MSB
0
1
5
VUCP
CH3 CH3 CH1
Fs
64Fs
AP5
AD2 AD1 ENC12 ENC34 CNF12 CNF34 DA2 DA1
(CNF Max Delay:2045
*
Fs)
(ENC Max Delay:6135
*
Fs)
1-26. Circuit Description
1-26-4. Audio System