Processor Technology Sol-PC, Руководство пользователя

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PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION SECTION VIII
set to the outputs of latches U2 and 13. U2 latches the starting row
address from DIO0-3 and U13 latches the data on DIO4-7, with
!PORT_OUT_FE being the strobe. Data on DIO4-7 specifies where the
first line will be displayed. Thus, the number loaded into U1 is
the address of the first displayable scan line, and the number loaded
into U22 defines the character row (0 through 15).
U11 is preset by !VDISP from pin 9 of J-!K flip-flop U43. This
means U11 is forced to its preset condition from the end of the dis-
played text to the top of the next character row. During this time,
pin 6 of another U43 J-!K flip-flop is set high to preset U1. If U11
is preset to 0, its TC output on pin 7 is low and pin 6 of U43 is re-
set to a low. This allows U1 to count with each horizontal scan line.
If U11 is preset to any number other than 0, pin 6 of U43 can-
not be reset low until U11 reaches zero. Assume U11 is preset to
two. It must count down two character rows before U1 starts count-
ing. During this time, pin 7 of U43 (PRE_BLANK) is low, and as pre-
viously discussed, the display is blanked.
We can now see that the PRE_BLANK time, often called "window
shade", is variable with the number loaded into U11. Therefore,
scrolling is performed by changing the numbers in U2 and U13 without
the need to reposition the text within the Display RAM.
The remaining circuit in the Display Section consists of
transistor Q2, one section of U87, 89 and 102. U88 and U102 are con-
nected as a one-shot 250 msec timer that is triggered when
!PORT_OUT_FE goes active (pin 1 of inverter U87 goes high). Thus,
when data is loaded into U2 and U13, this timer starts. Tri-state
driver U89, which is enabled by !PORT_IN_FE, transmits the state of
this timer to D100 on the Bidirectional Data Bus. The CPU can conse-
quently test the timer status by looking for a high on DIO0. This
timing allows a 250 msec scroll rate without the need for complex
timing routines in the CPU. Q2, R102 and C37 serve to speed up timer
reset.
8.5.5 Audio Tape I/O
Refer to Audio Tape I/O Schematic in Section X, Page X-19.
Timing for the Audio Tape I/O is derived from the 1200, 2400,
4800, 19,200 and 38,400 Hz signals received from the Baud Rate Gener-
ator in the Input/Output section of Sol. The first two are used by
the write data synchronizer (U100) and the digital-to-audio converter
(U101).
The remaining three signals are fed to two sections of U111,
a quad multiplexer or select gate. All four sections of U111 are
used to select clocks for low speed or high speed operation according
to the select inputs, pins 9 (A) and 14 (B). The states of these two
select inputs must be complementary to each other in order to select
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