Processor Technology Sol-PC, Руководство пользователя

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PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION SECTION VIII
an eight-line parallel output port, an eight-line sense switch logic
input port, and a unidirectional eight-line internal data bus.
The use of a unidirectional (input) data bus accommodates
Sol's internal low-drive memory and I/O devices that do not meet the
heavy drive requirement of the bidirectional data bus. The low-drive
requirement of the internal bus also allows using the tri-state cap-
abilities of the UART's (Universal Asynchronous Receiver/Transmitter)
in the serial and audio cassette I/O circuits without additional
drivers.
All CPU data and address lines are buffered through tri-state
drivers to support a larger array of memory and I/O devices than
would otherwise be possible with the 8080 output drive capability.
Data input to the CPU is selected by a four-input multiplexer from
the Keyboard Port, Parallel Port, Bidirectional Data Bus and Internal
Data Bus. The Internal Data Bus is the source of all data input to
the CPU from Sol's internal memory, the serial interface and the
cassette interface. The Bidirectional Data Bus is the source of all
data fed to memory and I/O, both internal and external. It is also
the source of data input to the CPU from eight internal sense switch-
es as well as from external memory and I/O.
8.3 BLOCK DIAGRAM ANALYSIS, Sol-PC
8.3.1 Functional Elements And Their Relationships
As can be seen in the Sol block diagram on Page X-24 in Sec-
tion X, timing signals for Sol are derived from a crystal controlled
oscillator that produces a "dot clock" frequency of 14.31818 MHz.
(This frequency, four times that of the NTSC color burst, provides
compatibility with color graphics devices.) The dot clock is applied
directly to the Video Display Generator circuit and divided in the
Clock Generator to provide
φ
1,
φ
2 and CLOCK. CLOCK synchronizes all
control inputs to the 8O8O;
φ
1 and
φ
2 are the nonoverlapping, two
phase clocks required by the 8O8O.
Memory internal to the Sol is divided between 2K of ROM (Read
Only Memory), 1K of System RAM (Random Access Read/Write Memory) and
1K of Display RAM. The ROM permanently stores the instructions that
direct the CPU's activities. (To enhance Sol's versatility, this
particular memory is on a plug-in "personality module". Thus, Sol
can be easily optimized for a particular application by plugging in a
personality module that contains a software control program designed
for the task. The CONSOL and SOLOS programs, which are described in
Section IX, are examples of such personality modules.) Display RAM
stores data for display on a video monitor, and the System RAM pro-
vides temporary storage for programs and data. All memories are ad-
dressed on the Address Bus (ADR0-15) and, except for the Display RAM,
input data to the CPU on the Internal Data Bus (INT0-7). Data entry
into both RAM's is done on the Bidirectional Data Bus (DIO0-7).
VIII-3