Processor Technology Sol-PC, Руководство пользователя

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PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION SECTION VIII
Unregulated -16 and +16 V dc, at 1 amp, from the filtered
outputs of FWB2 are made available on terminals X6 and X5. These are
not used in the Sol-10, but they are supplied to the backplane board
in the Sol-20 to drive S-100 Bus modules.
In the case of the Sol-20, the power transformer (T2) has an
additional 8-volt secondary winding and a third bridge rectifier
(FWB3) to 8 V dc at 8 amps. The output of FWB3 is filtered
by C9 and controlled by bleeder resistor R13. Again, this voltage is
supplied to the backplane board in the Sol-20.
Sol-20 also includes a cooling fan powered by the AC line
voltage.
8.5 Sol-PC CIRCUIT DESCRIPTIONS
8.5.1 CPU and Bus
Refer to the CPU and Bus Schematic in Section X, Page X-15.
A crystal, two inverter sections in U92 and four D flip-flops
(U90) and associated logic make up the Clock Generator.
The two U92 sections function as a free-running oscillator
that runs at the crystal frequency of 14.31818 MHz. R133 and R134
drive these two sections of U92 into their linear regions, and C61
and 64 provide the required feedback loop through the crystal. U77,
a permanently enabled tri-state non-inverting buffer/amplifier, fur-
nishes a high drive capability.
This fundamental clock frequency is fed directly to the Video
Display Generator and to the clock inputs of U90. U90 is a four-
stage register connected as a ring counter that is reset to zero when
power is applied to the Sol. This reset is accomplished with D8,
R104 and C39.
The bits contained in the ring counter shift one to the right
with every positive-going clock transition, but the output of the
last stage is inverted or "flipped" before being fed back to the input
In a simple four-stage "flip-tail" ring counter, the contents would
progress from left to right as follows: 1000, 1100, 1110, 1111, 0111,
0011, 0001, 0000--on the first through eighth clocks respectively.
The hypothetical counter would go through eight states, dividing the
clock by eight.
The Sol counter, however, is a modified flip-tail ring coun-
ter that can be configured to divide by one of three divisors--5, 6
or 7. This is made possible by using a two-input NAND gate (U91) in
the feedback path and three jumper options (no jumper, D-to-C and
D-to-E) to alter the feedback path. Let's see how it works.
VIII-8