Processor Technology Sol-PC, Руководство пользователя

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PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION SECTION VIII
Generator ROM automatically outputs all zeros for these two character
positions. After the last scan line in the third character row, the
Scan Counter is reset to a count of 15 to start the fourth character
row.
The Character Generator ROM output is converted from parallel
to serial form in an 8-bit shift register (U41) that is clocked by
DOT_CLOCK. For each high bit on the input, the serial output (QH,
pin 13) of U41 is high for one DOT_CLOCK period. For each low bit,
QH is low for one DOT_CLOCK period. Note that parallel input bit PH
(pin 14) is tied to ground. This effectively adds a low bit (or dot)
following the data and provides one of the spacer dots between
characters. The second spacer dot is generated by connecting the
serial input (pin 1) to ground and applying LOAD_CLOCK to the load
(LD, pin 15) input to U41. When LOAD_CLOCK goes low, which it does
every ninth DOT_CLOCK, U41 shifts in one zero.
A blink oscillator (two inverter sections in U88), a latch
(one section in U42) and their associated components comprise the
cursor circuit. The blink oscillator runs continuously at a rate set
by R84 and C36. Its output has a nominal 0.5 sec period. If the
blink option is selected with S1-5, the blink signal is applied to
one input of a gate in U60. The other input to this gate is provided
by the blink latch, one section in U41. If the cursor bit QA out of
Data Latch U26 is high, D flip-flop U42 sets for the time the ROM is
active on the character and remains set during the period when video
data is shifted out of U41. The output of U42 is gated high through
NAND gate U60 when BLINK (pin 6 of U88) is low. BLINK is held low
when the blink option is not selected. The output of U60 is in turn
gated with the video output of U41 in U74, an exclusive OR gate. U74
thus inverts the video if the output of U60 is high, and no inversion
takes place if the output of U60 is low.
The video signal including the cursor, is gated to pin 9 of
another U74 exclusive OR gate in the absence of any blanking signals
at the other two inputs to NOR gate U59. If S1-4 is open, U74 in-
verts the video signal to produce a reverse (black on white) display.
Raw video on pin 8 of U74 is supplied to pin 15 of J4. Video out on
pin 6 of inverter U87 is combined with COMP_SYNC on pin 8 of another
U87 inverter in a resistive mixer, R80-R82, to meet EIA composite
video signal standards, and coupled to P1 for use by a video monitor.
This mixer has a 61-ohm output impedance.
Both Beginning Address Counter U1 and First Screen Position
Counter U11 are enabled to advance their counts when pin 9 of J-!K
flip-flop U75 is low, which it is for about 600 nsec following
!OVERFLOW_LINE; that is, after the Scan Counter (U40) is loaded. This,
of course, occurs at the end of every scan line in the character row.
The scroll circuit consists of U1, U11, Scoll Control Latch
U2 and Screen Position Control Latch Ul3 and their associated cir-
cuitry. U1 and U11 are up and down counters respectively that are pre-
VIII-32