Processor Technology Sol-PC, Руководство пользователя

Страница: 159 / 284

PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION SECTION VIII
PXDR on pin 16 of J2 is supplied by the external device. It
indicates the device is ready to receive data. !PXDR is buffered to
INT2 and will effect the transfer of data to the Internal Data Bus
during the status input to the CPU. !PXDR is analogous to the pre-
viously discussed PIAK signal.
Sense Switches S2-1 through 8 are driven by !PORT_IN_FF when
it is low. Thus, the DIO lines connected to closed switches are
driven low, and those connected to open switches are pulled high.
U97 (a 4-bit D-type register) and one section of U52 (a J-!K
flip-flop connected as a D flip-flop) latch five bits of data on
D103-7 when !PORT_OUT_FA goes active. These bits, which supply the
indicated outputs, control conditions in both the PP and CDI. With
respect to the PP, PIE enables parallel input, and PUS selects the
parallel device for the transfer. The data in these two latches re-
mains until either a new word is read out or POC goes active.
Also during !PORT_OUT_FA, the keyboard flag is reported.
!KEYBOARD_DATA_READY on pin 3 of J3 is a low going pulse 1 to 10 usec
in duration. It is applied to pin 13 of J-!K flip-flop U70. Some
time after pin 13 of U70 goes low, but before 500 nsec, U70 is set
by
φ
2 and pin 10 goes low. This low is buffered through U71 to INT0
to indicate the keyboard is ready to send data. Reset of U70 occurs
with a POC or by !PORT_IN_FC. The latter occurs when data is accepted
from the keyboard.
The other half of flip-flop U52, with its output on pin 6,
latches one bit of status, D104, when !PORT_OUT_F8 is active. Its
output is applied to pin 5 of one operational amplifier section in
U56 to become the SRTS (request to send) signal on pin 4 of J1, the
SDI connector.
The SDI/UART centers around a UART, U51. The UART transmis-
sion conditions (parity, word length and stop bits) are determined by
the settings of S4-1 through 5. (Refer to Paragraphs 7.5.8 through
7.5.10 in Section VII for descriptions of the switch settings and
their effect on transmission.
Data destined to leave Sol through the SDI/UART enters the
UART on its TI1-6 inputs from the Bidirectional Data Bus when TBRL
(pin 23) is low; that is, when !PORT_OUT_F9 goes active. Circuitry
within the UART serializes the input data, which is in parallel form,
and outputs it on pin 25 at a rate determined by the clock on pin 40.
The binary states at pin 25 are low for a zero and high for a one.
Assuming Sol is not in local operation ("off line"), the output on
pin 25 of the UART is applied to pins 2 and 11 of J1 via two gates in
U55 and the other half of U56.
VIII-19