Processor Technology Sol-PC, Руководство пользователя

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PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION SECTION VIII
Normally the internal display address is multiplexed to the
Display RAM. When the CPU or a DMA device requests access (!PAGE_CC
active), the multiplexers switch to the external address lines,
ADR0-9.
Seven-bit ASCII-coded data is written into RAM chips U14
through U20 from bits DIO0-6 of the Bidirectional Data Bus, and the
cursor bit (DIO7) is written into RAM chip U21. This writing occurs
when the write enable (WE) input to the RAM chips is low. This oc-
curs when the Display RAM is addressed (!PAGE_CC active low) and
MWRITE on S-100 Bus pin 68 is high. The enable is supplied on out-
put pin 8 of NAND gate U44. Data is read out of the Display RAM
when pin 8 of U44 is high. Data out of the Display RAM is placed on
the Bidirectional Data Bus via tri-state drivers U29 and U89 when
!PAGE_CC and PDBIN (S-100 Bus pin 78) are active. U29 and U89 are
enabled by a low output on pin 11 of another U44 NAND gate.
Data out of the Display RAM is also strobed into Data
Latches U26 and U27 by LOAD_CLOCK. Seven outputs from these latches
are used to address the Character Generator ROM, U25. Note that the
output from RAM chip U19 is inverted in exclusive OR gate U74 before
being applied to the C input (pin 13) of U26, and the complement
(pin 14) of the QC output of U26 is used in addressing U25. This is
done so that the Data latches will output the space code (0100000)
to the Character Generator ROM when the latches are reset. These
latches are reset each time !PAGE_CC is active by way of U75, a J-!K
flip-flop connected as a D flip-flop, and D flip-flop U42 (Q output
pin 6). By outputting the space code on reset, the Data Latches
insure a blank character position on the screen.
The Character Generator ROM, U25, has seven character ad-
dress inputs (A1 through A7), four scan line inputs (RS1 through
RS4) and seven data outputs (B1 through B7). It is programmed to
generate seven bits (dots) of character information for the selected
scan line of the character row. U25 also automatically blanks scan
lines that are not a part of the character and shifts the g, j, p,
q, y, comma and semicolon to the fifth through 13th scan lines in
the dot matrix (refer to Figures 8-2 and 8-3 on Page VIII-24). Com-
plete patterns for the 6574 and 6575 Character Generator ROM's are
provided in Figures 8-5 and 8-6 respectively. Note that the address
bits A0 through A6 in Figures 8-4 and 8-5 correspond to the A1
through A7 inputs to U25 on the schematic, scan lines R0 through R8
are specified by the RS1 through RS4 inputs to U25 on the schematic,
and the data output bits D0 through D6 correspond to the B1 through
B7 outputs from U25 on the schematic.
Let's see how the Character Generator ROM produces a charac-
ter using an uppercase "C" and "T" as an example. In this example,
these two characters are to be displayed in the first and second
character positions respectively on the third character row of the
display screen. Remember that the character position and row param-
eters are contained in the Display RAM since the 7-bit ASCII-coded
VIII-29