![background image](http://html1.mh-extra.com/html/omron/srm1-programing-02-2001/srm1-programing-02-2001_programming-manual_742414110.webp)
2-3
Section
CPM1/CPM1A Interrupt Functions
89
(1)
(2)
(3)
(4)
(5)
Phase-Z
25200
CPU processing
1 cycle
Not reset
Not reset
Not reset
Reset
Reset
I/O refresh
Program
execution
Program
execution
Program
execution
Program
execution
Program
execution
Program
execution
Common processing,
communications servicing, etc.
Phase-Z Software Reset
No.
Operation timing
Reset
(1)
Phase-Z signal turns ON when
SR 25200 turns OFF.
Not reset.
(2)
Phase-Z signal turns ON within one
cycle after SR 25200 turns ON.
Not reset.
(3)
Phase-Z signal turns ON after at least
one cycle elapses after SR 25200
turns ON.
Reset with phase-Z leading edge.
(4)
Phase-Z signal turns ON within one
cycle after SR 25200 turns OFF.
Reset with phase-Z leading edge.
(5)
SR 25200 turns ON when phase-Z
signal is ON.
Not reset.
Note
The High-speed Counter Reset Bit (SR 25200) is refreshed once every cycle, so
in order for it to be read reliably it must be ON for at least one cycle.
The “Z” in “phase-Z” is an abbreviation for “Zero.” It is a signal that shows that the
encoder has completed one cycle.
High-speed Counter Interrupt Count
For high-speed counter 0 interrupts, a comparison table is used instead of a
“count up.” The count check can be carried out by either of the two methods de-
scribed below. In the comparison table, comparison conditions (for comparing to
the PV) and interrupt routine combinations are saved.
Target value:
A maximum of 16 comparison conditions (target values and count direc-
tions) and interrupt routine combinations are saved in the comparison table.
When the counter PV and the count direction match the comparison condi-
tions, then the specified interrupt routine is executed.
Range (zone) comparison:
Eight comparison conditions (upper and lower limits) and interrupt routine
combinations are saved in the comparison table. When the PV is greater
than or equal to the lower limit and less than or equal to the upper limit, then
the specified interrupt routine is executed.
Содержание SRM1 - PROGRAMING 02-2001
Страница 1: ...Programmable Controllers Cat No W353 E1 06 SYSMAC CPM1 CPM1A CPM2A CPM2C SRM1 V2 PROGRAMMING MANUAL ...
Страница 2: ...CPM1 CPM1A CPM2A CPM2C SRM1 V2 Programmable Controllers Programming Manual Revised February 2008 ...
Страница 3: ...iv ...
Страница 5: ...vi ...
Страница 9: ...x ...
Страница 15: ...xvi ...