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MSCM_CP0CFGn field descriptions
Field Description
31–24
ICSZ
Level 1 Instruction Cache Size
This read-only field provides an encoded value of the Instruction Cache size. The capacity of the memory
is expressed as Size [bytes] = 2
(8+SZ)
, where SZ is non-zero; a SZ = 0 indicates the memory is not
present.
23–16
ICWY
Level 1 Instruction Cache Ways
This read-only field provides the number of cache ways for the Instruction Cache.
15–8
DCSZ
Level 1 Data Cache Size
This read-only field provides an encoded value of the Data Cache size. The capacity of the memory is
expressed as Size [bytes] = 2
(8+SZ)
,where SZ is non-zero; a SZ = 0 indicates the memory is not present.
DCWY Level 1 Data Cache Ways
This read-only field provides the number of cache ways for the Data Cache.
34.4.12 On-Chip Memory Descriptor Register (MSCM_OCMDRn)
This section of the programming model is an array of 32-bit generic on-chip memory
descriptor registers that provide static information about the attached memories, as well
as configurable controls (where appropriate).
• Privileged 32-bit reads from a processor core or the debugger return the appropriate
processor information.
• Reads from any other bus master return all zeroes.
• Privileged writes from a processor core or the debugger to writeable registers update
the appropriate fields.
• Privileged writes from other bus masters are ignored.
• Attempted user mode accesses or any access with a size other than 32 bits are
terminated with an error.
Chapter 34 Miscellaneous System Control Module (MSCM)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 887