NXP Semiconductors K32 L2A Series, Справочное руководство, Страница: 789 / 1379

the FRAMESZ configuration is reached, or at the end of a word when a new transmit
command word is at the top of the transmit/command FIFO. The HREQ input is only
checked the next time the LPSPI goes idle (completes the current transfer and transmit/
command register is empty).
The transmit/command FIFO also supports a Circular FIFO feature. This allows the
LPSPI master to (periodically) repeat a short data transfer that can fit within the transmit/
command FIFO, without requiring additional FIFO accesses. When the circular FIFO is
enabled, the current state of the FIFO read pointer is saved and the status flags do not
update. Once the transmit/command FIFO is considered empty and the LPSPI is idle, the
FIFO read pointer is restored with the saved version, so the contents of the transmit/
command FIFO are not permanently pulled from the FIFO while circular FIFO mode is
enabled.
29.3.2.2 Receive FIFO and Data Match
The receive FIFO is used to store receive data during SPI bus transfers. When RXMSK is
set, receive data is discarded instead of storing in the receive FIFO.
Receive data supports a receive data match function that can match received data against
one of two words or against a masked data word. The data match function can also be
configured to compare only the first one or two received data words since the start of the
frame. Receive data that is already discarded due to RXMSK bit cannot cause the data
match to set and will delay the match on first received data word until after all discarded
data is received. The receiver match function can also be configured to discard all receive
data until a data match is detected, using the MCFGR0[RDMO] control bit. When
clearing the MCFGR0[RDMO] control bit following a data match, clear
MCFGR0[RDMO] before clearing MSR[DMF] to allow all subsequent data to be
received.
29.3.2.3 Timing Parameters
The following table lists the timing parameters that are used for all SPI bus transfers,
these timing parameters are relative to the LPSPI functional clock divided by the
PRESCALE configuration. Although the Clock Configuration Register cannot be
changed when the LPSPI is busy, the PRESCALE configuration can be altered between
transfers using the command register, to support interfacing to different slave devices at
different frequencies.
Chapter 29 Low Power Serial Peripheral Interface (LPSPI)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 789