NXP Semiconductors K32 L2A Series, Справочное руководство, Страница: 1367 / 1379

before the MCU enters low power mode. Otherwise, the MCU
may not be waken up from low power mode.
54.3.2.3 Example code: Reconfiguring the Watchdog
The following code segment shows an example reconfiguration of the WDOG module.
The unlock command access size is 32-bit.
/* Initialize watchdog with ~1-kHz clock source, ~1s time-out */
DisableInterrupts; // disable global interrupt
WDOG_CNT = 0xD928C520; // unlock word
WDOG_TOVAL = 1000; // setting timeout value
WDOG_CS = WDOG_CS_CLK_MASK; // setting 1-kHz clock source
WDOG_CS = WDOG_CS_EN_MASK; // enable counter running
EnableInterrupts; // enable global interrupt
54.3.3 Clock source
The watchdog counter has the following clock source options selected by programming
CS[CLK]:
• bus clock
• internal Low-Power Oscillator clock (LPO_CLK) (This is the default source.)
• internal 8 MHz clock (SIRC)
• external clock (SOSC)
The options allow software to select a clock source independent of the bus clock for
applications that need to meet more robust safety requirements. Using a clock source
other than the bus clock ensures that the watchdog counter continues to run if the bus
clock is somehow halted; see
Backup reset .
An optional fixed prescaler for all clock sources allows for longer timeout periods. When
CS[PRES] is set, the clock source is prescaled by 256 before clocking the watchdog
counter.
The following table summarizes the different watchdog timeout periods available.
Chapter 54 Watchdog timer (WDOG32)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1367