NXP Semiconductors K32 L2A Series, Справочное руководство, Страница: 109 / 1379

5.3 SCG Output Clocks
The SCG has several output clock trees. All of the four clock sources, SOSC, SIRC,
FIRC and SPLL each can feed these output clock trees with optional dividers.
5.3.1 DIVCORE_CLK
The main system clock that feeds the CPU, DMA, tightly coupled memories and platform
is provided via a divider called DIVCORE. The SCG can select one of the four clock
sources to feed DIVCORE. This is generally the fastest clock in the system but can also
run slower than peripheral timing clocks.
5.3.2 DIVSLOW_CLK
The DIVSLOW clock is used as the main “peripheral interface” clock and is referenced
by the CPU and the DMA when accessing the peripheral registers.
The DIVSLOW_CLK is also used to clock the flash memory module. This clock is fed
directly from DIVCORE clock, and has optional dividers to ensure the frequency of this
clock is <25MHZ, for reliable flash operation.
NOTE
Throughout this manual, DIVSLOW_CLK may also be referred
to as the bus clock.
5.3.3 Peripheral functional clocks
The SCG provides additional output clock trees that are used as the “peripheral
functional” clocks. Peripheral functional clocks are used as the fundamental “timing” of
the peripheral, providing asynchronous clocking from the CPU main clock. For example
the peripheral functional clock for a timer will clock the reference counter that is used for
all timings, and for a serial communications peripherals will source the baud rate for the
external communication.
This allows peripherals to operate either slower or faster than the CPU platform.
Each of the four clock sources can provide three additional output clocks that are
generally used as alternative peripheral functional clocks. This provides flexible clocking
in a SoC, and allows groups of peripherals to be clocked by one specific functional clock,
Chapter 5 Clock Distribution
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 109