NXP Semiconductors K32 L2A Series, Справочное руководство, Страница: 524 / 1379

The transmit FIFO can be flushed by setting the FLSH_TX bit in the CTRL register. A
transmit NACK threshold error (TNTE) will halt the transmitter, and flush the transmit
FIFO. The flush operation resets the transmit read and write pointers to equal values.
Everything in the transmitter block is reset by the transmit flush operation. This does not
include the control registers associated with the transmitter. The Transmit data threshold
flag (TDTF) does not get cleared by the FLSH_TX operation.
21.6.6.2 Receive FIFO
A 4-byte deep FIFO is implemented in the receiver. Since more than 4-bytes can be
received in the FIFO, the software must ensure that the Rx FIFO is periodically read. The
Rx FIFO can be read by software via normal CPU accesses on interrupt (RX_DATA
interrupt flag) or via DMA by setting the DMA_RX_EN bit in CTRL register. The
software cannot write to this register. A write access may terminate in a transfer error.
The Rx FIFO is loaded by the receiver when it receives an error free message byte with
correct parity. The FIFO stores the message byte only. When the total bytes in the Rx
FIFO equals the programmed threshold value (RDT[3:0] in RX_THD register), the
RDTF bit is asserted in the RX_STATUS register. An interrupt will be asserted if the
RDT_IM bit in the INT_MASK is cleared. If DMA access to RX_FIFO is enabled, the
DMA request to read the Rx FIFO will be asserted when the threshold flag is set and will
clear when all the bytes are read out from the Rx FIFO.
The receive FIFO can be flushed by setting the FLSH_RX bit in the CTRL register. The
flush operation resets the receiver except for receiver control registers.
NOTE
Since the register bits and the receiver logic are in different
clock domains, the software needs to make sure to allow clock
synchronization time when sampling the RDTF bit. One
proposed method could be to read one byte at a time (from Rx
FIFO) when RDTF is asserted, allow a time of 3 bus clock
cycles after Rx FIFO read and then check the status of the
RDTF bit and repeat as necessary. Alternatively, one could set
the receiver threshold one more than actually needed.
Rx FIFO Overflow Detection: When a byte is received by the receiver and the Rx FIFO
is not read and already contains 4 bytes, a FIFO overflow error will be asserted (RFO bit
set to 1 in RX_STATUS register). The received byte will be discarded leaving the FIFO
with the first 4 bytes received. If the ONACK bit in the CTRL register is asserted, the
Functional Description
K32 L2A Reference Manual, Rev. 2, 01/2020
524 NXP Semiconductors