NXP Semiconductors K32 L2A Series, Справочное руководство, Страница: 502 / 1379

EMVSIMx_TX_STATUS field descriptions (continued)
Field Description
0 FIFO is emtpy
>0 Total bytes in FIFO
21–18
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
17–16
TX_RPTR
Transmit FIFO Read Pointer
Value of the read pointer of transmit FIFO.
15–10
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9
GPCNT1_TO
General Purpose Counter 1 Timeout Flag
Used to indicate when the General Purpose Counter 1 has reached the GPCNT1_VAL value in the
GPCNT_VAL register.
0 GPCNT1_VAL time not reached, or bit has been cleared. (default)
1 General Purpose counter has reached the GPCNT1_VAL value
8
GPCNT0_TO
General Purpose Counter 0 Timeout Flag
Used to indicate when the General Purpose Counter 0 has reached the GPCNT0_VAL value in the
GPCNT_VAL register.
0 GPCNT0_VAL time not reached, or bit has been cleared. (default)
1 General Purpose counter has reached the GPCNT0_VAL value
7
TDTF
Transmit Data Threshold Flag
Interrupt flag asserted when total bytes in the Transmit FIFO is less than or equal to the programmed
transmit data threshold TDT[3:0]. The TDTF flag will be set any time the number of bytes in the transmit
FIFO is less than or equal to the value set by TDT[3:0]. The flag can be cleared by writing enough bytes
into the transmit FIFO so as to take the number of bytes in the FIFO above the TDT[3:0] level. Another
way to clear the flag is to set the TDT[3:0] level lower than the number of bytes currently in the FIFO.
The TDTF flag will create an interrupt if the TDT_IM bit in the INT_MASK register is cleared.
0 Number of bytes in FIFO is greater than TDT[3:0], or bit has been cleared
1 Number of bytes in FIFO is less than or equal to TDT[3:0] (default)
6
TFF
Transmit FIFO Full Flag
Used to indicate when the Transmit FIFO has been written with maximum number of bytes that it can
store. Subsequent writes may get ignored. The TFF bit can only be cleared by writing 1 to this bit or
setting the FLUSH_XMT or SOFT_RESET bit in the RESET_CNTL register.
0 Transmit FIFO Full condition has not occurred (default)
1 A Transmit FIFO Full condition has occurred
5
TCF
Transmit Complete Flag
Used to indicate whether the EMV SIM transmitter is ready for a new transmission. The TC flag becomes
set when the guard time has expired after the last byte in the transmit FIFO (if XMT_CRC_LRC = 0) or the
LRC or CRC byte (if XMT_CRC_LRC bit = 1) has been transmitted. The TC flag will create an interrupt if
TC_IM in the INT_MASK register is low. The TC bit is a write-one-to-clear bit.
0 Transmit pending or in progress
1 Transmit complete (default)
Table continues on the next page...
Memory Map and Registers
K32 L2A Reference Manual, Rev. 2, 01/2020
502 NXP Semiconductors