NXP Semiconductors K32 L2A Series, Справочное руководство, Страница: 231 / 1379

The generic BME2 definition supports a 1024 KB address space based at
0x4000_0000.... . The decorated address space is mapped to the 448 MB region located at
0x4400_0000–0x5FFF_FFFF.
13.3 Functional description
Information found here details the specific functions supported by the BME.
Recall the combination of the basic load and store instructions of the Cortex-M
instruction set architecture (v6M, v7M) plus the concept of decorated storage provided by
the BME provides a robust and efficient read-modify-write capability. The resulting
architectural capability defined by this core platform function is targeted at the
manipulation of n-bit fields in peripheral registers and RAM and is consistent with I/O
hardware addressing in the Embedded C standard. For most BME commands, a single
core read or write bus cycle is converted into an atomic read-modify-write, that is, an
indivisible "read followed by a write" bus sequence.
Consider decorated store operations first, then decorated loads.
13.3.1 BME decorated stores
The functions supported by the BME's decorated stores include three logical operators
(AND, OR, XOR) plus a bit field insert.
For all these operations, BME converts a single decorated AHB store transaction into a 2-
cycle atomic read-modify-write sequence, where the combined read-modify operation is
performed in the first AHB data phase, and then the write is performed in the second
AHB data phase.
A generic timing diagram of a decorated store showing a peripheral bit field insert
operation is shown as follows:
Chapter 13 Bit Manipulation Engine2 (BME2)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 231