NXP Semiconductors K32 L2A Series, Справочное руководство, Страница: 859 / 1379

MMDVSQx_CSR field descriptions (continued)
Field Description
0 Reads of the RES register return the register contents
1 If CSR[DZ] = 1, an attempted read of RES register is error terminated to signal a divide-by-zero, else
the register contents are returned
2
REM
REMainder calculation
This indicator selects whether the quotient or the remainder is returned in the RES register. The combined
CSR[REM] and CSR[USGN] bits define four possible divide operations:
• If CSR[REM, USGN] = 0b00, perform a signed divide, returning the quotient
• If CSR[REM, USGN] = 0b01, perform an unsigned divide, returning the quotient
• If CSR[REM, USGN] = 0b10, perform a signed divide, returning the remainder
• If CSR[REM, USGN] = 0b11, perform an unsigned divide, returning the remainder
0 Return the quotient in the RES for the divide calculation
1 Return the remainder in the RES for the divide calculation
1
USGN
Unsigned calculation
This indicator selects whether a signed (default) or unsigned divide is performed. See the CSR[REM]
description for the encoding of the four possible divide operations.
0 Perform a signed divide
1 Perform an unsigned divide
0
SRT
Start
When written with a logical one and CSR[DFS] = 1, this flag initiates a divide operation. If written as a
logical one with CSR[DFS] = 0, it is ignored. This bit always reads as a zero. The state of the register write
data defines this bit’s function.
0 No operation initiated
1 If CSR[DFS] = 1, then initiate a divide calculation, else ignore
Chapter 32 Memory-Mapped Divide and Square Root (MMDVSQ)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 859