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48.1.3.2 Register interface (IP Slave bus)
The TRNG's register interface (32-bit IP bus) is used to read and write registers within
TRNG for the following purposes:
Table 48-2. Summary of register interface uses
Purpose For more information, see
During chip initialization time
To configure TRNG including initialization of the
• Registers
• TRNG Register Interface
During hardware and software debugging
Read status registers • RNG TRNG Status Register
•
NOTE
Accesses to registers must use full-word (32-bit) reads or
writes.
48.1.3.3 TRNG0 Register Descriptions
All accesses of undefined addresses always return zero and assert IPS transfer error.
Writes to undefined and read-only addresses are ignored. Undefined addresses are those
undocumented, protected or reserved addresses within and outside the range of the
addresses defined in the memory map below. Although many of the TRNG0 registers
hold more than 32 bits, the register addresses shown in the Memory Map below represent
how these registers are accessed over the register bus as 32-bit words.
The format and fields in each TRNG0 register are defined below. Some of the register
format figures apply to several different registers. In such cases a different register name
will be associated with each of the register offset addresses that appear at the top of the
register format figure. Although these registers share the same format, they are
independent registers. In addition, many registers can be accessed at multiple addresses.
In these cases there will be a single register name and the list of addresses at which that
register is accessible will be indicated as aliases. Unless noted in the individual register
descriptions, registers are reset only at Power-On Reset (POR).
Chapter 48 SA-TRNG Standalone
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1215