Chapter 3 -Appendix D – GTXI Buffer Board
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Appendix D – GTXI Buffer Board
The GTXI buffer board can be programmed to assign resources to
the ISA bus. This chapter explains how to assign resources (IRQ,
DMA, I/O, MEM) to the GT7700’s system controller, the GTXI’s
GTPC-7586 controller module, the host computer, or the GTXI
instrument platform.
The GTXI Buffer Board Registers
Resources are assigned by writing to special registers in the GTXI
system controller bridge board (GT7700) or buffer board (GTXI-
700).
Up to four boards can be used by a system (one buffer and three
extender boards). The user can select the I/O base address of these
boards by using a switch located on the board. Each board uses two
16 bit I/O addresses, with one for the Internal Address Register
(IAR) and the other for Data. Both are read and write. The board
base address can be set to one of the following values:
1. 178: 178 - IAR, 17A - Data.
2. 17C: 17C - IAR, 17E - Data.
3. 578: 578 - IAR, 57A - Data.
4. 57C: 57C - IAR, 57E - Data.
The IAR register is used to select and enable one of the buffer
internal registers. These are 16 bit registers that are used to assign
resources. All of the internal registers utilize 16 bit Read/Write
access although not all 16 bits are used. To read or write to/from
any buffer register, the internal address must be set and enabled first
using the IAR register. The register can then be transferred using
the Data address.
The following sections describe the IAR register and the board
internal registers. Each register is described by a table showing the
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