GE LOGIQ P5, Руководство по обслуживанию

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GE H
EALTHCARE
D
IRECTION
5394141, R
EVISION
5 LOGIQ™ P5 S
EVICE
M
ANUAL
Section 5-4 - Main Board Detail 5-15
5-4-2-5 Transmit Pulse Generation Block
The CTX in CL1TRX generate bipolar transmit pulse and have dual driver for each scan mode, for
example, low voltage driver for PWD or CFM and high voltage for B. This board has 64 channels
transmit signal drivers, Transmit Pulse Generator ASIC, control FPGA and so on. Transmit pulse are
generated by TPG2 ASIC. Each TPG2 ASIC makes 16 channels signals, so total 4 ASIC are used in
CTX in CL1TRX. All of control informations for pulse generation, pulse width, time delay of each channel
are come from SYSCONPM(SYSCONCM) in real time via Backplane. The control FPGA, TRBC FPGA
provide interface between SYSCONPM(SYSCONCM) and TPG2 ASICs and control operation
condition of CTX in CL1TRX Main items are
• TPG2 ASIC: A TPG2 ASIC can generate 16 channels logic level transmit pulse signal. This ASIC
use 2 phase 40MHz clocks for transmit delay control and pulse generation. 40Mhz operation clocks
are come from L1SYSCON assy via Backplane.
• Transmit Pulse Driver : TPG2 ASIC generated logic level signal for transmit pulse. So this signal
need to be expanded to high voltage signal. Driver circuit make logic level signal to high voltage
level signal.
• THV Switch : LOGIQ™ P5 system use dual transmit high voltage for transmit driver because B
mode and CFM mode use different voltage level of transmit pulse. So in duplex of triplex mode, B/
CFM or B/DOP, Low THV and High THV are switched in CTX in CL1TRX in real time.
• TRBC FPGA : This FPGA is located on L1BFC board interfacing with SYSCONPM(SYSCONCM)
and updating the TPG data in real time.
Figure 5-14 Tx pulse Generation Block Diagram
T P G 2
T X D riv e r_ H V L
(C T X O n ly )
T X D riv e r_ H V H
S
e
le
c
ti
o
n
B
u
ffe
r
T P G 2
T P G 2
T P G 2
6 4 c h
T X s ig n a l
fo r H V L
6 4 c h
T X s ig n a l
fo r H V H
T P G 2
C o n tro l S ig n a l
P
ro
b
e
In
te
rf
a
c
e
B
o
a
rd
B u ffe r e n a b le s ig n a l
to s e le c t T X D riv e r
T P G 2
T X D riv e r_ H V L
(C T X O n ly )
T X D riv e r_ H V H
S
e
le
c
ti
o
n
B
u
ffe
r
T P G 2
T P G 2
T P G 2
6 4 c h
T X s ig n a l
fo r H V L
6 4 c h
T X s ig n a l
fo r H V H
T P G 2
C o n tro l S ig n a l
P
ro
b
e
In
te
rf
a
c
e
B
o
a
rd
B u ffe r e n a b le s ig n a l
to s e le c t T X D riv e r