GR716-DS-UM, May 2019, Version 1.29
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GR716
4.3
System clock
The system clock is used to clock the processors, the AMBA buses, and all on-chip cores. The system
clock can be derived directly from input pin SYS_CLK or from the external pins SPWCLK via the
internal PLL.
The microcontroller includes an on-chip oscillator able to provide a 5 - 25 MHz internal clock. This
clock can optionally be used to generate other on-chip clocks for the processor system, SpaceWire and
MIL-STD-1553B. To be able to provide a high-accuracy reference clock a crystal oscillator is imple-
mented, where the active oscillator part is implemented on-chip and the crystal is to be connected
externally. Alternatively, any arbitrary clock source can be applied as a logic-level clock signal on one
of the crystal-interface input pins.
The output from the on-chip oscillator needs to be connected outside the microcontroller device if to
used.
4.3.1
System clock source selection
By selecting a system clock source and/or system clock divisor for the system. The core system can be
configured to run slower or faster than the external system clock. Special care needs to be taken when
switching system clock source in order to switch to a existing clock source.
The device will automatically switch back to use the default system input clock during reset and if the
system tries to switch to a disabled clock source.
4.4
SpaceWire clock
The clock used for the SpaceWire link receiver and transmitter logic is taken from the dedicated
SpaceWire clock pin SPW_CLK either directly, or multiplied with a PLL, depending on the value of
the configuration register for the SpaceWire clock mux and PLL. See chapter 10 for more informa-
tion.
4.5
MIL-STD-1553B clock
The 20 MHz clock for the MIL-STD-1553B codec is taken from the dedicated pin gr1553b_clk or
from the external SPWCLK signal configured via the internal register.
4.5.1
Using PLL clock as input clock for 1553B interface
The PLL output clock frequency can be used to generate a MIL-STD-1553B clock. The MIL-STD-
1553B clock can be generated by divide the PLL frequency by 20, see section 10 for details on the
MIL-STD-1553B clock divisor registers.
4.6
PacketWire RX Clock
The external clock input for the PacketWire clock receiver is available via the IO mux, see table 2.6.
For more information about the PacketWire see section 31.
The PacketWire RX clock can also be generated from internal PacketWire TX clock. The PacketWire
TX clock is selected as input to the PacketWire RX clock when the PacketWire is deselected in the IO
mux.
4.7
ADC Clock
ADC clock shall match the sampling speed required by the application. Maximum sampling speed is
200 Ksps i.e. maximum ADC clock frequency is 2 MHz. The ADC clock is configured via registers,
see 12.