16
32072H–AVR32–10/2012
AT32UC3A3
SDA10
SDRAM Address 10 Line
Output
SDCK
SDRAM Clock
Output
SDCKE
SDRAM Clock Enable
Output
SDWE
SDRAM Write Enable
Output
Low
MultiMedia Card Interface - MCI
CLK
Multimedia Card Clock
Output
CMD[1:0]
Multimedia Card Command
I/O
DATA[15:0]
Multimedia Card Data
I/O
Memory Stick Interface - MSI
SCLK
Memory Stick Clock
Output
BS
Memory Stick Command
I/O
DATA[3:0]
Multimedia Card Data
I/O
Serial Peripheral Interface - SPI0, SPI1
MISO
Master In Slave Out
I/O
MOSI
Master Out Slave In
I/O
NPCS[3:0]
SPI Peripheral Chip Select
I/O
Low
SPCK
Clock
Output
Synchronous Serial Controller - SSC
RX_CLOCK
SSC Receive Clock
I/O
RX_DATA
SSC Receive Data
Input
RX_FRAME_SYNC
SSC Receive Frame Sync
I/O
TX_CLOCK
SSC Transmit Clock
I/O
TX_DATA
SSC Transmit Data
Output
TX_FRAME_SYNC
SSC Transmit Frame Sync
I/O
Timer/Counter - TC0, TC1
A0
Channel 0 Line A
I/O
A1
Channel 1 Line A
I/O
A2
Channel 2 Line A
I/O
Table 3-6.
Signal Description List
Signal Name
Function
Type
Active
Level
Comments
Содержание AT32UC3A3128
Страница 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Страница 260: ...260 32072H AVR32 10 2012 AT32UC3A3 5 2560 3071 6 3072 3583 7 3584 4095 Bit Index n Sector Boundaries...
Страница 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Страница 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Страница 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...