842
32072H–AVR32–10/2012
AT32UC3A3
0x044
Interrupt Enable Register
IER
Write-only
0x00000000
0x048
Interrupt Disable Register
IDR
Write-only
0x00000000
0x04C
Interrupt Mask Register
IMR
Read-only
0x00000000
0x050
DMA Configuration Register
DMA
Read-write
0x00000000
0x054
Configuration Register
CFG
Read-write
0x00000000
0x0E4
Write Protection Mode Register
WPMR
Read-write
0x00000000
0x0E8
Write Protection Status Register
WPSR
Read-only
0x00000000
0x0FC
Version Register
VERSION
Read-only
-
(1)
0x200-0x3FFC
FIFO Memory Aperture
–
Read-write
0x00000000
1.
The reset value are device specific. Please refer to the Module Configuration section at the end of this chapter.
Table 31-7.
MCI Register Memory Map
Offset
Register
Name
Access
Reset
Содержание AT32UC3A3128
Страница 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Страница 260: ...260 32072H AVR32 10 2012 AT32UC3A3 5 2560 3071 6 3072 3583 7 3584 4095 Bit Index n Sector Boundaries...
Страница 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Страница 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Страница 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...