UG-707
ADV8005 Hardware Reference Manual
timer6_irq_cnt[31:0]
, SPI Device Address 0x0B (TIMER),
Address 0x5E[7:0]; Address 0x5F[7:0]; Address 0x60[7:0]; Address 0x61[7:0] (Read Only)
The number of times the timer 6 interrupt was generated.
timer7_irq_cnt[31:0]
, SPI Device Address 0x0B (TIMER),
Address 0x62[7:0]; Address 0x63[7:0]; Address 0x64[7:0]; Address 0x65[7:0] (Read Only)
The number of times the timer 7 interrupt was generated.
timer8_irq_cnt[31:0]
, SPI Device Address 0x0B (TIMER),
Address 0x66[7:0]; Address 0x67[7:0]; Address 0x68[7:0]; Address 0x69[7:0] (Read Only)
The number of times the timer 8 interrupt was generated.
4.2.7.
OSD Scaler
The
OSD core contains an arbitrary resolution conversion scaler. This scaler performs a scaling function if the OSD resolution inside
the DDR2 memory is different from the output video. If the output video is interlaced, the OSD scaler can change the progressive OSD data to
interlaced data for blending. As mentioned in Section
, the OSD scaler also guarantees the correct synchronization of OSD data and input
video data.
4.2.8.
OSD Master/Slave SPI Interface
The
OSD requires an external DDR2 memory and some configuration done to the OSD SPI registers in order to work. OSD data can
be written to the DDR2 memory on startup by the
. In addition, to dynamically configure the OSD, configuration registers need to be
controlled. Note that all this configuration is taken care of by
Blimp OSD
and the firmware, so a detailed explanation of the DDR2 SPI interface
is not provided. For this reason, this section covers only top level information (enable/disable, muxing configuration of the OSD through the IO
Map I
2
C registers). The SPI slave hardware interface is also described in this section.
4.2.8.1.
Overview
It is possible to access the DDR2 and OSD SPI registers in one of two ways:
•
The
SPI master interface (serial port 2) can pull in resource data to DDR2 memory from an external SPI flash memory, as
shown in
•
The system MCU (SPI master) can write OSD data into DDR2 memory using the
SPI slave interface (serial port 1), as shown
in
Figure 86: Data Loaded from SPI Flash Through
SPI Master Interface
OSD_CORE
SPI
Slave
Config
Register
DDR2 Memory
I2C
Slave
FLASH
MEM
System
Controller(CPU)
SPI
Master
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