ADV8005 Hardware Reference Manual
UG-707
Figure 89: SPI Slave Interface Timing and Data Format
The CPOL/CPHA can be configured through the I
2
C registers described below.
spi_slave_cpol
, IO Map,
Address 0x1A14[3]
This bit is used to select the SPI slave clock polarity.
Function
spi_slave_cpol
Description
0
Idle state, clock is low
1 (default)
Idle state, clock is high
spi_slave_cpha
, IO Map,
Address 0x1A14[2]
This bit is used to select the SPI slave clock phase.
Function
spi_slave_cpha
Description
0
Negedge used
1 (default)
Posedge used
, the LSB bit of the device address sets whether the access is read or write.
The SPI subaddress is an 8-bit field and the data is also 8 bits wide with MSB sent first and LSB last.
The SPI slave readback has both delay mode and no delay mode, and it is controlled by the following SPI register.
slave_delay_mode
, SPI Device Address 0x0A,
Address 0x85[0]
SPI slave read data MISO1 output delay mode.
Function
slave_delay_mode
Description
0
No delay
1
Delay 8 clocks (8 bits dummy data)
In no delay mode, counting from the last rising edge of SCK1 (send subaddress) to the first falling edge of SCK1 (send out MISO1), there are
about 10 system clock delays. Assuming the SCK1 is 50% duty cycle, only when SCK1 is slower than system clock/20 = 162 MHz/20 = 8.1 MHz,
can no delay mode work normally.
If SCK1 is slower than 6 MHz, no delay mode can be set.
The
features an analog antiglitch used to reject glitches on SCK1 (SPI slave). There are three modes of operation of this filter: bypass,
2 ns glitch rejection, and 5ns glitch rejection. The 2 ns glitch rejection mode should be used for clock frequencies between 10MHz and 40 MHz.
The 5 ns glitch rejection mode should be used for clock frequencies of less than 10 MHz.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Device Address
W/R
Sub Address
Data in 0
Data in 1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Data out 0
Data out 1
Dummy byte
Data out 0
CS1
SCK1
MOSI1
MISO1
MISO1
Delay Mode
No Delay Mode
SCK1
SCK1
SCK1
CPOL CPHA
0
0
0
1
1
0
1
1
Rev. A | Page 179 of 317
