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ADV8005 Hardware Reference Manual UG-707
Figure 80: ADV8005 External Sync Mode Block Diagram
3.6.1. Functional Description
The ADV8005 compares the phase difference between the MAS_VS and the internally generated VS out as shown in Figure 80 . The phase
difference is measured using a fixed crystal clock running at 27MHz. The phase difference between the input and output VS signals constitutes
an error which must be reduced to zero in order for the outputs to be locked together. This is achieved by varying the output clock in order to
change the period of the output VS. Once the error is reduced to 0 the output video and timing will be locked to the external master. This locking
process can take from 0 – 5 seconds. As the external master sync will always be present and stable this will constitute a start-up condition and
once locked will remain locked. If the input video source is changed at a future time this will not disrupt the relationship between the external
master sync and output timing.
The video output will be locked to /-2 Xtal clock cycles of the externally provided master sync. In the worst case scenario where 4k2k is
being output on a 297MHz clock the potential pixel difference is +/-22pixels. For 1080p outputs this variation drops to +/-11 pixels. This
difference between outputs can be eliminated using a small FIFO. Note that this resynchronisation block will also eliminate any cable delay
differences between different
ADV8005 systems.
It is important to note that if the output timing is being locked to the external MAS_VS reference it cannot be locked to the input timing at the same
time. This means that if there are frequency differences between the external timing and input timing provided to the
ADV8005 , input frames of video
will be either dropped or repeated to account for these differences and keep the output timing locked to the external master reference (MAS_VS).
It is also possible to add a track_offset via pvsp_track_offset[20:0] to the phase error that is eliminated. This allows the
ADV8005
to either
advance or delay the output timing versus the reference timing, which is externally provided on the MAS_VS ball in this case. If there is not
the possibility of providing an advanced external sync versus the desired output timing then an advance can be programmed to individual
ADV8005
parts in order to achieve the same effect.
pvsp_track_offset[20:0] , IO Map, Address 0x1A94[4:0]; Address 0x1A95[7:0]; Address 0x1A96[7:0]
This signal is used to program the delay on the output timing of VSyncs from the Primary VSP.
Function
pvsp_track_offset[20:0] Description
0  input and output VSync coincident
1 1 Xtal clk between input and output VSync
MAS sync mode using frame track can be enabled using pvsp_frtrk_mas_mode_en.
PVSP
FRAME TRACK CLK_GEN
XTAL_REF
VS_MAS
VS_PVSP
PVSP_CLK_PERIOD
PVSP_CLK
TTL OUTPUT
TX1 OUTPUT
TX2 OUTPUT
HS_PVSP
DE_PVSP
DATA_PVSP[36:0]
M_P2I
HS_MAS
FIELD_DETECT
O_EXT_ODD_FLD
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