ADV8005 Hardware Reference Manual
UG-707
3.5.
HORIZONTAL PRE-SCALER
A Horizontal Pre-Scaler (HPS) has been implemented on the
to extend the scaling functions of the
. The PVSP and SVSP
are limited in the pixel clock frequencies and line lengths which they can handle. The HPS block has been designed for scaling between
determined video formats as follows:
1.
Down-conversion of video standards with pixel clocks greater than 162MHz and/or more than 2048 pixels/line. Typical use would be
downscaling to video modes with pixel clocks of less than 162MHz, e.g. 4K@30 to 1080p@60.
2.
Up-conversion of video standards with pixel clocks greater than 162MHz and/or more than 1920 pixels/line (but less than 3840) to
video modes with pixel clocks greater than 162MHz, e.g. VESA 2048x1152 (162MHz) to 4K, VESA 1920x1440 (234MHz) to 4K.
3.
Conversion of video standards with pixel clocks greater than 162MHz and more than 3840 pixels/lines. Typical use would be converting
between different 4K timings, e.g. 4K@24 to 4K@24 SMPTE.
4.
3D to 2D conversion of some video modes.
5.
Bypassing the downsampling block within the HPS, can be used just as an additional high-frequency filter to the one provided by the
P/SVSP.
Video may be routed in to the HPS from any of the
inputs using hps_inp_sel. The output from the HPS can be routed to either the
hps_inp_sel[3:0]
, IO Map,
Address 0x1A09[7:4]
This signal is used to select the video source for the Horizontal pre-scaler (HPS) block
Function
hps_inp_sel[3:0]
Description
0x00 (default)
From Primary Input Channel
0x01
From Secondary Input Channel
0x02
From RX Input
0x03
From Internal OSD Blend 1
Figure 74 HPS Block Diagram
The HPS block provides two separate low pass filters which can be selected using hps_filt_bypass. The HPS filter can be powered down using
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