UG-707
ADV8005 Hardware Reference Manual
LRCLK
SCLK
DATA
LEFT
RIGHT
LSB
MSB
MSB
LSB
32 Clock Slots
32 Clock Slots
Figure 100: Timing of Standard I2S Stream Input to ADV8005
LRCLK
SCLK
DATA
LEFT
RIGHT
LSB
MSB
MSB
LSB
32 Clock Slots
32 Clock Slots
MSB
MSB
MSB
MSB
MSB-1
MSB
MSB
MSB-1
MSB extended
MSB extended
Figure 101: Timing for Right-Justified I2S Stream Input to ADV8005
LRCLK
SCLK
DATA
LEFT
RIGHT
LSB
MSB
MSB
LSB
32 Clock Slots
32 Clock Slots
Figure 102: Timing for Left-Justified I2S Stream Input to ADV8005
LRCLK
SCLK
DATA
LEFT
RIGHT
LSB
left
MSB
left
MSB
right
LSB
left
16 Clock Slots
16 Clock Slots
LSB
right
Figure 103: Timing for I2S Stream in 32-bit Mode
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